git.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/config_space_header.vhd

   1 -- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
   2
   3 LIBRARY ieee;
   4
   5 USE ieee.std_logic_1164.ALL;
   6 USE ieee.numeric_std.ALL;
   7
   8
   9 entity CONFIG_SPACE_HEADER is
  10         Port ( AD_REG : In std_logic_vector (31 downto 0);
  11                ADDR_REG : In std_logic_vector (31 downto 0);
  12                CBE_REGn : In std_logic_vector (3 downto 0);
  13                CF_RD_COM : In std_logic;
  14                CF_WR_COM : In std_logic;
  15                IRDY_REGn : In std_logic;
  16                PCI_CLOCK : In std_logic;
  17                PCI_RSTn : In std_logic;
  18                PERR : In std_logic;
  19                REVISION_ID : In std_logic_vector (7 downto 0);
  20                SERR : In std_logic;
  21                TRDYn : In std_logic;
  22                VENDOR_ID : In std_logic_vector (15 downto 0);
  23                CONF_DATA : Out std_logic_vector (31 downto 0);
  24                CONF_DATA_04H : Out std_logic_vector (31 downto 0);
  25                CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
  26 end CONFIG_SPACE_HEADER;
  27
  28 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
  29
  30         constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
  31
  32         SIGNAL gnd : std_logic := '0';
  33         SIGNAL vcc : std_logic := '1';
  34
  35         signal CONF_WR_04H : std_logic;
  36         signal CONF_WR_10H : std_logic;
  37         signal CONF_WR_3CH : std_logic;
  38         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
  39         signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
  40         signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
  41         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
  42         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
  43         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
  44
  45         component CONFIG_MUX_0
  46                 Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
  47                        CONF_DATA_04H : In std_logic_vector (31 downto 0);
  48                        CONF_DATA_08H : In std_logic_vector (31 downto 0);
  49                        CONF_DATA_10H : In std_logic_vector (31 downto 0);
  50                        CONF_DATA_3CH : In std_logic_vector (31 downto 0);
  51                        READ_SEL : In std_logic_vector (2 downto 0);
  52                        CONF_DATA : Out std_logic_vector (31 downto 0) );
  53         end component;
  54
  55         component CONFIG_RD_0
  56                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
  57                        CF_RD_COM : In std_logic;
  58                        READ_SEL : Out std_logic_vector (2 downto 0) );
  59         end component;
  60
  61         component CONFIG_WR_0
  62                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
  63                        CF_WR_COM : In std_logic;
  64                        IRDY_REGn : In std_logic;
  65                        TRDYn : In std_logic;
  66                        CONF_WR_04H : Out std_logic;
  67                        CONF_WR_10H : Out std_logic;
  68                        CONF_WR_3CH : Out std_logic );
  69         end component;
  70
  71         component CONFIG_3CH
  72                 Port ( AD_REG : In std_logic_vector (31 downto 0);
  73                        CBE_REGn : In std_logic_vector (3 downto 0);
  74                        CONF_WR_3CH : In std_logic;
  75                        PCI_CLOCK : In std_logic;
  76                        PCI_RSTn : In std_logic;
  77                        CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
  78         end component;
  79
  80         component CONFIG_10H
  81                 Port ( AD_REG : In std_logic_vector (31 downto 0);
  82                        CBE_REGn : In std_logic_vector (3 downto 0);
  83                        CONF_WR_10H : In std_logic;
  84                        PCI_CLOCK : In std_logic;
  85                        PCI_RSTn : In std_logic;
  86                        CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
  87         end component;
  88
  89         component CONFIG_08H
  90                 Port ( REVISION_ID : In std_logic_vector (7 downto 0);
  91                        CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
  92         end component;
  93
  94         component CONFIG_04H
  95                 Port ( AD_REG : In std_logic_vector (31 downto 0);
  96                        CBE_REGn : In std_logic_vector (3 downto 0);
  97                        CONF_WR_04H : In std_logic;
  98                        PCI_CLOCK : In std_logic;
  99                        PCI_RSTn : In std_logic;
 100                        PERR : In std_logic;
 101                        SERR : In std_logic;
 102                        CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
 103         end component;
 104
 105 begin
 106         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
 107
 108         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
 109         CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
 110
 111         I10 : CONFIG_MUX_0
 112         Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
 113         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
 114         CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
 115         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
 116         CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
 117         READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
 118         CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
 119         I9 : CONFIG_RD_0
 120         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
 121                    CF_RD_COM=>CF_RD_COM,
 122                    READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
 123         I8 : CONFIG_WR_0
 124         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
 125                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
 126                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
 127                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
 128         I6 : CONFIG_3CH
 129         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 130         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
 131         CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
 132         PCI_RSTn=>PCI_RSTn,
 133         CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
 134         I5 : CONFIG_10H
 135         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 136         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
 137         CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
 138         PCI_RSTn=>PCI_RSTn,
 139         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
 140         I4 : CONFIG_08H
 141         Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
 142         CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
 143         I2 : CONFIG_04H
 144         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 145         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
 146         CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
 147         PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
 148         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
 149
 150 end SCHEMATIC;