+= use xilinx block ram for ethernet
[raggedstone] / dhwk_old / dhwk.prj
1 verilog work "source/sync.v"
2 verilog work "source/pcidec.v"
3 verilog work "source/pcidmux.v"
4 verilog work "source/generic_fifo_sc_a.v"
5 verilog work "source/generic_dpram.v"
6 verilog work "source/wb_fifo.v"
7
8 verilog work "source/pciwbsequ.v"
9 verilog work "source/pcipargen.v"
10
11 vhdl work "source/pciwbsequ.vhd"
12 vhdl work "source/pfs.vhd"
13 vhdl work "source/new_pciregs.vhd"
14 vhdl work "source/pcipargen.vhd"
15 vhdl work "source/new_pci32tlite.vhd"
16 vhdl work "source/top_dhwk.vhd"
17 vhdl work "source/heartbeat.vhd"
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