make clean makes really clean now
[raggedstone] / dhwk / fifo.xco
1 ##############################################################
2 #
3 # Xilinx Core Generator version J.30
4 # Date: Sat Mar 10 21:20:43 2007
5 #
6 ##############################################################
7 #
8 # This file contains the customisation parameters for a
9 # Xilinx CORE Generator IP GUI. It is strongly recommended
10 # that you do not manually alter this file as it may cause
11 # unexpected and unsupported behavior.
12 #
13 ##############################################################
14 #
15 # BEGIN Project Options
16 SET addpads = False
17 SET asysymbol = False
18 SET busformat = BusFormatAngleBracketNotRipped
19 SET createndf = False
20 SET designentry = VHDL
21 SET device = xc3s1500
22 SET devicefamily = spartan3
23 SET flowvendor = Other
24 SET formalverification = False
25 SET foundationsym = False
26 SET implementationfiletype = Ngc
27 SET package = fg456
28 SET removerpms = False
29 SET simulationfiles = Behavioral
30 SET speedgrade = -4
31 SET verilogsim = False
32 SET vhdlsim = True
33 # END Project Options
34 # BEGIN Select
35 SELECT Fifo_Generator family Xilinx,_Inc. 3.2
36 # END Select
37 # BEGIN Parameters
38 CSET almost_empty_flag=true
39 CSET almost_full_flag=true
40 CSET component_name=fifo_generator_v3_2
41 CSET data_count=false
42 CSET data_count_width=12
43 CSET dout_reset_value=0
44 CSET empty_threshold_assert_value=2
45 CSET empty_threshold_negate_value=3
46 CSET fifo_implementation=Common_Clock_Block_RAM
47 CSET full_threshold_assert_value=2048
48 CSET full_threshold_negate_value=2047
49 CSET input_data_width=8
50 CSET input_depth=4096
51 CSET output_data_width=8
52 CSET output_depth=4096
53 CSET overflow_flag=false
54 CSET overflow_sense=Active_High
55 CSET performance_options=Standard_FIFO
56 CSET programmable_empty_type=No_Programmable_Empty_Threshold
57 CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
58 CSET read_clock_frequency=100
59 CSET read_data_count=false
60 CSET read_data_count_width=12
61 CSET reset_pin=true
62 CSET reset_type=Asynchronous_Reset
63 CSET underflow_flag=false
64 CSET underflow_sense=Active_High
65 CSET use_extra_logic=false
66 CSET valid_flag=false
67 CSET valid_sense=Active_High
68 CSET write_acknowledge_flag=false
69 CSET write_acknowledge_sense=Active_High
70 CSET write_clock_frequency=100
71 CSET write_data_count=false
72 CSET write_data_count_width=12
73 # END Parameters
74 GENERATE
75 # CRC: c795162c
76
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