git.zerfleddert.de Git - raggedstone/blob - dhwk/source/config_10h.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: CONFIG_10H.VHD
   5
   6 library IEEE;
   7 use IEEE.std_logic_1164.all;
   8
   9 entity CONFIG_10H is
  10         port
  11         (
  12         PCI_CLOCK                       :in             std_logic;
  13         PCI_RSTn                        :in             std_logic;
  14         AD_REG                          :in             std_logic_vector(31 downto 0);
  15         CBE_REGn                        :in             std_logic_vector( 3 downto 0);
  16         CONF_WR_10H             :in             std_logic;
  17         CONF_DATA_10H   :out    std_logic_vector(31 downto 0)
  18         );
  19 end entity CONFIG_10H;
  20
  21 architecture CONFIG_10H_DESIGN of CONFIG_10H is
  22
  23         signal          CONF_BAS_ADDR_REG       :std_logic_vector(31 downto  0);
  24
  25 begin
  26
  27 --*******************************************************************
  28 --***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******
  29 --*******************************************************************
  30
  31         CONF_BAS_ADDR_REG(1 downto 0) <= "01"   ;-- Base Address Register for "I/O"
  32         CONF_BAS_ADDR_REG(3 downto 2)   <= "00" ;-- IO Bereich = 16 BYTE
  33
  34         process (PCI_CLOCK,PCI_RSTn)
  35         begin
  36
  37 --      if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
  38                 if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
  39
  40                 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
  41
  42                         if                      CONF_WR_10H      = '1'and CBE_REGn(3) = '0' then
  43
  44                                                         CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
  45
  46                                 else    CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
  47                         end if;
  48
  49                         if                      CONF_WR_10H      = '1'and CBE_REGn(2) = '0' then
  50
  51                                                         CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
  52
  53                                 else    CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
  54                         end if;
  55
  56                         if                      CONF_WR_10H      = '1'and CBE_REGn(1) = '0' then
  57
  58                                                         CONF_BAS_ADDR_REG(15 downto  8) <= AD_REG(15 downto  8);
  59
  60                                 else    CONF_BAS_ADDR_REG(15 downto  8) <= CONF_BAS_ADDR_REG(15 downto  8);
  61                         end if;
  62
  63 --                      if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then
  64 --
  65 --                                                      CONF_BAS_ADDR_REG( 7 downto  2) <= AD_REG( 7 downto  2);
  66 --
  67 --                              else    CONF_BAS_ADDR_REG( 7 downto  2) <= CONF_BAS_ADDR_REG( 7 downto  2);
  68 --                      end if;
  69
  70                         if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then
  71
  72                                                         CONF_BAS_ADDR_REG( 7 downto  4) <= AD_REG( 7 downto  4);
  73
  74                                 else    CONF_BAS_ADDR_REG( 7 downto  4) <= CONF_BAS_ADDR_REG( 7 downto  4);
  75                         end if;
  76
  77
  78                 end if;
  79
  80         end process;
  81
  82         CONF_DATA_10H   <= CONF_BAS_ADDR_REG;
  83
  84 end architecture CONFIG_10H_DESIGN;
  85
  86
  87