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1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name: pci_target32_sm.v ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Tadej Markovic, tadej@opencores.org ////
10 //// ////
11 //// All additional information is avaliable in the README.txt ////
12 //// file. ////
13 //// ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 //// ////
17 //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
18 //// ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
23 //// ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
29 //// ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
34 //// details. ////
35 //// ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
39 //// ////
40 //////////////////////////////////////////////////////////////////////
41 //
42 // CVS Revision History
43 //
44 // $Log: pci_target32_sm.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
46 // add shit
47 //
48 // Revision 1.11 2003/12/19 11:11:30 mihad
49 // Compact PCI Hot Swap support added.
50 // New testcases added.
51 // Specification updated.
52 // Test application changed to support WB B3 cycles.
53 //
54 // Revision 1.10 2003/08/08 16:36:33 tadejm
55 // Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
56 //
57 // Revision 1.9 2003/01/27 16:49:31 mihad
58 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
59 //
60 // Revision 1.8 2003/01/21 16:06:56 mihad
61 // Bug fixes, testcases added.
62 //
63 // Revision 1.7 2002/09/24 19:09:17 mihad
64 // Number of state bits define was removed
65 //
66 // Revision 1.6 2002/09/24 18:30:00 mihad
67 // Changed state machine encoding to true one-hot
68 //
69 // Revision 1.5 2002/08/22 09:07:06 mihad
70 // Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
71 //
72 // Revision 1.4 2002/02/19 16:32:37 mihad
73 // Modified testbench and fixed some bugs
74 //
75 // Revision 1.3 2002/02/01 15:25:12 mihad
76 // Repaired a few bugs, updated specification, added test bench files and design document
77 //
78 // Revision 1.2 2001/10/05 08:14:30 mihad
79 // Updated all files with inclusion of timescale file for simulation purposes.
80 //
81 // Revision 1.1.1.1 2001/10/02 15:33:47 mihad
82 // New project directory structure
83 //
84 //
85
86 `include "pci_constants.v"
87
88 // synopsys translate_off
89 `include "timescale.v"
90 // synopsys translate_on
91
92 module pci_target32_sm
93 (
94 // system inputs
95 clk_in,
96 reset_in,
97 // master inputs
98 pci_frame_in,
99 pci_irdy_in,
100 pci_idsel_in,
101 pci_frame_reg_in,
102 pci_irdy_reg_in,
103 pci_idsel_reg_in,
104 // target response outputs
105 pci_trdy_out,
106 pci_stop_out,
107 pci_devsel_out,
108 pci_trdy_en_out,
109 pci_stop_en_out,
110 pci_devsel_en_out,
111 ad_load_out,
112 ad_load_on_transfer_out,
113 // address, data, bus command, byte enable in/outs
114 pci_ad_reg_in,
115 pci_ad_out,
116 pci_ad_en_out,
117 pci_cbe_reg_in,
118 pci_cbe_in,
119 bckp_trdy_en_in,
120 bckp_devsel_in,
121 bckp_trdy_in,
122 bckp_stop_in,
123 pci_trdy_reg_in,
124 pci_stop_reg_in,
125
126 // backend side of state machine with control signals to pci_io_mux ...
127 address_out,
128 addr_claim_in,
129 bc_out,
130 bc0_out,
131 data_out,
132 data_in,
133 be_out,
134 next_be_out,
135 req_out,
136 rdy_out,
137 addr_phase_out,
138 bckp_devsel_out,
139 bckp_trdy_out,
140 bckp_stop_out,
141 last_reg_out,
142 frame_reg_out,
143 fetch_pcir_fifo_out,
144 load_medium_reg_out,
145 sel_fifo_mreg_out,
146 sel_conf_fifo_out,
147 load_to_pciw_fifo_out,
148 load_to_conf_out,
149 same_read_in,
150 norm_access_to_config_in,
151 read_completed_in,
152 read_processing_in,
153 target_abort_in,
154 disconect_wo_data_in,
155 disconect_w_data_in,
156 target_abort_set_out,
157 pciw_fifo_full_in,
158 pcir_fifo_data_err_in,
159 wbw_fifo_empty_in,
160 wbu_del_read_comp_pending_in,
161 wbu_frame_en_in
162
163 ) ;
164
165 /*----------------------------------------------------------------------------------------------------------------------
166 Various parameters needed for state machine and other stuff
167 ----------------------------------------------------------------------------------------------------------------------*/
168 parameter S_IDLE = 3'b001 ;
169 parameter S_WAIT = 3'b010 ;
170 parameter S_TRANSFERE = 3'b100 ;
171
172
173 /*==================================================================================================================
174 System inputs.
175 ==================================================================================================================*/
176 // PCI side clock and reset
177 input clk_in,
178 reset_in ;
179
180
181 /*==================================================================================================================
182 PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
183 module. Enables are separate signals.
184 ==================================================================================================================*/
185 // master inputs
186 input pci_frame_in,
187 pci_irdy_in,
188 pci_idsel_in ;
189 input pci_frame_reg_in,
190 pci_irdy_reg_in,
191 pci_idsel_reg_in ;
192
193 // target response outputs
194 output pci_trdy_out,
195 pci_stop_out,
196 pci_devsel_out ;
197 output pci_trdy_en_out,
198 pci_stop_en_out,
199 pci_devsel_en_out ;
200 output ad_load_out ;
201 output ad_load_on_transfer_out ;
202 // address, data, bus command, byte enable in/outs
203 input [31:0] pci_ad_reg_in ;
204 output [31:0] pci_ad_out ;
205 output pci_ad_en_out ;
206 input [3:0] pci_cbe_reg_in ;
207 input [3:0] pci_cbe_in ;
208 input bckp_trdy_en_in ;
209 input bckp_devsel_in ;
210 input bckp_trdy_in ;
211 input bckp_stop_in ;
212 input pci_trdy_reg_in ;
213 input pci_stop_reg_in ;
214
215
216 /*==================================================================================================================
217 Other side of PCI Target state machine
218 ==================================================================================================================*/
219 // Data, byte enables, bus commands and address ports
220 output [31:0] address_out ; // current request address output - registered
221 input addr_claim_in ; // current request address claim input
222 output [3:0] bc_out ; // current request bus command output - registered
223 output bc0_out ; // current cycle RW signal output
224 input [31:0] data_in ; // for read operations - current dataphase data input
225 output [31:0] data_out ; // for write operations - current request data output - registered
226 output [3:0] be_out ; // current dataphase byte enable outputs - registered
227 output [3:0] next_be_out ; // next dataphase byte enable outputs - NOT registered
228 // Port connection control signals from PCI FSM
229 output req_out ; // Read is requested to WB master
230 output rdy_out ; // DATA / ADDRESS selection when read or write - registered
231 output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
232 output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent
233 output bckp_trdy_out ; // TRDY output (which is registered) equivalent
234 output bckp_stop_out ; // STOP output (which is registered) equivalent
235 output last_reg_out ; // Indicates last data phase - registered
236 output frame_reg_out ; // FRAME output signal - registered
237 output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side
238 output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
239 output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
240 output sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO"
241 output load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO
242 output load_to_conf_out ; // Write enable to Configuration space registers
243
244
245 /*==================================================================================================================
246 Status
247 ==================================================================================================================*/
248 input same_read_in ; // Indicates the same read request (important when read is finished on WB side)
249 input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands
250 input read_completed_in ; // Indicates that read request is completed on WB side
251 input read_processing_in ; // Indicates that read request is processing on WB side
252 input target_abort_in ; // Indicates target abort termination
253 input disconect_wo_data_in ; // Indicates disconnect without data termination
254 input disconect_w_data_in ; // Indicates disconnect with data termination
255 input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full
256 input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO
257 input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
258 input wbu_del_read_comp_pending_in ; // Indicates that WB SÈAVE UNIT has a delayed read pending
259 input wbu_frame_en_in ; // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if
260 // address on PCI bus is also claimed by decoder in this PCI TARGET UNIT
261 output target_abort_set_out ; // Signal used to be set in configuration space registers
262
263 /*==================================================================================================================
264 END of input / output PORT DEFINITONS !!!
265 ==================================================================================================================*/
266
267 // Delayed frame signal for determining the address phase
268 reg previous_frame ;
269 // Delayed read completed signal for preparing the data from pcir fifo
270 reg read_completed_reg ;
271 // Delayed disconnect with/without data for stop loading data to PCIW_FIFO
272 //reg disconect_wo_data_reg ;
273
274 wire config_disconnect ;
275 wire disconect_wo_data = disconect_wo_data_in || config_disconnect ;
276 wire disconect_w_data = disconect_w_data_in ;
277 // Delayed frame signal for determining the address phase!
278 always@(posedge clk_in or posedge reset_in)
279 begin
280 if (reset_in)
281 begin
282 previous_frame <= #`FF_DELAY 1'b0 ;
283 read_completed_reg <= #`FF_DELAY 1'b0 ;
284 end
285 else
286 begin
287 previous_frame <= #`FF_DELAY pci_frame_reg_in ;
288 read_completed_reg <= #`FF_DELAY read_completed_in ;
289 end
290 end
291
292 // Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU)
293 wire addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ;
294
295 `ifdef HOST
296 `ifdef NO_CNF_IMAGE
297 // Wire tells when there is configuration (read or write) command with IDSEL signal active
298 wire config_access = 1'b0 ;
299 // Write and read progresses are used for determining next state
300 wire write_progress = ( (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
301 (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
302 wire read_progress = ( (read_completed_in && wbw_fifo_empty_in) ) ;
303 `else
304 // Wire tells when there is configuration (read or write) command with IDSEL signal active
305 wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x)
306 (pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle
307
308 // Write and read progresses are used for determining next state
309 wire write_progress = ( (norm_access_to_config_in) ||
310 (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
311 (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
312 wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
313 (read_completed_in && wbw_fifo_empty_in) ) ;
314 `endif
315 `else
316 // Wire tells when there is configuration (read or write) command with IDSEL signal active
317 wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x)
318 (pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle
319
320 // Write and read progresses are used for determining next state
321 wire write_progress = ( (norm_access_to_config_in) ||
322 (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
323 (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
324 wire read_progress = ( (~read_completed_in && norm_access_to_config_in) ||
325 (read_completed_in && wbw_fifo_empty_in) ) ;
326 `endif
327
328 // Signal for loading data to medium register from pcir fifo when read completed from WB side!
329 wire prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ;
330
331 // Write allowed to PCIW_FIFO
332 wire write_to_fifo = ((read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
333 (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in)) ;
334 // Read allowed from PCIR_FIFO
335 wire read_from_fifo = (read_completed_in && wbw_fifo_empty_in) ;
336 `ifdef HOST
337 `ifdef NO_CNF_IMAGE
338 // Read request is allowed to be proceed regarding the WB side
339 wire read_request = (~read_completed_in && ~read_processing_in) ;
340 `else
341 // Read request is allowed to be proceed regarding the WB side
342 wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
343 `endif
344 `else
345 // Read request is allowed to be proceed regarding the WB side
346 wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
347 `endif
348
349 // Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period
350 reg rw_cbe0 ;
351 reg wr_progress ;
352 reg rd_progress ;
353 reg rd_from_fifo ;
354 reg rd_request ;
355 reg wr_to_fifo ;
356 reg same_read_reg ;
357
358 always@(posedge clk_in or posedge reset_in)
359 begin
360 if (reset_in)
361 begin
362 rw_cbe0 <= #`FF_DELAY 1'b0 ;
363 wr_progress <= #`FF_DELAY 1'b0 ;
364 rd_progress <= #`FF_DELAY 1'b0 ;
365 rd_from_fifo <= #`FF_DELAY 1'b0 ;
366 rd_request <= #`FF_DELAY 1'b0 ;
367 wr_to_fifo <= #`FF_DELAY 1'b0 ;
368 same_read_reg <= #`FF_DELAY 1'b0 ;
369 end
370 else
371 begin
372 if (addr_phase)
373 begin
374 rw_cbe0 <= #`FF_DELAY pci_cbe_reg_in[0] ;
375 wr_progress <= #`FF_DELAY write_progress ;
376 rd_progress <= #`FF_DELAY read_progress ;
377 rd_from_fifo <= #`FF_DELAY read_from_fifo ;
378 rd_request <= #`FF_DELAY read_request ;
379 wr_to_fifo <= #`FF_DELAY write_to_fifo ;
380 same_read_reg <= #`FF_DELAY same_read_in ;
381 end
382 end
383 end
384
385 `ifdef HOST
386 `ifdef NO_CNF_IMAGE
387 wire norm_access_to_conf_reg = 1'b0 ;
388 wire cnf_progress = 1'b0 ;
389 `else
390 reg norm_access_to_conf_reg ;
391 reg cnf_progress ;
392 always@(posedge clk_in or posedge reset_in)
393 begin
394 if (reset_in)
395 begin
396 norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ;
397 cnf_progress <= #`FF_DELAY 1'b0 ;
398 end
399 else
400 begin
401 if (addr_phase)
402 begin
403 norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
404 cnf_progress <= #`FF_DELAY config_access ;
405 end
406 end
407 end
408 `endif
409 `else
410 reg norm_access_to_conf_reg ;
411 reg cnf_progress ;
412 always@(posedge clk_in or posedge reset_in)
413 begin
414 if (reset_in)
415 begin
416 norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ;
417 cnf_progress <= #`FF_DELAY 1'b0 ;
418 end
419 else
420 begin
421 if (addr_phase)
422 begin
423 norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
424 cnf_progress <= #`FF_DELAY config_access ;
425 end
426 end
427 end
428 `endif
429
430 // Signal used in S_WAIT state to determin next state
431 wire s_wait_progress = (
432 (~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
433 (~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && ~pcir_fifo_data_err_in) ||
434 (~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
435 (cnf_progress && ~target_abort_in)
436 ) ;
437
438 // Signal used in S_TRANSFERE state to determin next state
439 wire s_tran_progress = (
440 (rw_cbe0 && !disconect_wo_data) ||
441 (~rw_cbe0 && !disconect_wo_data && !target_abort_in && !pcir_fifo_data_err_in)
442 ) ;
443
444 // Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY
445 wire pcit_sm_clk_en ;
446 // FSM states signals indicating the current state
447 reg state_idle ;
448 reg state_wait ;
449 reg sm_transfere ;
450 reg backoff ;
451 reg state_default ;
452 wire state_backoff = sm_transfere && backoff ;
453 wire state_transfere = sm_transfere && !backoff ;
454
455 always@(posedge clk_in or posedge reset_in)
456 begin
457 if ( reset_in )
458 backoff <= #`FF_DELAY 1'b0 ;
459 else if ( state_idle )
460 backoff <= #`FF_DELAY 1'b0 ;
461 else
462 backoff <= #`FF_DELAY (state_wait && !s_wait_progress) ||
463 (sm_transfere && !s_tran_progress && !pci_frame_in && !pci_irdy_in) ||
464 backoff ;
465 end
466 assign config_disconnect = sm_transfere && (norm_access_to_conf_reg || cnf_progress) ;
467
468 // Clock enable module used for preserving the architecture because of minimum delay for critical inputs
469 pci_target32_clk_en pci_target_clock_en
470 (
471 .addr_phase (addr_phase),
472 .config_access (config_access),
473 .addr_claim_in (addr_claim_in),
474 .pci_frame_in (pci_frame_in),
475 .state_wait (state_wait),
476 .state_transfere (sm_transfere),
477 .state_default (state_default),
478 .clk_enable (pcit_sm_clk_en)
479 );
480
481 reg [2:0] c_state ; //current state register
482 reg [2:0] n_state ; //next state input to current state register
483
484 // state machine register control
485 always@(posedge clk_in or posedge reset_in)
486 begin
487 if (reset_in) // reset state machine to S_IDLE state
488 c_state <= #`FF_DELAY S_IDLE ;
489 else
490 if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state!
491 c_state <= #`FF_DELAY n_state ;
492 end
493
494 // state machine logic
495 always@(c_state)
496 begin
497 case (c_state)
498 S_IDLE :
499 begin
500 state_idle <= 1'b1 ;
501 state_wait <= 1'b0 ;
502 sm_transfere <= 1'b0 ;
503 state_default <= 1'b0 ;
504 n_state <= S_WAIT ;
505 end
506 S_WAIT :
507 begin
508 state_idle <= 1'b0 ;
509 state_wait <= 1'b1 ;
510 sm_transfere <= 1'b0 ;
511 state_default <= 1'b0 ;
512 n_state <= S_TRANSFERE ;
513 end
514 S_TRANSFERE :
515 begin
516 state_idle <= 1'b0 ;
517 state_wait <= 1'b0 ;
518 sm_transfere <= 1'b1 ;
519 state_default <= 1'b0 ;
520 n_state <= S_IDLE ;
521 end
522 default :
523 begin
524 state_idle <= 1'b0 ;
525 state_wait <= 1'b0 ;
526 sm_transfere <= 1'b0 ;
527 state_default <= 1'b1 ;
528 n_state <= S_IDLE ;
529 end
530 endcase
531 end
532
533 // if not retry and not target abort
534 // NO CRITICAL SIGNALS
535 wire trdy_w = (
536 (state_wait && ~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
537 (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && !pcir_fifo_data_err_in) ||
538 (state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
539 (state_wait && cnf_progress && ~target_abort_in)
540 ) ;
541 // if not disconnect without data and not target abort (only during reads)
542 // MUST BE ANDED WITH CRITICAL ~FRAME
543 wire trdy_w_frm = (
544 (state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
545 (state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
546 (state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in &&
547 ((~rw_cbe0 && ~pcir_fifo_data_err_in) || rw_cbe0))
548 ) ;
549 // if not disconnect without data and not target abort (only during reads)
550 // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
551 wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ;
552 // TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
553 pci_target32_trdy_crit pci_target_trdy_critical
554 (
555 .trdy_w (trdy_w),
556 .trdy_w_frm (trdy_w_frm),
557 .trdy_w_frm_irdy (trdy_w_frm_irdy),
558 .pci_frame_in (pci_frame_in),
559 .pci_irdy_in (pci_irdy_in),
560 .pci_trdy_out (pci_trdy_out)
561 );
562
563 // if target abort or retry
564 // NO CRITICAL SIGNALS
565 wire stop_w = (
566 (state_wait && target_abort_in) ||
567 (state_wait && ~cnf_progress && rw_cbe0 && ~wr_progress) ||
568 (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && ~rd_progress) ||
569 (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) ||
570 (state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && ~norm_access_to_conf_reg)
571 ) ;
572 // if asserted, wait for deactivating the frame
573 // MUST BE ANDED WITH CRITICAL ~FRAME
574 wire stop_w_frm = (
575 (state_backoff && ~bckp_stop_in)
576 ) ;
577 // if target abort or if disconnect without data (after data transfere)
578 // MUST BE ANDED WITH CRITICAL ~FRAME AND ~IRDY
579 wire stop_w_frm_irdy = (
580 (state_transfere && (disconect_wo_data)) ||
581 (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
582 ) ;
583 // STOP critical module used for preserving the architecture because of minimum delay for critical inputs
584 pci_target32_stop_crit pci_target_stop_critical
585 (
586 .stop_w (stop_w),
587 .stop_w_frm (stop_w_frm),
588 .stop_w_frm_irdy (stop_w_frm_irdy),
589 .pci_frame_in (pci_frame_in),
590 .pci_irdy_in (pci_irdy_in),
591 .pci_stop_out (pci_stop_out)
592 );
593
594 // if OK to respond and not target abort
595 // NO CRITICAL SIGNALS
596 wire devs_w = (
597 (addr_phase && config_access) ||
598 (addr_phase && ~config_access && addr_claim_in) ||
599 (state_wait && ~target_abort_in && !(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) )
600 ) ;
601
602 // if not target abort (only during reads) or if asserted, wait for deactivating the frame
603 // MUST BE ANDED WITH CRITICAL ~FRAME
604 wire devs_w_frm = (
605 (state_transfere && rw_cbe0) ||
606 (state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in) ||
607 (state_backoff && ~bckp_devsel_in)
608 ) ;
609 // if not target abort (only during reads)
610 // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
611 wire devs_w_frm_irdy = (
612 (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
613 ) ;
614 // DEVSEL critical module used for preserving the architecture because of minimum delay for critical inputs
615 pci_target32_devs_crit pci_target_devsel_critical
616 (
617 .devs_w (devs_w),
618 .devs_w_frm (devs_w_frm),
619 .devs_w_frm_irdy (devs_w_frm_irdy),
620 .pci_frame_in (pci_frame_in),
621 .pci_irdy_in (pci_irdy_in),
622 .pci_devsel_out (pci_devsel_out)
623 );
624
625 // signal used in AD enable module with preserving the hierarchy because of minimum delay for critical inputs
626 assign pci_ad_en_out = (
627 (addr_phase && config_access && ~pci_cbe_reg_in[0]) ||
628 (addr_phase && ~config_access && addr_claim_in && ~pci_cbe_reg_in[0]) ||
629 (state_wait && ~rw_cbe0) ||
630 (state_transfere && ~rw_cbe0) ||
631 (state_backoff && ~rw_cbe0 && ~pci_frame_reg_in)
632 ) ;
633
634 wire fast_back_to_back = (addr_phase && ~pci_irdy_reg_in) ;
635
636 // if cycle will progress or will not be stopped
637 // NO CRITICAL SIGNALS
638 wire ctrl_en =
639 /*(~wbu_frame_en_in && fast_back_to_back) ||*/
640 (addr_phase && config_access) ||
641 (addr_phase && ~config_access && addr_claim_in) ||
642 (state_wait) ||
643 (state_transfere && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) ||
644 (state_backoff && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) ;
645
646 assign pci_trdy_en_out = ctrl_en ;
647 assign pci_stop_en_out = ctrl_en ;
648 assign pci_devsel_en_out = ctrl_en ;
649
650 // target ready output signal delayed for one clock used in conjunction with irdy_reg to select which
651 // data are registered in io mux module - from fifo or medoum register
652 reg bckp_trdy_reg ;
653 // delayed indicators for states transfere and backoff
654 reg state_transfere_reg ;
655 reg state_backoff_reg ;
656 always@(posedge clk_in or posedge reset_in)
657 begin
658 if (reset_in)
659 begin
660 bckp_trdy_reg <= #`FF_DELAY 1'b1 ;
661 state_transfere_reg <= #`FF_DELAY 1'b0 ;
662 state_backoff_reg <= #`FF_DELAY 1'b0 ;
663 end
664 else
665 begin
666 bckp_trdy_reg <= #`FF_DELAY bckp_trdy_in ;
667 state_transfere_reg <= #`FF_DELAY state_transfere ;
668 state_backoff_reg <= #`FF_DELAY state_backoff ;
669 end
670 end
671
672 // Read control signals assignments
673 assign
674 fetch_pcir_fifo_out = (
675 (prepare_rd_fifo_data) ||
676 (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in) ||
677 (bckp_trdy_en_in && ~pci_trdy_reg_in && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~pci_irdy_reg_in)
678 ) ;
679
680 assign ad_load_out = (state_wait) ;
681
682 assign ad_load_on_transfer_out = (bckp_trdy_en_in && ~rw_cbe0) ;
683
684 assign load_medium_reg_out = (
685 (prepare_rd_fifo_data) ||
686 (state_wait && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~target_abort_in) ||
687 (~pci_irdy_reg_in && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~pci_trdy_reg_in && bckp_trdy_en_in)
688 ) ;
689
690 assign sel_fifo_mreg_out = (~pci_irdy_reg_in && ~bckp_trdy_reg) ;
691
692 `ifdef HOST
693 `ifdef NO_CNF_IMAGE
694 assign sel_conf_fifo_out = 1'b0 ;
695 `else
696 assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
697 `endif
698 `else
699 assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
700 `endif
701
702 // Write control signals assignments
703 assign
704 load_to_pciw_fifo_out = (
705 (state_wait && (~cnf_progress && ~norm_access_to_conf_reg) && rw_cbe0 && wr_to_fifo && ~target_abort_in) ||
706 (state_transfere_reg && ~state_backoff && rw_cbe0 && wr_to_fifo /*&& ~disconect_wo_data_reg*/ && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) ||
707 ((state_backoff || state_backoff_reg) && rw_cbe0 && wr_to_fifo && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg))
708 ) ;
709
710 `ifdef HOST
711 `ifdef NO_CNF_IMAGE
712 assign load_to_conf_out = 1'b0 ;
713 `else
714 assign load_to_conf_out = (
715 (state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
716 (state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
717 ) ;
718 `endif
719 `else
720 assign load_to_conf_out = (
721 (state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
722 (state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
723 ) ;
724 `endif
725
726 // General control sigal assignments
727 assign addr_phase_out = addr_phase ;
728 assign last_reg_out = (pci_frame_reg_in && ~pci_irdy_reg_in) ;
729 assign frame_reg_out = pci_frame_reg_in ;
730 assign bckp_devsel_out = bckp_devsel_in ;
731 assign bckp_trdy_out = bckp_trdy_in ;
732 assign bckp_stop_out = bckp_stop_in ;
733 assign target_abort_set_out = (bckp_devsel_in && bckp_trdy_in && ~bckp_stop_in && bckp_trdy_en_in) ;
734 // request signal for delayed sinc. module
735 reg master_will_request_read ;
736 always@(posedge clk_in or posedge reset_in)
737 begin
738 if ( reset_in )
739 master_will_request_read <= #`FF_DELAY 1'b0 ;
740 else
741 master_will_request_read <= #`FF_DELAY ((state_wait && ~target_abort_in) || (state_backoff && ~target_abort_set_out)) && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request ;
742 end
743 // MORE OPTIMIZED READS, but not easy to control in a testbench!
744 //assign req_out = master_will_request_read ;
745 assign req_out = master_will_request_read && !pci_irdy_reg_in && !read_processing_in ;
746
747 // ready tells when address or data are written into fifo - RDY ? DATA : ADDRESS
748 assign rdy_out = ~bckp_trdy_reg ;
749
750 // data and address outputs assignments!
751 assign pci_ad_out = data_in ;
752
753 assign data_out = pci_ad_reg_in ;
754 assign be_out = pci_cbe_reg_in ;
755 assign next_be_out = pci_cbe_in ;
756 assign address_out = pci_ad_reg_in ;
757 assign bc_out = pci_cbe_reg_in ;
758 assign bc0_out = rw_cbe0 ;
759
760
761 endmodule
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