all files to lowercase,

[raggedstone] / dhwk / source / pci / verg_4.vhd

diff --git a/dhwk/source/pci/verg_4.vhd b/dhwk/source/pci/verg_4.vhd
new file mode 100644 (file)
index 0000000..02edc30
--- /dev/null
+++ b/dhwk/source/pci/verg_4.vhd
@@ -0,0 +1,33 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_4 is
+        port
+        (
+                IN_A :in std_logic_vector(3 downto 0);
+                IN_B :in std_logic_vector(3 downto 0);
+                GLEICH :out std_logic
+        );
+end entity VERG_4;
+
+architecture VERG_4_DESIGN of VERG_4 is
+
+begin
+
+        process (IN_A,IN_B)
+        begin
+
+                if IN_A = IN_B then
+                        GLEICH <= '1';
+                else
+                        GLEICH <= '0';
+                end if;
+        end process;
+
+end architecture VERG_4_DESIGN;
+