-vhdl work "source/verg_8.vhd"
-vhdl work "source/synplify.vhd"
-vhdl work "source/parity_out.vhd"
+vhdl work "source/par_ser_con.vhd"
+vhdl work "source/ser_par_con.vhd"
+vhdl work "source/pci/address_register.vhd"
+vhdl work "source/pci/comm_dec.vhd"
+vhdl work "source/pci/comm_fsm.vhd"
+vhdl work "source/pci/config_00h.vhd"
+vhdl work "source/pci/config_04h.vhd"
+vhdl work "source/pci/config_08h.vhd"
+vhdl work "source/pci/config_10h.vhd"
+vhdl work "source/pci/config_3Ch.vhd"
+vhdl work "source/pci/config_mux_0.vhd"
+vhdl work "source/pci/config_rd_0.vhd"
vhdl work "source/pci/config_space_header.vhd"
vhdl work "source/pci/config_wr_0.vhd"
-vhdl work "source/pci/config_rd_0.vhd"
-vhdl work "source/pci/config_mux_0.vhd"
-vhdl work "source/pci/config_3Ch.vhd"
-vhdl work "source/pci/config_10h.vhd"
-vhdl work "source/pci/config_08h.vhd"
-vhdl work "source/pci/config_04h.vhd"
-vhdl work "source/pci/config_00h.vhd"
-vhdl work "source/Verg_4.vhd"
-vhdl work "source/Verg_2.vhd"
-vhdl work "source/REG.vhd"
-vhdl work "source/Parity_4.vhd"
-vhdl work "source/Io_reg.vhd"
-vhdl work "source/Io_mux.vhd"
-vhdl work "source/CONT_FSM.vhd"
-vhdl work "source/COMM_FSM.vhd"
-vhdl work "source/pci/comm_dec.vhd"
-vhdl work "source/vergleich.vhd"
-vhdl work "source/steuerung.vhd"
-vhdl work "source/reg_io.vhd"
-vhdl work "source/parity.vhd"
-vhdl work "source/io_mux_reg.vhd"
-vhdl work "source/IO_RW_SEL.vhd"
-vhdl work "source/DATA_MUX.vhd"
-vhdl work "source/user_io.vhd"
-vhdl work "source/pci_interface.vhd"
-vhdl work "source/fifo_io_control.vhd"
-vhdl work "source/connecting_fsm.vhd"
-vhdl work "source/SER_PAR_CON.vhd"
-vhdl work "source/PAR_SER_CON.vhd"
-vhdl work "source/FLAG_BUS.vhd"
-vhdl work "source/pci_top.vhd"
-vhdl work "source/fifo_control.vhd"
-vhdl work "source/MESS_1_TB.vhd"
-vhdl work "source/INTERRUPT.vhd"
-vhdl work "source/top.vhd"
-vhdl work "source/ven_rev_id.vhd"
-vhdl work "source/pci/address_register.vhd"
+vhdl work "source/pci/connecting_fsm.vhd"
+vhdl work "source/pci/cont_fsm.vhd"
+vhdl work "source/pci/data_mux.vhd"
+vhdl work "source/pci/fifo_control.vhd"
+vhdl work "source/pci/fifo_io_control.vhd"
+vhdl work "source/pci/flag_bus.vhd"
+vhdl work "source/pci/interrupt.vhd"
+vhdl work "source/pci/io_mux.vhd"
+vhdl work "source/pci/io_mux_reg.vhd"
+vhdl work "source/pci/io_reg.vhd"
+vhdl work "source/pci/io_rw_sel.vhd"
+vhdl work "source/pci/parity.vhd"
+vhdl work "source/pci/parity_4.vhd"
+vhdl work "source/pci/parity_out.vhd"
+vhdl work "source/pci/pci_interface.vhd"
+vhdl work "source/pci/pci_top.vhd"
+vhdl work "source/pci/reg.vhd"
+vhdl work "source/pci/reg_io.vhd"
+vhdl work "source/pci/steuerung.vhd"
+vhdl work "source/pci/synplify.vhd"
+vhdl work "source/pci/top.vhd"
+vhdl work "source/pci/user_io.vhd"
+vhdl work "source/pci/ven_rev_id.vhd"
+vhdl work "source/pci/verg_2.vhd"
+vhdl work "source/pci/verg_4.vhd"
+vhdl work "source/pci/verg_8.vhd"
+vhdl work "source/pci/vergleich.vhd"
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: COMM_FSM.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity COMM_FSM is
- port
- (
- PCI_CLOCK :in std_logic;
- PCI_RSTn :in std_logic;
- IO_READ :in std_logic;
- IO_WRITE :in std_logic;
- CONF_READ :in std_logic;
- CONF_WRITE :in std_logic;
- DEVSELn :in std_logic;
-
- IO_RD_COM : out std_logic;--> MUX_SEL(0)
- CF_RD_COM :out std_logic;
- IO_WR_COM :out std_logic;
- CF_WR_COM :out std_logic
- );
-end entity COMM_FSM;
-
-architecture COMM_FSM_DESIGN of COMM_FSM is
-
-
- --**********************************************************
- --*** COMMAND FSM CODIERUNG ***
- --**********************************************************
- --
- --
- -- |--------- IO_RD_COM
- -- ||-------- CF_RD_COM
- -- |||------- IO_WR_COM
- -- ||||------ CF_WR_COM
- -- ||||
- constant ST_IDLE_COMM :std_logic_vector (3 downto 0) := "0000";--
- constant ST_CONF_WRITE :std_logic_vector (3 downto 0) := "0001";--
- constant ST_IO_WRITE :std_logic_vector (3 downto 0) := "0010";--
- constant ST_CONF_READ :std_logic_vector (3 downto 0) := "0100";--
- constant ST_IO_READ :std_logic_vector (3 downto 0) := "1000";--
-
- signal COMM_STATE :std_logic_vector (3 downto 0);
-
- --************************************************************
- --*** FSM SPEICHER-AUTOMAT ***
- --************************************************************
-
- attribute syn_state_machine : boolean;
- attribute syn_state_machine of COMM_STATE : signal is false;
-
-begin
-
- --**********************************************************
- --*** COMMAND FSM ***
- --**********************************************************
-
- process (PCI_CLOCK, PCI_RSTn)
- begin
- if PCI_RSTn = '0' then
- COMM_STATE <= "0000";
-
- elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
- case COMM_STATE is
- when ST_IDLE_COMM =>
- if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
-
- elsif CONF_READ = '1' then
- COMM_STATE <= ST_CONF_READ;
-
- elsif IO_WRITE = '1' then
- COMM_STATE <= ST_IO_WRITE;
-
- elsif CONF_WRITE = '1' then
- COMM_STATE <= ST_CONF_WRITE;
-
- else
- COMM_STATE <= ST_IDLE_COMM;
- end if;
-
- when ST_IO_READ =>
- if DEVSELn = '1' then
- COMM_STATE <= ST_IDLE_COMM;
- end if;
-
- when ST_CONF_READ =>
- if DEVSELn = '1' then
- COMM_STATE <= ST_IDLE_COMM;
- end if;
-
- when ST_IO_WRITE =>
- if DEVSELn = '1' then
- COMM_STATE <= ST_IDLE_COMM;
- end if;
-
- when ST_CONF_WRITE =>
- if DEVSELn = '1' then
- COMM_STATE <= ST_IDLE_COMM;
- end if;
-
- when others =>
- COMM_STATE <= ST_IDLE_COMM;
-
- end case; -- COMM_STATE
- end if; -- CLOCK
-end process; -- PROCESS
-
- IO_RD_COM <= COMM_STATE(3);
- CF_RD_COM <= COMM_STATE(2);
- IO_WR_COM <= COMM_STATE(1);
- CF_WR_COM <= COMM_STATE(0);
-
-end architecture COMM_FSM_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONT_FSM.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity CONT_FSM is
- port
- (
- PCI_CLOCK :in std_logic;
- PCI_RSTn :in std_logic;
- IO_READ :in std_logic;
- IO_WRITE :in std_logic;
- CONF_READ :in std_logic;
- CONF_WRITE :in std_logic;
- FIFO_READ :in std_logic;
- READ :out std_logic;--> MUX_SEL(1) , OE_PCI_AD
- PERR_CHECK :out std_logic;
- DEVSELn :out std_logic;
- OE_PCI_PAR :out std_logic;
- OE_PCI_PERR :out std_logic;
- TRDYn :out std_logic;
- PCI_TRDYn :out std_logic; -- s/t/s
- PCI_STOPn :out std_logic; -- s/t/s
- PCI_DEVSELn :out std_logic; -- s/t/s
- FIFO_RDn :out std_logic
- );
-end entity CONT_FSM;
-
-architecture CONT_FSM_DESIGN of CONT_FSM is
-
-
-
- --**********************************************************
- --*** CONTROL FSM CODIERUNG ***
- --**********************************************************
- --
- --
- --
- -- |----------- HELP
- -- ||---------- FIFO_READn
- -- |||--------- OE_PCI_PERR
- -- ||||-------- PERR_CHECK
- -- |||||------- TRDYn
- -- ||||||------ STOPn
- -- |||||||----- DEVSELn
- -- ||||||||---- OE_PCI_PAR
- -- |||||||||--- OE_CONTROL
- -- ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD
- -- ||||||||||
- constant ST_IDLE :std_logic_vector (9 downto 0) := "0100111000";-- 138
-
- constant ST_READ_1 :std_logic_vector (9 downto 0) := "0100110011";-- 133
- constant ST_READ_2 :std_logic_vector (9 downto 0) := "0100000111";-- 107
- constant ST_READ_3 :std_logic_vector (9 downto 0) := "0100111111";-- 13F
-
- constant ST_RD_FIFO_1 :std_logic_vector (9 downto 0) := "0000110011";-- 033
- constant ST_RD_FIFO_2 :std_logic_vector (9 downto 0) := "1100110011";-- 233
-
-
- constant ST_WRITE_1 :std_logic_vector (9 downto 0) := "0111110010";-- 1F2
- constant ST_WRITE_2 :std_logic_vector (9 downto 0) := "0110000010";-- 182
- constant ST_WRITE_3 :std_logic_vector (9 downto 0) := "0110111010";-- 1BA
-
- signal CONTROL_STATE :std_logic_vector (9 downto 0);
-
-
- --signal DEVSELn :std_logic;
- signal STOPn :std_logic;
- --signal TRDYn :std_logic;
-
- --************************************************************
- --*** FSM SPEICHER-AUTOMAT ***
- --************************************************************
-
- attribute syn_state_machine : boolean;
- attribute syn_state_machine of CONTROL_STATE : signal is false;
-
-begin
-
- --**********************************************************
- --*** CONTROL FSM ***
- --**********************************************************
-
- process (PCI_CLOCK, PCI_RSTn)
- begin
- if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE;
-
- elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
-
- case CONTROL_STATE is
- when ST_IDLE =>
- if IO_READ = '1' then
- CONTROL_STATE <= ST_READ_1;
-
- elsif CONF_READ = '1' then
- CONTROL_STATE <= ST_READ_1;
-
- elsif IO_WRITE = '1' then
- CONTROL_STATE <= ST_WRITE_1;
-
- elsif CONF_WRITE = '1' then
- CONTROL_STATE <= ST_WRITE_1;
-
- else CONTROL_STATE <= ST_IDLE;
- end if;
-
- -- when ST_READ_1 =>
- -- CONTROL_STATE <= ST_READ_2;
-
- when ST_READ_1 =>
- if FIFO_READ = '1' then
- CONTROL_STATE <= ST_RD_FIFO_1;
- else
- CONTROL_STATE <= ST_READ_2;
- end if;
-
- when ST_READ_2 =>
- CONTROL_STATE <= ST_READ_3;
-
- when ST_READ_3 =>
- CONTROL_STATE <= ST_IDLE;
-
- when ST_RD_FIFO_1=>
- CONTROL_STATE <= ST_RD_FIFO_2;
-
- when ST_RD_FIFO_2=>
- CONTROL_STATE <= ST_READ_2;
-
- when ST_WRITE_1 =>
- CONTROL_STATE <= ST_WRITE_2;
-
- when ST_WRITE_2 =>
- CONTROL_STATE <= ST_WRITE_3;
-
- when ST_WRITE_3 =>
- CONTROL_STATE <= ST_IDLE;
-
- when others =>
- CONTROL_STATE <= ST_IDLE;
-
- end case; -- COMM_STATE
- end if; -- CLOCK
-end process; -- PROCESS
-
-
-READ <= CONTROL_STATE(0);
---OE_CONTROL <= CONTROL_STATE(1);
-OE_PCI_PAR <= CONTROL_STATE(2);
-DEVSELn <= CONTROL_STATE(3);
-STOPn <= CONTROL_STATE(4);
-TRDYn <= CONTROL_STATE(5);
-PERR_CHECK <= CONTROL_STATE(6);
-OE_PCI_PERR <= CONTROL_STATE(7);
-
-FIFO_RDn <= CONTROL_STATE(8);
-
-
-PCI_DEVSELn <= CONTROL_STATE(3) when CONTROL_STATE(1) = '1' else 'Z';
-PCI_STOPn <= STOPn when CONTROL_STATE(1) = '1' else 'Z';
-PCI_TRDYn <= CONTROL_STATE(5) when CONTROL_STATE(1) = '1' else 'Z';
-
-end architecture CONT_FSM_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: DATA_MUX.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity DATA_MUX is
- port
- (
- READ_SEL :in std_logic_vector( 1 downto 0);
- ADDR_REG :in std_logic_vector(31 downto 0);
- CBE_REGn :in std_logic_vector( 3 downto 0);
- MUX_IN_XX0 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX1 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX2 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX3 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX4 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX5 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX6 :in std_logic_vector( 7 downto 0);
- MUX_IN_XX7 :in std_logic_vector( 7 downto 0);
- MUX_OUT :out std_logic_vector(31 downto 0);
- READ_XX1_0 :out std_logic;
- READ_XX3_2 :out std_logic;
- READ_XX5_4 :out std_logic;
- READ_XX7_6 :out std_logic
- --READ_FIFO :out std_logic
- );
-end entity DATA_MUX;
-
-architecture DATA_MUX_DESIGN of DATA_MUX is
-
- signal MUX :std_logic_vector(31 downto 0);
- signal SEL :std_logic_vector( 7 downto 0);
-
- signal SIG_READ_XX1_0 :std_logic;
- signal SIG_READ_XX3_2 :std_logic;
- signal SIG_READ_XX5_4 :std_logic;
- signal SIG_READ_XX7_6 :std_logic;
-
-begin
-
- SEL <= ADDR_REG(3 downto 2) & CBE_REGn & READ_SEL;
-
- SIG_READ_XX1_0 <= '1' when SEL = "00110011" else '0';
- SIG_READ_XX3_2 <= '1' when SEL = "00001111" else '0';
- SIG_READ_XX5_4 <= '1' when SEL = "01110011" else '0';
- SIG_READ_XX7_6 <= '1' when SEL = "01001111" else '0';
-
- MUX <= (X"00" & X"00" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else
- (MUX_IN_XX3 & MUX_IN_XX2 & X"00" & X"00" ) when SIG_READ_XX3_2 = '1' else
- (X"00" & X"00" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else
- (MUX_IN_XX7 & MUX_IN_XX6 & X"00" & X"00" ) when SIG_READ_XX7_6 = '1' else
- (others => '0');
-
-
- -- MUX <= (X"01" & X"23" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else
- -- (MUX_IN_XX3 & MUX_IN_XX2 & X"45" & X"67" ) when SIG_READ_XX3_2 = '1' else
- -- (X"89" & X"AB" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else
- -- (MUX_IN_XX7 & MUX_IN_XX6 & X"CD" & X"EF" ) when SIG_READ_XX7_6 = '1' else
- -- (others => '0');
-
-
- MUX_OUT <= MUX;
-
-
- READ_XX1_0 <= SIG_READ_XX1_0;
- READ_XX3_2 <= SIG_READ_XX3_2;
- READ_XX5_4 <= SIG_READ_XX5_4;
- READ_XX7_6 <= SIG_READ_XX7_6;
-
---READ_FIFO <= SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test
-
-end architecture DATA_MUX_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: FLAG_BUS.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity FLAG_BUS is
- port
- (
- PCI_CLOCK :in std_logic;
- KONS_1 :in std_logic;
- FLAG_IN_0 :in std_logic;
- R_EFn :in std_logic;
- R_HFn :in std_logic;
- R_FFn :in std_logic;
- FLAG_IN_4 :in std_logic;
- S_EFn :in std_logic;
- S_HFn :in std_logic;
- S_FFn :in std_logic;
- HOLD :in std_logic;
- SYNC_FLAG :out std_logic_vector (7 downto 0)
- );
-end entity FLAG_BUS;
-
-architecture FLAG_BUS_DESIGN of FLAG_BUS is
-
-
- signal FF1_S_EFn :std_logic;
- signal FF1_S_HFn :std_logic;
- signal FF1_S_FFn :std_logic;
- signal FF1_R_EFn :std_logic;
- signal FF1_R_HFn :std_logic;
- signal FF1_R_FFn :std_logic;
-
- signal FF2_S_EFn :std_logic;
- signal FF2_S_HFn :std_logic;
- signal FF2_S_FFn :std_logic;
- signal FF2_R_EFn :std_logic;
- signal FF2_R_HFn :std_logic;
- signal FF2_R_FFn :std_logic;
-
-begin
-
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- FF1_S_EFn <= not S_EFn;
- FF1_S_HFn <= not S_HFn;
- FF1_S_FFn <= not S_FFn;
- FF1_R_EFn <= not R_EFn;
- FF1_R_HFn <= not R_HFn;
- FF1_R_FFn <= not R_FFn;
- end if;
- end process;
-
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- if HOLD = '0' then
- FF2_S_EFn <= FF1_S_EFn;
- FF2_S_HFn <= FF1_S_HFn;
- FF2_S_FFn <= FF1_S_FFn;
- FF2_R_EFn <= FF1_R_EFn;
- FF2_R_HFn <= FF1_R_HFn;
- FF2_R_FFn <= FF1_R_FFn;
-
- elsif HOLD = '1' then
- FF2_S_EFn <= FF2_S_EFn;
- FF2_S_HFn <= FF2_S_HFn;
- FF2_S_FFn <= FF2_S_FFn;
- FF2_R_EFn <= FF2_R_EFn;
- FF2_R_HFn <= FF2_R_HFn;
- FF2_R_FFn <= FF2_R_FFn;
- end if;
- end if;
- end process;
-
-SYNC_FLAG(0) <= FLAG_IN_0;
-SYNC_FLAG(1) <= FF2_R_EFn;
-SYNC_FLAG(2) <= FF2_R_HFn;
-SYNC_FLAG(3) <= FF2_R_FFn;
-SYNC_FLAG(4) <= FLAG_IN_4;
-SYNC_FLAG(5) <= FF2_S_EFn;
-SYNC_FLAG(6) <= FF2_S_HFn;
-SYNC_FLAG(7) <= FF2_S_FFn;
-
-end architecture FLAG_BUS_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: INTERRUPT.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity INTERRUPT is
- port
- (
- PCI_CLOCK :in std_logic;
- PCI_RSTn :in std_logic; -- PCI reset is asynchron (low active)
- RESET :in std_logic;
- TAST_SETn :in std_logic;
- TAST_RESn :in std_logic;
- INT_IN_0 :in std_logic;
- INT_IN_1 :in std_logic;
- INT_IN_2 :in std_logic;
- INT_IN_3 :in std_logic;
- INT_IN_4 :in std_logic;
- INT_IN_5 :in std_logic;
- INT_IN_6 :in std_logic;
- INT_IN_7 :in std_logic;
- TRDYn :in std_logic; -- event 1 after read of Interrupt status register (low active)
- READ_XX5_4 :in std_logic; -- event 2 after read of Interrupt status register
- INT_RES :in std_logic_vector(7 downto 0); -- clear selected interrupts
- INT_MASKE :in std_logic_vector(7 downto 0); -- interrupt mask register
- INT_REG :out std_logic_vector(7 downto 0); -- interrupt status register
- INTAn :out std_logic; -- second interrupt line for PCI analyzer
- PCI_INTAn :out std_logic -- PCI interrupt line
- );
-
-end entity INTERRUPT;
-
-architecture INTERRUPT_DESIGN of INTERRUPT is
-
- signal SIG_TAST_Q :std_logic;
- signal SIG_TAST_Qn :std_logic;
-
-
- signal SIG_INTA :std_logic;
-
- signal FF_A :std_logic_vector(7 downto 0);
- signal FF_B :std_logic_vector(7 downto 0);
- signal SET :std_logic_vector(7 downto 0);
-
- signal SIG_PROPAGATE_INT :std_logic;
- signal SIG_PROPAGATE_INT_SECOND :std_logic;
- signal REG :std_logic_vector(7 downto 0);
-
-begin
-
-
-
-
- ------------------------------------------------------
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
-
- -- THIS IS BROKEN (it cycles the interrupt)
- SIG_TAST_Q <= not (TAST_SETn and SIG_TAST_Qn);
- SIG_TAST_Qn <= not (TAST_RESn and SIG_TAST_Q);
-
- end if;
- end process;
-
- ------------------------------------------------------
-
- process (PCI_CLOCK)
- begin
- if (PCI_RSTn = '0') then
- SET <= "00000000";
- FF_A <= "00000000";
- FF_B <= "00000000";
-
- elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
- if (RESET = '1') then
- SET <= "00000000";
- FF_A <= "00000000";
- FF_B <= "00000000";
- else
- FF_A(0) <= INT_IN_0; -- Receive FIFO Empty Flag
-
- FF_A(1) <= INT_IN_1; -- Send FIFO Half Full
- FF_A(2) <= INT_IN_2;
- FF_A(3) <= INT_IN_3;
-
- FF_A(4) <= INT_IN_4;
-
- FF_A(5) <= INT_IN_5;
- FF_A(6) <= INT_IN_6;
- FF_A(7) <= INT_IN_7;
-
- FF_B <= FF_A;
-
- SET <= FF_A AND not FF_B;
- end if;
- end if;
- end process;
-
- process (PCI_CLOCK,PCI_RSTn)
- begin
- if (PCI_RSTn = '0') then
- REG <= "00000000";
-
- elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then
- if(RESET = '1') then
- REG <= "00000000";
-
- -- elsif(SIG_TAST_Q = '1') then
- -- REG <= "00000000" or SET;
-
- elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
- REG <= (REG AND NOT INT_RES) OR SET;
- else
- REG <= REG OR SET;
- end if;
- end if;
- end process;
-
- SIG_PROPAGATE_INT <=
- (REG(0) AND INT_MASKE(0))
- OR (REG(1) AND INT_MASKE(1))
- OR (REG(2) AND INT_MASKE(2))
- OR (REG(3) AND INT_MASKE(3))
- OR (REG(4) AND INT_MASKE(4))
- OR (REG(5) AND INT_MASKE(5))
- OR (REG(6) AND INT_MASKE(6))
- OR (REG(7) AND INT_MASKE(7));
-
- process (PCI_CLOCK)
- begin
- if(PCI_CLOCK'event and PCI_CLOCK = '1') then
- SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
- end if;
- end process;
-
- INTAn <= not SIG_PROPAGATE_INT_SECOND;
- PCI_INTAn <= '0' when SIG_PROPAGATE_INT_SECOND = '0' else 'Z';
- INT_REG <= REG;
-
-end architecture INTERRUPT_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONFIG_WR_SEL.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity IO_WR_SEL is
- port
- (
- IO_WR_COM :in std_logic;
- IRDY_REGn :in std_logic;
- TRDYn :in std_logic;
- ADDR_REG :in std_logic_vector(31 downto 0);
- CBE_REGn :in std_logic_vector( 3 downto 0);
- WRITE_XX1_0 :out std_logic;
- WRITE_XX3_2 :out std_logic;
- WRITE_XX5_4 :out std_logic;
- WRITE_XX7_6 :out std_logic
- );
-end entity IO_WR_SEL;
-
---PCI Byte Enable
---C/BE[3..0] gueltige Datenbits
--------------------------------
--- 0000 AD 31..0
--- 1000 AD 23..0
--- 1100 AD 15..0
--- 1110 AD 7..0
--- 0011 AD 31..16
-
-architecture IO_WR_SEL_DESIGN of IO_WR_SEL is
-
- signal WR_ENA :std_logic;
- signal ADDR :std_logic_vector( 5 downto 0);
-
-begin
-
- WR_ENA <= '1' when
- IO_WR_COM = '1' and
- IRDY_REGn = '0' and
- TRDYn = '0' else '0';
-
- ADDR <= ADDR_REG(3) & ADDR_REG(2) & CBE_REGn;
-
- WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0';
- WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';
- WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0';
- WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';
-
-end architecture IO_WR_SEL_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: IO_MUX.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity IO_MUX is
- port
- (
- READ_SEL :in std_logic_vector ( 1 downto 0);
- USER_DATA :in std_logic_vector (31 downto 0);
- CONFIG_DATA :in std_logic_vector (31 downto 0);
- PCI_AD :in std_logic_vector (31 downto 0);
- IO_DATA :out std_logic_vector (31 downto 0)
- );
-end entity IO_MUX;
-
-architecture IO_MUX_DESIGN of IO_MUX is
-
- signal MUX :std_logic_vector (31 downto 0);
-
-begin
-
- MUX <= PCI_AD when READ_SEL = "00" else -- WRITE_CONFIG
- PCI_AD when READ_SEL = "01" else -- WRITE_IO
- CONFIG_DATA when READ_SEL = "10" else -- READ_CONFIG
- USER_DATA when READ_SEL = "11" else -- READ_IO
- CONFIG_DATA;
-
- -- MUX;
-
- IO_DATA <= MUX;
-
-end architecture IO_MUX_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: IO_MUX.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity IO_REG is
- port
- (
- PCI_CLOCK :in std_logic;
- PCI_RSTn :in std_logic;
- PCI_FRAMEn :in std_logic;
- PCI_IRDYn :in std_logic;
- PCI_IDSEL :in std_logic;
- PCI_PAR :in std_logic;
- PCI_CBEn :in std_logic_vector ( 3 downto 0);
- OE_PCI_AD :in std_logic;
- IO_DATA :in std_logic_vector (31 downto 0);
- AD_REG :out std_logic_vector (31 downto 0);
- CBE_REGn :out std_logic_vector ( 3 downto 0);
- FRAME_REGn :out std_logic;
- IRDY_REGn :out std_logic;
- IDSEL_REG :out std_logic;
- PAR_REG :out std_logic;
- PCI_AD :out std_logic_vector (31 downto 0) -- t/s
- );
-end entity IO_REG;
-
-architecture IO_REG_DESIGN of IO_REG is
-
- signal REG_AD :std_logic_vector (31 downto 0);
- signal REG_CBEn :std_logic_vector ( 3 downto 0);
- signal REG_FRAMEn :std_logic;
- signal REG_IRDYn :std_logic;
- signal REG_IDSEL :std_logic;
- signal REG_PAR :std_logic;
-
-begin
-
- process (PCI_CLOCK, PCI_RSTn)
- begin
- if PCI_RSTn = '0' then
- REG_AD <= X"00000000";
- REG_CBEn <= "0000";
- REG_FRAMEn <= '1';
- REG_IRDYn <= '1';
- REG_IDSEL <= '0';
- REG_PAR <= '0';
-
- elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
- REG_AD <= IO_DATA;
- REG_CBEn <= PCI_CBEn;
- REG_FRAMEn <= PCI_FRAMEn;
- REG_IRDYn <= PCI_IRDYn;
- REG_IDSEL <= PCI_IDSEL;
- REG_PAR <= PCI_PAR;
- end if;
- end process;
-
- PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');
-
- AD_REG <= REG_AD;
- CBE_REGn <= REG_CBEn;
- FRAME_REGn <= REG_FRAMEn;
- IRDY_REGn <= REG_IRDYn;
- IDSEL_REG <= REG_IDSEL;
- PAR_REG <= REG_PAR;
-
-end architecture IO_REG_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 29.08.2006
--- File: MESS_1_TB.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity MESS_1_TB is
- port
- (
- KONST_1 :in std_logic;
- PCI_IDSEL :in std_logic;
- DEVSELn :in std_logic;
- INTAn :in std_logic;
- REG_OUT_XX7 :in std_logic_vector(7 downto 0);
- TB_PCI_IDSEL :out std_logic;
- TB_DEVSELn :out std_logic;
- TB_INTAn :out std_logic
- );
-end entity MESS_1_TB;
-
-architecture MESS_1_TB_DESIGN of MESS_1_TB is
-
-begin
-
- TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;
-
- TB_INTAn <= INTAn and KONST_1;
-
- TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
-
-end architecture MESS_1_TB_DESIGN;
+++ /dev/null
--- $Id: PAR_SER_CON.vhd,v 1.4 2007-03-11 08:44:31 sithglan Exp $
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity PAR_SER_CON is
- port
- (
- PCI_CLOCK :in std_logic;
- RESET :in std_logic;
- PSC_ENABLE :in std_logic; -- Parallel Serial Converter Enable
- SYNC_S_FIFO_EFn :in std_logic; -- Empty Flag (low active)
- SPC_RDY_IN :in std_logic; -- Ready to receive data
- PAR_IN :in std_logic_vector(7 downto 0);
- SER_OUT :out std_logic; -- Serial Output
- S_FIFO_READn :out std_logic -- FIFO Read (low active)
- );
-end entity PAR_SER_CON ;
-
-architecture PAR_SER_CON_DESIGN of PAR_SER_CON is
-
- constant STATE_END :std_logic_vector(3 downto 0) := "0001";
- constant STATE_SEND :std_logic_vector(3 downto 0) := "0010";
- constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";
- constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";
- constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";
- constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";
- constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";
- constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";
- constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";
- constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";
-
- signal COUNT :std_logic_vector (3 downto 0);
- signal STATE :std_logic_vector (3 downto 0);
- signal DATUM :std_logic_vector (7 downto 0);
- signal SYNC :std_logic; -- make SPC_RDY_IN stable
-
- attribute syn_state_machine:boolean;
- attribute syn_state_machine of STATE: signal is false;
- attribute syn_state_machine of COUNT: signal is false;
-begin
-
- process(PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- if ("0000" < COUNT) then
- COUNT <= COUNT - 1;
- end if;
-
- if (RESET = '1') then
- STATE <= STATE_SEND;
- COUNT <= "0000";
- SER_OUT <= '0';
- S_FIFO_READn <= '1';
-
- elsif (PSC_ENABLE = '1') then
- if (COUNT = "0000") then
- COUNT <= "0011";
- case STATE is
- when STATE_SEND =>
- if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then
- SER_OUT <= '1';
- S_FIFO_READn <= '0';
- STATE <= STATE_SEND_BIT_0;
- end if;
-
- when STATE_SEND_BIT_0 =>
- DATUM <= PAR_IN;
- S_FIFO_READn <= '1';
- SER_OUT <= PAR_IN(0);
- STATE <= STATE_SEND_BIT_1;
-
- when STATE_SEND_BIT_1 =>
- SER_OUT <= DATUM(1);
- STATE <= STATE_SEND_BIT_2;
-
- when STATE_SEND_BIT_2 =>
- SER_OUT <= DATUM(2);
- STATE <= STATE_SEND_BIT_3;
-
- when STATE_SEND_BIT_3 =>
- SER_OUT <= DATUM(3);
- STATE <= STATE_SEND_BIT_4;
-
- when STATE_SEND_BIT_4 =>
- SER_OUT <= DATUM(4);
- STATE <= STATE_SEND_BIT_5;
-
- when STATE_SEND_BIT_5 =>
- SER_OUT <= DATUM(5);
- STATE <= STATE_SEND_BIT_6;
-
- when STATE_SEND_BIT_6 =>
- SER_OUT <= DATUM(6);
- STATE <= STATE_SEND_BIT_7;
-
- when STATE_SEND_BIT_7 =>
- SER_OUT <= DATUM(7);
- STATE <= STATE_END;
-
- when STATE_END =>
- SER_OUT <= '0';
- STATE <= STATE_SEND;
-
- when others => STATE <= STATE_END;
- end case;
-
- else
- S_FIFO_READn <= '1';
- end if; -- COUNT
- end if; -- RESET ... / PSC_ENABLE ...
- end if; -- PCI_CLOCK ...
- end process;
-
- process(PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- SYNC <= SPC_RDY_IN;
- end if;
- end process;
-
-end architecture PAR_SER_CON_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: PARITY_4.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity PARITY_4 is
- port
- (
- PAR_IN :in std_logic_vector(3 downto 0);
- PAR_OUT :out std_logic
- );
-end entity PARITY_4;
-
-architecture PARITY_4_DESIGN of PARITY_4 is
-
-begin
-
- PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);
-
-end architecture PARITY_4_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: REG.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity REG is
- port
- (
- CLOCK :in std_logic;
- RESET :in std_logic;
- WRITE :in std_logic;
- REG_IN :in std_logic_vector(7 downto 0);
- REG_OUT :out std_logic_vector(7 downto 0)
- );
-end entity REG;
-
-architecture REG_DESIGN of REG is
-
- signal SIG_REG :std_logic_vector (7 downto 0);
-
-begin
-
- process (CLOCK)
- begin
- if (CLOCK'event and CLOCK = '1') then
- if RESET = '1' then
- SIG_REG <= X"00";
-
- elsif WRITE = '1' then
- SIG_REG <= REG_IN;
-
- else
- SIG_REG <= SIG_REG;
- end if;
- end if;
- end process;
-
- REG_OUT <= SIG_REG;
-
-end architecture REG_DESIGN;
+++ /dev/null
--- $Id: SER_PAR_CON.vhd,v 1.3 2007-03-11 08:44:31 sithglan Exp $
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity SER_PAR_CON is
- port
- (
- PCI_CLOCK :in std_logic;
- RESET :in std_logic;
- SPC_ENABLE :in std_logic; -- Driver Enable Sender/Receiver
- SYNC_R_FIFO_FFn :in std_logic; -- FIFO Full Flag (low active)
- SERIAL_IN :in std_logic; -- Serial Input
- R_FIFO_WRITEn :out std_logic; -- FIFO Write (low active)
- SPC_RDY_OUT :out std_logic; -- Ready to Receive Data
- PAR_OUT :out std_logic_vector(7 downto 0)
- );
-end entity SER_PAR_CON;
-
-
-architecture SER_PAR_CON_DESIGN of SER_PAR_CON is
-
--- constant STATE_RECV :std_logic_vector(3 downto 0) := "0001";
- constant STATE_RECV_START_BIT :std_logic_vector(3 downto 0) := "0010";
- constant STATE_RECV_BIT_0 :std_logic_vector(3 downto 0) := "0011";
- constant STATE_RECV_BIT_1 :std_logic_vector(3 downto 0) := "0100";
- constant STATE_RECV_BIT_2 :std_logic_vector(3 downto 0) := "0101";
- constant STATE_RECV_BIT_3 :std_logic_vector(3 downto 0) := "0110";
- constant STATE_RECV_BIT_4 :std_logic_vector(3 downto 0) := "0111";
- constant STATE_RECV_BIT_5 :std_logic_vector(3 downto 0) := "1000";
- constant STATE_RECV_BIT_6 :std_logic_vector(3 downto 0) := "1001";
- constant STATE_RECV_BIT_7 :std_logic_vector(3 downto 0) := "1010";
- constant STATE_RECV_FIFOFULL :std_logic_vector(3 downto 0) := "1011";
-
- signal COUNT :std_logic_vector (3 downto 0);
- signal STATE :std_logic_vector (3 downto 0);
- signal STARTBIT :std_logic_vector (3 downto 0);
-
-
- attribute syn_state_machine:boolean;
- attribute syn_state_machine of STATE: signal is false;
- attribute syn_state_machine of COUNT: signal is false;
-
-begin
-
- process(PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- if ("0000" < COUNT) then
- COUNT <= COUNT - 1;
- end if;
-
- -- war nicht das Problem des Datenverlusts
- -- if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
- -- R_FIFO_WRITEn <= '1';
- --- end if;
-
- if (RESET = '1') then
- STATE <= STATE_RECV_START_BIT;
- COUNT <= "0000";
- R_FIFO_WRITEn <= '1';
-
- elsif (SPC_ENABLE = '1') then
-
- if (STATE = STATE_RECV_START_BIT) then
- R_FIFO_WRITEn <= '1';
- if (STARTBIT = "0011") then
- COUNT <= "0011";
- STATE <= STATE_RECV_BIT_0;
- end if;
-
- elsif (STATE = STATE_RECV_FIFOFULL) then
- if (SYNC_R_FIFO_FFn = '1') then
- R_FIFO_WRITEn <= '0';
- STATE <= STATE_RECV_START_BIT;
- end if;
-
- elsif (COUNT = "0000") then
- COUNT <= "0011";
- case STATE is
-
- when STATE_RECV_BIT_0 =>
- PAR_OUT(0) <= STARTBIT(0);
- STATE <= STATE_RECV_BIT_1;
-
- when STATE_RECV_BIT_1 =>
- PAR_OUT(1) <= STARTBIT(0);
- STATE <= STATE_RECV_BIT_2;
-
- when STATE_RECV_BIT_2 =>
- PAR_OUT(2) <= STARTBIT(0);
- STATE <= STATE_RECV_BIT_3;
-
- when STATE_RECV_BIT_3 =>
- PAR_OUT(3) <= STARTBIT(0);
- STATE <= STATE_RECV_BIT_4;
-
- when STATE_RECV_BIT_4 =>
- PAR_OUT(4) <= STARTBIT(0);
- STATE <= STATE_RECV_BIT_5;
-
- when STATE_RECV_BIT_5 =>
- PAR_OUT(5) <= STARTBIT(0);
- STATE <= STATE_RECV_BIT_6;
-
- when STATE_RECV_BIT_6 =>
- PAR_OUT(6) <= STARTBIT(0);
- STATE <= STATE_RECV_BIT_7;
-
- when STATE_RECV_BIT_7 =>
- PAR_OUT(7) <= STARTBIT(0);
-
- if (SYNC_R_FIFO_FFn = '1') then
- STATE <= STATE_RECV_START_BIT;
- R_FIFO_WRITEn <= '0';
- else
- STATE <= STATE_RECV_FIFOFULL;
- end if;
-
- when others =>
- STATE <= STATE_RECV_START_BIT;
-
- end case;
- end if; -- COUNT
- end if; -- RESET ... / SPC_ENABLE ...
- end if; -- PCI_CLOCK ...
- end process;
-
- process(PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
- end if;
- end process;
-
-
- process(PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- if (RESET = '1') then
- STARTBIT <= "0000";
- else
- STARTBIT(0) <= SERIAL_IN;
- STARTBIT(1) <= STARTBIT(0);
- STARTBIT(2) <= STARTBIT(1);
- STARTBIT(3) <= STARTBIT(2);
- end if;
- end if;
- end process;
-
-end architecture SER_PAR_CON_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VERG_2.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity VERG_2 is
- port
- (
- IN_A :in std_logic_vector(1 downto 0);
- IN_B :in std_logic_vector(1 downto 0);
- GLEICH :out std_logic
- );
-end entity VERG_2;
-
-architecture VERG_2_DESIGN of VERG_2 is
-
-begin
-
- process (IN_A,IN_B)
- begin
-
- if IN_A = IN_B then
- GLEICH <= '1';
- else
- GLEICH <= '0';
- end if;
-
-end process;
-
-end architecture VERG_2_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VERG_4.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity VERG_4 is
- port
- (
- IN_A :in std_logic_vector(3 downto 0);
- IN_B :in std_logic_vector(3 downto 0);
- GLEICH :out std_logic
- );
-end entity VERG_4;
-
-architecture VERG_4_DESIGN of VERG_4 is
-
-begin
-
- process (IN_A,IN_B)
- begin
-
- if IN_A = IN_B then
- GLEICH <= '1';
- else
- GLEICH <= '0';
- end if;
- end process;
-
-end architecture VERG_4_DESIGN;
-
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONNECTING_FSM.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity CONNECTING_FSM is
- port
- (
- PCI_CLOCK :in std_logic;
- RESET :in std_logic;
- PSC_ENABLE :in std_logic;
- SYNC_S_FIFO_EFn :in std_logic;
- SPC_ENABLE :in std_logic;
- SYNC_R_FIFO_FFn :in std_logic;
- S_FIFO_Q_OUT :in std_logic_vector(7 downto 0);
- S_FIFO_READn :out std_logic;
- R_FIFO_WRITEn :out std_logic;
- R_FIFO_D_IN :out std_logic_vector(7 downto 0)
- );
-end entity CONNECTING_FSM;
-
-architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
-
- signal REG :std_logic_vector(7 downto 0);
- signal HELP_0,HELP_1 :std_logic;
- signal SIG_LOAD :std_logic;
-
-
- --**********************************************************
- --*** CONNECTING FSM CODIERUNG ***
- --**********************************************************
- --
- --
- -- ---------- HELP_0
- -- |--------- HELP_1
- -- ||-------- LOAD
- -- |||------- WRITE
- -- ||||------ READ
- -- |||||
- constant S0 :std_logic_vector(4 downto 0) := "00011";--
- constant S1 :std_logic_vector(4 downto 0) := "01010";--READ
- constant S2 :std_logic_vector(4 downto 0) := "10010";--READ
- constant S3 :std_logic_vector(4 downto 0) := "11110";--READ,LOAD
- constant S4 :std_logic_vector(4 downto 0) := "11011";--
- constant S5 :std_logic_vector(4 downto 0) := "01001";--WRITE
- constant S6 :std_logic_vector(4 downto 0) := "10001";--WRITE
- constant S7 :std_logic_vector(4 downto 0) := "11001";--WRITE
-
- signal STATES :std_logic_vector(4 downto 0);
-
- --************************************************************
- --*** FSM SPEICHER-AUTOMAT ***
- --************************************************************
-
- attribute syn_state_machine : boolean;
- attribute syn_state_machine of STATES : signal is false;
-
---************************************************************
---*** REGISTER BESCHREIBUNG ***
---************************************************************
-
-begin
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- if SIG_LOAD = '1' then
- REG <= S_FIFO_Q_OUT;
-
- elsif SIG_LOAD = '0' then
- REG <= REG;
- end if;
- end if;
- end process;
-
- --************************************************************
- --*** FSM BESCHREIBUNG ***
- --************************************************************
-
-process (PCI_CLOCK)
-begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
-
- if RESET = '1' then
- STATES <= S0;
- else
-
- case STATES is
-
- when S0 =>
- if PSC_ENABLE = '1' and SPC_ENABLE = '1' and SYNC_S_FIFO_EFn = '1' then
- STATES <= S1;
- else
- STATES <= S0;
- end if;
-
- when S1 =>
- STATES <= S2;
-
- when S2 =>
- STATES <= S3;
-
- when S3 =>
- STATES <= S4;
-
- when S4 =>
- if SYNC_R_FIFO_FFn = '1' then
- STATES <= S5;
- else
- STATES <= S4;
- end if;
-
- when S5 =>
- STATES <= S6;
-
- when S6 =>
- STATES <= S7;
-
- when S7 =>
- STATES <= S0;
-
- when others =>
- STATES <= S0;
-
- end case; -- STATES
- end if; -- RESET
- end if; -- PCI_CLOCK
-end process; -- PROCESS
-
- --************************************************************
- --*** ZUWEISUNG signal/out <= STATES ***
- --************************************************************
-
-HELP_0 <= STATES(4);
-HELP_1 <= STATES(3);
-SIG_LOAD <= STATES(2);
-R_FIFO_WRITEn <= STATES(1);
-S_FIFO_READn <= STATES(0);
-
-R_FIFO_D_IN <= REG;
-
-end architecture CONNECTING_FSM_DESIGN;
+++ /dev/null
--- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
-
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity FIFO_CONTROL is
- Port ( FIFO_RDn : In std_logic;
- FLAG_IN_0 : In std_logic;
- FLAG_IN_4 : In std_logic;
- HOLD : In std_logic;
- KONST_1 : In std_logic;
- PCI_CLOCK : In std_logic;
- PSC_ENABLE : In std_logic;
- R_EFn : In std_logic;
- R_FFn : In std_logic;
- R_HFn : In std_logic;
- RESET : In std_logic;
- S_EFn : In std_logic;
- S_FFn : In std_logic;
- S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
- S_HFn : In std_logic;
- SERIAL_IN : In std_logic;
- SPC_ENABLE : In std_logic;
- SPC_RDY_IN : In std_logic;
- WRITE_XX1_0 : In std_logic;
- R_ERROR : Out std_logic;
- R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
- R_FIFO_READn : Out std_logic;
- R_FIFO_RESETn : Out std_logic;
- R_FIFO_RETRANSMITn : Out std_logic;
- R_FIFO_WRITEn : Out std_logic;
- RESERVE : Out std_logic;
- S_ERROR : Out std_logic;
- S_FIFO_READn : Out std_logic;
- S_FIFO_RESETn : Out std_logic;
- S_FIFO_RETRANSMITn : Out std_logic;
- S_FIFO_WRITEn : Out std_logic;
- SERIAL_OUT : Out std_logic;
- SPC_RDY_OUT : Out std_logic;
- SR_ERROR : Out std_logic;
- SYNC_FLAG : Out std_logic_vector (7 downto 0));
-end FIFO_CONTROL;
-
-architecture SCHEMATIC of FIFO_CONTROL is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal XXXR_FIFO_WRITEn : std_logic;
- signal XXXS_FIFO_READn : std_logic;
- signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
- signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
-
- component SER_PAR_CON
- Port ( PCI_CLOCK : In std_logic;
- RESET : In std_logic;
- SERIAL_IN : In std_logic;
- SPC_ENABLE : In std_logic;
- SYNC_R_FIFO_FFn : In std_logic;
- PAR_OUT : Out std_logic_vector (7 downto 0);
- R_FIFO_WRITEn : Out std_logic;
- SPC_RDY_OUT : Out std_logic );
- end component;
-
- component PAR_SER_CON
- Port ( PAR_IN : In std_logic_vector (7 downto 0);
- PCI_CLOCK : In std_logic;
- PSC_ENABLE : In std_logic;
- RESET : In std_logic;
- SPC_RDY_IN : In std_logic;
- SYNC_S_FIFO_EFn : In std_logic;
- S_FIFO_READn : Out std_logic;
- SER_OUT : Out std_logic );
- end component;
-
- component FIFO_IO_CONTROL
- Port ( FIFO_RDn : In std_logic;
- PCI_CLOCK : In std_logic;
- RESET : In std_logic;
- SYNC_FLAG_1 : In std_logic;
- SYNC_FLAG_7 : In std_logic;
- WRITE_XX1_0 : In std_logic;
- R_ERROR : Out std_logic;
- R_FIFO_READn : Out std_logic;
- R_FIFO_RESETn : Out std_logic;
- R_FIFO_RETRANSMITn : Out std_logic;
- S_ERROR : Out std_logic;
- S_FIFO_RESETn : Out std_logic;
- S_FIFO_RETRANSMITn : Out std_logic;
- S_FIFO_WRITEn : Out std_logic;
- SR_ERROR : Out std_logic );
- end component;
-
- component CONNECTING_FSM
- Port ( PCI_CLOCK : In std_logic;
- PSC_ENABLE : In std_logic;
- RESET : In std_logic;
- S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
- SPC_ENABLE : In std_logic;
- SYNC_R_FIFO_FFn : In std_logic;
- SYNC_S_FIFO_EFn : In std_logic;
- R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
- R_FIFO_WRITEn : Out std_logic;
- S_FIFO_READn : Out std_logic );
- end component;
-
- component FLAG_BUS
- Port ( FLAG_IN_0 : In std_logic;
- FLAG_IN_4 : In std_logic;
- HOLD : In std_logic;
- KONS_1 : In std_logic;
- PCI_CLOCK : In std_logic;
- R_EFn : In std_logic;
- R_FFn : In std_logic;
- R_HFn : In std_logic;
- S_EFn : In std_logic;
- S_FFn : In std_logic;
- S_HFn : In std_logic;
- SYNC_FLAG : Out std_logic_vector (7 downto 0) );
- end component;
-
-begin
-
- SYNC_FLAG <= SYNC_FLAG_DUMMY;
-
- RESERVE <= gnd;
- I23 : SER_PAR_CON
- Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
- SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
- SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
- PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
- R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
- I22 : PAR_SER_CON
- Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
- PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
- RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
- SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
- S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
- I21 : FIFO_IO_CONTROL
- Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
- SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
- SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
- WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
- R_FIFO_READn=>R_FIFO_READn,
- R_FIFO_RESETn=>R_FIFO_RESETn,
- R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
- S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
- S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
- S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
- I20 : CONNECTING_FSM
- Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
- RESET=>RESET,
- S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
- SPC_ENABLE=>SPC_ENABLE,
- SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
- SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
- R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
- R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
- S_FIFO_READn=>XXXS_FIFO_READn );
- I19 : FLAG_BUS
- Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
- KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
- R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
- S_HFn=>S_HFn,
- SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
-
-end SCHEMATIC;
+++ /dev/null
--- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 08:44:31 sithglan Exp $
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity FIFO_IO_CONTROL is
- port
- (
- PCI_CLOCK :in std_logic;
- WRITE_XX1_0 :in std_logic; -- PCI Write
- FIFO_RDn :in std_logic; -- FIFO Read (low active)
- RESET :in std_logic;
- SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
- SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
- S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
- R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
- S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
- R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
- S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
- R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
- S_ERROR :out std_logic; -- Send ERROR
- R_ERROR :out std_logic; -- Recv ERROR
- SR_ERROR :out std_logic -- Send / Recv Error
- );
-end entity FIFO_IO_CONTROL;
-
-architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is
-
- signal SIG_S_ERROR :std_logic; -- Send Error
- signal SIG_R_ERROR :std_logic; -- Recv Error
-
-begin
-
- -- FIFO Write
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK = '1') then
- if (RESET = '1') then
- S_FIFO_WRITEn <= '1';
- SIG_S_ERROR <= '0';
-
- elsif (WRITE_XX1_0 = '0') then
- S_FIFO_WRITEn <= '1';
-
- elsif (WRITE_XX1_0 = '1') then
- if (SYNC_FLAG_7 = '0') then
- SIG_S_ERROR <= '1';
-
- elsif (SYNC_FLAG_7 = '1') then
- S_FIFO_WRITEn <= '0';
- SIG_S_ERROR <= '0';
- end if;
- end if;
- end if;
- end process;
-
- S_ERROR <= SIG_S_ERROR;
-
- -- FIFO Read
-
- R_FIFO_READn <= FIFO_RDn;
-
--- Receive Error
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- if (RESET = '1') then
- SIG_R_ERROR <= '0';
-
- elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
- SIG_R_ERROR <= '1';
- end if;
- end if;
- end process;
-
- R_ERROR <= SIG_R_ERROR;
-
--- Send or Receive Error
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;
- end if;
- end process;
-
--- FIFO Reset
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- S_FIFO_RESETn <= not RESET;
- R_FIFO_RESETn <= not RESET;
- end if;
- end process;
-
-
--- FIFO Retransmit
-
- process (PCI_CLOCK)
- begin
- if (PCI_CLOCK'event and PCI_CLOCK ='1') then
- S_FIFO_RETRANSMITn <= '1';
- R_FIFO_RETRANSMITn <= '1';
- end if;
- end process;
-
-end architecture FIFO_IO_CONTROL_DESIGN;
+++ /dev/null
--- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007
-
-
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity IO_MUX_REG is
- Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
- LOAD_ADDR_REG : In std_logic;
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_PAR : In std_logic;
- PCI_RSTn : In std_logic;
- READ_SEL : In std_logic_vector (1 downto 0);
- USER_DATA : In std_logic_vector (31 downto 0);
- PCI_AD : InOut std_logic_vector (31 downto 0);
- AD_REG : Out std_logic_vector (31 downto 0);
- ADDR_REG : Out std_logic_vector (31 downto 0);
- CBE_REGn : Out std_logic_vector (3 downto 0);
- FRAME_REGn : Out std_logic;
- IDSEL_REG : Out std_logic;
- IRDY_REGn : Out std_logic;
- PAR_REG : Out std_logic );
-end IO_MUX_REG;
-
-architecture SCHEMATIC of IO_MUX_REG is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal IO_DATA : std_logic_vector (31 downto 0);
- signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
-
- component ADDRESS_REGISTER
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- LOAD_ADDR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- ADDR_REG : Out std_logic_vector (31 downto 0) );
- end component;
-
- component IO_REG
- Port ( IO_DATA : In std_logic_vector (31 downto 0);
- OE_PCI_AD : In std_logic;
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_PAR : In std_logic;
- PCI_RSTn : In std_logic;
- AD_REG : Out std_logic_vector (31 downto 0);
- CBE_REGn : Out std_logic_vector (3 downto 0);
- FRAME_REGn : Out std_logic;
- IDSEL_REG : Out std_logic;
- IRDY_REGn : Out std_logic;
- PAR_REG : Out std_logic;
- PCI_AD : Out std_logic_vector (31 downto 0) );
- end component;
-
- component IO_MUX
- Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
- PCI_AD : In std_logic_vector (31 downto 0);
- READ_SEL : In std_logic_vector (1 downto 0);
- USER_DATA : In std_logic_vector (31 downto 0);
- IO_DATA : Out std_logic_vector (31 downto 0) );
- end component;
-
-begin
-
- AD_REG <= AD_REG_DUMMY;
-
- I5 : ADDRESS_REGISTER
- Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,
- PCI_RSTn=>PCI_RSTn,
- ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );
- I1 : IO_REG
- Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),
- OE_PCI_AD=>READ_SEL(1),
- PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
- PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
- PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
- PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
- AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
- IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,
- PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );
- I2 : IO_MUX
- Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),
- PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
- READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
- USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),
- IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );
-
-end SCHEMATIC;
--- /dev/null
+-- $Id: par_ser_con.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity PAR_SER_CON is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ RESET :in std_logic;
+ PSC_ENABLE :in std_logic; -- Parallel Serial Converter Enable
+ SYNC_S_FIFO_EFn :in std_logic; -- Empty Flag (low active)
+ SPC_RDY_IN :in std_logic; -- Ready to receive data
+ PAR_IN :in std_logic_vector(7 downto 0);
+ SER_OUT :out std_logic; -- Serial Output
+ S_FIFO_READn :out std_logic -- FIFO Read (low active)
+ );
+end entity PAR_SER_CON ;
+
+architecture PAR_SER_CON_DESIGN of PAR_SER_CON is
+
+ constant STATE_END :std_logic_vector(3 downto 0) := "0001";
+ constant STATE_SEND :std_logic_vector(3 downto 0) := "0010";
+ constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";
+ constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";
+ constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";
+ constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";
+ constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";
+ constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";
+ constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";
+ constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";
+
+ signal COUNT :std_logic_vector (3 downto 0);
+ signal STATE :std_logic_vector (3 downto 0);
+ signal DATUM :std_logic_vector (7 downto 0);
+ signal SYNC :std_logic; -- make SPC_RDY_IN stable
+
+ attribute syn_state_machine:boolean;
+ attribute syn_state_machine of STATE: signal is false;
+ attribute syn_state_machine of COUNT: signal is false;
+begin
+
+ process(PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if ("0000" < COUNT) then
+ COUNT <= COUNT - 1;
+ end if;
+
+ if (RESET = '1') then
+ STATE <= STATE_SEND;
+ COUNT <= "0000";
+ SER_OUT <= '0';
+ S_FIFO_READn <= '1';
+
+ elsif (PSC_ENABLE = '1') then
+ if (COUNT = "0000") then
+ COUNT <= "0011";
+ case STATE is
+ when STATE_SEND =>
+ if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then
+ SER_OUT <= '1';
+ S_FIFO_READn <= '0';
+ STATE <= STATE_SEND_BIT_0;
+ end if;
+
+ when STATE_SEND_BIT_0 =>
+ DATUM <= PAR_IN;
+ S_FIFO_READn <= '1';
+ SER_OUT <= PAR_IN(0);
+ STATE <= STATE_SEND_BIT_1;
+
+ when STATE_SEND_BIT_1 =>
+ SER_OUT <= DATUM(1);
+ STATE <= STATE_SEND_BIT_2;
+
+ when STATE_SEND_BIT_2 =>
+ SER_OUT <= DATUM(2);
+ STATE <= STATE_SEND_BIT_3;
+
+ when STATE_SEND_BIT_3 =>
+ SER_OUT <= DATUM(3);
+ STATE <= STATE_SEND_BIT_4;
+
+ when STATE_SEND_BIT_4 =>
+ SER_OUT <= DATUM(4);
+ STATE <= STATE_SEND_BIT_5;
+
+ when STATE_SEND_BIT_5 =>
+ SER_OUT <= DATUM(5);
+ STATE <= STATE_SEND_BIT_6;
+
+ when STATE_SEND_BIT_6 =>
+ SER_OUT <= DATUM(6);
+ STATE <= STATE_SEND_BIT_7;
+
+ when STATE_SEND_BIT_7 =>
+ SER_OUT <= DATUM(7);
+ STATE <= STATE_END;
+
+ when STATE_END =>
+ SER_OUT <= '0';
+ STATE <= STATE_SEND;
+
+ when others => STATE <= STATE_END;
+ end case;
+
+ else
+ S_FIFO_READn <= '1';
+ end if; -- COUNT
+ end if; -- RESET ... / PSC_ENABLE ...
+ end if; -- PCI_CLOCK ...
+ end process;
+
+ process(PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ SYNC <= SPC_RDY_IN;
+ end if;
+ end process;
+
+end architecture PAR_SER_CON_DESIGN;
+++ /dev/null
--- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-entity PARITY is
- Port ( OE_PCI_PAR : In std_logic;
- OE_PCI_PERR : In std_logic;
- PA_ER_RE : In std_logic;
- PAR_IN : In std_logic_vector (35 downto 0);
- PAR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- PERR_CHECK : In std_logic;
- SERR_CHECK : In std_logic;
- SERR_ENA : In std_logic;
- PCI_PAR : InOut std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PERR : Out std_logic;
- SERR : Out std_logic );
-end PARITY;
-
-architecture SCHEMATIC of PARITY is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal PAR_OUT : std_logic_vector (10 downto 0);
-
- component PARITY_OUT
- Port ( OE_PCI_PAR : In std_logic;
- OE_PCI_PERR : In std_logic;
- PA_ER_RE : In std_logic;
- PAR_IN : In std_logic_vector (2 downto 0);
- PAR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_PAR_IN : In std_logic;
- PCI_RSTn : In std_logic;
- PERR_CHECK : In std_logic;
- SERR_CHECK : In std_logic;
- SERR_ENA : In std_logic;
- PCI_PAR : Out std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PERR : Out std_logic;
- SERR : Out std_logic );
- end component;
-
- component PARITY_4
- Port ( PAR_IN : In std_logic_vector (3 downto 0);
- PAR_OUT : Out std_logic );
- end component;
-
-begin
-
- I12 : PARITY_OUT
- Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
- PA_ER_RE=>PA_ER_RE,
- PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),
- PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
- PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
- PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,
- SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,
- PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,
- SERR=>SERR );
- I9 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),
- PAR_OUT=>PAR_OUT(8) );
- I11 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),
- PAR_OUT=>PAR_OUT(10) );
- I8 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),
- PAR_OUT=>PAR_OUT(7) );
- I7 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),
- PAR_OUT=>PAR_OUT(6) );
- I6 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),
- PAR_OUT=>PAR_OUT(5) );
- I5 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),
- PAR_OUT=>PAR_OUT(4) );
- I4 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),
- PAR_OUT=>PAR_OUT(3) );
- I3 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),
- PAR_OUT=>PAR_OUT(2) );
- I2 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),
- PAR_OUT=>PAR_OUT(1) );
- I1 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),
- PAR_OUT=>PAR_OUT(0) );
- I10 : PARITY_4
- Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),
- PAR_OUT=>PAR_OUT(9) );
-
-end SCHEMATIC;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: PARITY_OUT.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity PARITY_OUT is
- port(
- PCI_CLOCK :in std_logic;
- PCI_RSTn :in std_logic;
- PAR_IN :in std_logic_vector ( 2 downto 0);
- PAR_REG :in std_logic;
- SERR_CHECK :in std_logic;
- PERR_CHECK :in std_logic;
- OE_PCI_PAR :in std_logic;
- OE_PCI_PERR :in std_logic;
- PA_ER_RE :in std_logic;
- SERR_ENA :in std_logic;
- PCI_PAR_IN :in std_logic;
- PERR :out std_logic;
- SERR :out std_logic;
- PCI_PERRn :out std_logic; -- s/t/s
- PCI_SERRn :out std_logic; -- o/d
- PCI_PAR :out std_logic -- t/s
- );
-end entity PARITY_OUT;
-
-architecture PARITY_OUT_DESIGN of PARITY_OUT is
-
- signal PAR :std_logic;
- signal PAR_FF :std_logic;
- signal SERR_FF :std_logic;
- signal PERR_FF :std_logic;
-
-begin
-
- PAR <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) );
-
- process (PCI_CLOCK, PCI_RSTn)
- begin
- if PCI_RSTn = '0' then PAR_FF <= '0';
- PERR_FF <= '0';
- SERR_FF <= '0';
-
- elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
- SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
- PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
- end if;
-end process;
-
-SERR <= SERR_FF;
-PERR <= PERR_FF;
-
-PCI_PAR <= PAR_FF when OE_PCI_PAR = '1' else 'Z';
-PCI_SERRn <= '0' when SERR_FF = '1' else 'Z';
-PCI_PERRn <= not PERR_FF when OE_PCI_PERR = '1' and PA_ER_RE = '1' else 'Z';
-
-end architecture PARITY_OUT_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: COMM_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity COMM_FSM is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ PCI_RSTn :in std_logic;
+ IO_READ :in std_logic;
+ IO_WRITE :in std_logic;
+ CONF_READ :in std_logic;
+ CONF_WRITE :in std_logic;
+ DEVSELn :in std_logic;
+
+ IO_RD_COM : out std_logic;--> MUX_SEL(0)
+ CF_RD_COM :out std_logic;
+ IO_WR_COM :out std_logic;
+ CF_WR_COM :out std_logic
+ );
+end entity COMM_FSM;
+
+architecture COMM_FSM_DESIGN of COMM_FSM is
+
+
+ --**********************************************************
+ --*** COMMAND FSM CODIERUNG ***
+ --**********************************************************
+ --
+ --
+ -- |--------- IO_RD_COM
+ -- ||-------- CF_RD_COM
+ -- |||------- IO_WR_COM
+ -- ||||------ CF_WR_COM
+ -- ||||
+ constant ST_IDLE_COMM :std_logic_vector (3 downto 0) := "0000";--
+ constant ST_CONF_WRITE :std_logic_vector (3 downto 0) := "0001";--
+ constant ST_IO_WRITE :std_logic_vector (3 downto 0) := "0010";--
+ constant ST_CONF_READ :std_logic_vector (3 downto 0) := "0100";--
+ constant ST_IO_READ :std_logic_vector (3 downto 0) := "1000";--
+
+ signal COMM_STATE :std_logic_vector (3 downto 0);
+
+ --************************************************************
+ --*** FSM SPEICHER-AUTOMAT ***
+ --************************************************************
+
+ attribute syn_state_machine : boolean;
+ attribute syn_state_machine of COMM_STATE : signal is false;
+
+begin
+
+ --**********************************************************
+ --*** COMMAND FSM ***
+ --**********************************************************
+
+ process (PCI_CLOCK, PCI_RSTn)
+ begin
+ if PCI_RSTn = '0' then
+ COMM_STATE <= "0000";
+
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ case COMM_STATE is
+ when ST_IDLE_COMM =>
+ if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
+
+ elsif CONF_READ = '1' then
+ COMM_STATE <= ST_CONF_READ;
+
+ elsif IO_WRITE = '1' then
+ COMM_STATE <= ST_IO_WRITE;
+
+ elsif CONF_WRITE = '1' then
+ COMM_STATE <= ST_CONF_WRITE;
+
+ else
+ COMM_STATE <= ST_IDLE_COMM;
+ end if;
+
+ when ST_IO_READ =>
+ if DEVSELn = '1' then
+ COMM_STATE <= ST_IDLE_COMM;
+ end if;
+
+ when ST_CONF_READ =>
+ if DEVSELn = '1' then
+ COMM_STATE <= ST_IDLE_COMM;
+ end if;
+
+ when ST_IO_WRITE =>
+ if DEVSELn = '1' then
+ COMM_STATE <= ST_IDLE_COMM;
+ end if;
+
+ when ST_CONF_WRITE =>
+ if DEVSELn = '1' then
+ COMM_STATE <= ST_IDLE_COMM;
+ end if;
+
+ when others =>
+ COMM_STATE <= ST_IDLE_COMM;
+
+ end case; -- COMM_STATE
+ end if; -- CLOCK
+end process; -- PROCESS
+
+ IO_RD_COM <= COMM_STATE(3);
+ CF_RD_COM <= COMM_STATE(2);
+ IO_WR_COM <= COMM_STATE(1);
+ CF_WR_COM <= COMM_STATE(0);
+
+end architecture COMM_FSM_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONNECTING_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity CONNECTING_FSM is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ RESET :in std_logic;
+ PSC_ENABLE :in std_logic;
+ SYNC_S_FIFO_EFn :in std_logic;
+ SPC_ENABLE :in std_logic;
+ SYNC_R_FIFO_FFn :in std_logic;
+ S_FIFO_Q_OUT :in std_logic_vector(7 downto 0);
+ S_FIFO_READn :out std_logic;
+ R_FIFO_WRITEn :out std_logic;
+ R_FIFO_D_IN :out std_logic_vector(7 downto 0)
+ );
+end entity CONNECTING_FSM;
+
+architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
+
+ signal REG :std_logic_vector(7 downto 0);
+ signal HELP_0,HELP_1 :std_logic;
+ signal SIG_LOAD :std_logic;
+
+
+ --**********************************************************
+ --*** CONNECTING FSM CODIERUNG ***
+ --**********************************************************
+ --
+ --
+ -- ---------- HELP_0
+ -- |--------- HELP_1
+ -- ||-------- LOAD
+ -- |||------- WRITE
+ -- ||||------ READ
+ -- |||||
+ constant S0 :std_logic_vector(4 downto 0) := "00011";--
+ constant S1 :std_logic_vector(4 downto 0) := "01010";--READ
+ constant S2 :std_logic_vector(4 downto 0) := "10010";--READ
+ constant S3 :std_logic_vector(4 downto 0) := "11110";--READ,LOAD
+ constant S4 :std_logic_vector(4 downto 0) := "11011";--
+ constant S5 :std_logic_vector(4 downto 0) := "01001";--WRITE
+ constant S6 :std_logic_vector(4 downto 0) := "10001";--WRITE
+ constant S7 :std_logic_vector(4 downto 0) := "11001";--WRITE
+
+ signal STATES :std_logic_vector(4 downto 0);
+
+ --************************************************************
+ --*** FSM SPEICHER-AUTOMAT ***
+ --************************************************************
+
+ attribute syn_state_machine : boolean;
+ attribute syn_state_machine of STATES : signal is false;
+
+--************************************************************
+--*** REGISTER BESCHREIBUNG ***
+--************************************************************
+
+begin
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if SIG_LOAD = '1' then
+ REG <= S_FIFO_Q_OUT;
+
+ elsif SIG_LOAD = '0' then
+ REG <= REG;
+ end if;
+ end if;
+ end process;
+
+ --************************************************************
+ --*** FSM BESCHREIBUNG ***
+ --************************************************************
+
+process (PCI_CLOCK)
+begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+ if RESET = '1' then
+ STATES <= S0;
+ else
+
+ case STATES is
+
+ when S0 =>
+ if PSC_ENABLE = '1' and SPC_ENABLE = '1' and SYNC_S_FIFO_EFn = '1' then
+ STATES <= S1;
+ else
+ STATES <= S0;
+ end if;
+
+ when S1 =>
+ STATES <= S2;
+
+ when S2 =>
+ STATES <= S3;
+
+ when S3 =>
+ STATES <= S4;
+
+ when S4 =>
+ if SYNC_R_FIFO_FFn = '1' then
+ STATES <= S5;
+ else
+ STATES <= S4;
+ end if;
+
+ when S5 =>
+ STATES <= S6;
+
+ when S6 =>
+ STATES <= S7;
+
+ when S7 =>
+ STATES <= S0;
+
+ when others =>
+ STATES <= S0;
+
+ end case; -- STATES
+ end if; -- RESET
+ end if; -- PCI_CLOCK
+end process; -- PROCESS
+
+ --************************************************************
+ --*** ZUWEISUNG signal/out <= STATES ***
+ --************************************************************
+
+HELP_0 <= STATES(4);
+HELP_1 <= STATES(3);
+SIG_LOAD <= STATES(2);
+R_FIFO_WRITEn <= STATES(1);
+S_FIFO_READn <= STATES(0);
+
+R_FIFO_D_IN <= REG;
+
+end architecture CONNECTING_FSM_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONT_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity CONT_FSM is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ PCI_RSTn :in std_logic;
+ IO_READ :in std_logic;
+ IO_WRITE :in std_logic;
+ CONF_READ :in std_logic;
+ CONF_WRITE :in std_logic;
+ FIFO_READ :in std_logic;
+ READ :out std_logic;--> MUX_SEL(1) , OE_PCI_AD
+ PERR_CHECK :out std_logic;
+ DEVSELn :out std_logic;
+ OE_PCI_PAR :out std_logic;
+ OE_PCI_PERR :out std_logic;
+ TRDYn :out std_logic;
+ PCI_TRDYn :out std_logic; -- s/t/s
+ PCI_STOPn :out std_logic; -- s/t/s
+ PCI_DEVSELn :out std_logic; -- s/t/s
+ FIFO_RDn :out std_logic
+ );
+end entity CONT_FSM;
+
+architecture CONT_FSM_DESIGN of CONT_FSM is
+
+
+
+ --**********************************************************
+ --*** CONTROL FSM CODIERUNG ***
+ --**********************************************************
+ --
+ --
+ --
+ -- |----------- HELP
+ -- ||---------- FIFO_READn
+ -- |||--------- OE_PCI_PERR
+ -- ||||-------- PERR_CHECK
+ -- |||||------- TRDYn
+ -- ||||||------ STOPn
+ -- |||||||----- DEVSELn
+ -- ||||||||---- OE_PCI_PAR
+ -- |||||||||--- OE_CONTROL
+ -- ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD
+ -- ||||||||||
+ constant ST_IDLE :std_logic_vector (9 downto 0) := "0100111000";-- 138
+
+ constant ST_READ_1 :std_logic_vector (9 downto 0) := "0100110011";-- 133
+ constant ST_READ_2 :std_logic_vector (9 downto 0) := "0100000111";-- 107
+ constant ST_READ_3 :std_logic_vector (9 downto 0) := "0100111111";-- 13F
+
+ constant ST_RD_FIFO_1 :std_logic_vector (9 downto 0) := "0000110011";-- 033
+ constant ST_RD_FIFO_2 :std_logic_vector (9 downto 0) := "1100110011";-- 233
+
+
+ constant ST_WRITE_1 :std_logic_vector (9 downto 0) := "0111110010";-- 1F2
+ constant ST_WRITE_2 :std_logic_vector (9 downto 0) := "0110000010";-- 182
+ constant ST_WRITE_3 :std_logic_vector (9 downto 0) := "0110111010";-- 1BA
+
+ signal CONTROL_STATE :std_logic_vector (9 downto 0);
+
+
+ --signal DEVSELn :std_logic;
+ signal STOPn :std_logic;
+ --signal TRDYn :std_logic;
+
+ --************************************************************
+ --*** FSM SPEICHER-AUTOMAT ***
+ --************************************************************
+
+ attribute syn_state_machine : boolean;
+ attribute syn_state_machine of CONTROL_STATE : signal is false;
+
+begin
+
+ --**********************************************************
+ --*** CONTROL FSM ***
+ --**********************************************************
+
+ process (PCI_CLOCK, PCI_RSTn)
+ begin
+ if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE;
+
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+ case CONTROL_STATE is
+ when ST_IDLE =>
+ if IO_READ = '1' then
+ CONTROL_STATE <= ST_READ_1;
+
+ elsif CONF_READ = '1' then
+ CONTROL_STATE <= ST_READ_1;
+
+ elsif IO_WRITE = '1' then
+ CONTROL_STATE <= ST_WRITE_1;
+
+ elsif CONF_WRITE = '1' then
+ CONTROL_STATE <= ST_WRITE_1;
+
+ else CONTROL_STATE <= ST_IDLE;
+ end if;
+
+ -- when ST_READ_1 =>
+ -- CONTROL_STATE <= ST_READ_2;
+
+ when ST_READ_1 =>
+ if FIFO_READ = '1' then
+ CONTROL_STATE <= ST_RD_FIFO_1;
+ else
+ CONTROL_STATE <= ST_READ_2;
+ end if;
+
+ when ST_READ_2 =>
+ CONTROL_STATE <= ST_READ_3;
+
+ when ST_READ_3 =>
+ CONTROL_STATE <= ST_IDLE;
+
+ when ST_RD_FIFO_1=>
+ CONTROL_STATE <= ST_RD_FIFO_2;
+
+ when ST_RD_FIFO_2=>
+ CONTROL_STATE <= ST_READ_2;
+
+ when ST_WRITE_1 =>
+ CONTROL_STATE <= ST_WRITE_2;
+
+ when ST_WRITE_2 =>
+ CONTROL_STATE <= ST_WRITE_3;
+
+ when ST_WRITE_3 =>
+ CONTROL_STATE <= ST_IDLE;
+
+ when others =>
+ CONTROL_STATE <= ST_IDLE;
+
+ end case; -- COMM_STATE
+ end if; -- CLOCK
+end process; -- PROCESS
+
+
+READ <= CONTROL_STATE(0);
+--OE_CONTROL <= CONTROL_STATE(1);
+OE_PCI_PAR <= CONTROL_STATE(2);
+DEVSELn <= CONTROL_STATE(3);
+STOPn <= CONTROL_STATE(4);
+TRDYn <= CONTROL_STATE(5);
+PERR_CHECK <= CONTROL_STATE(6);
+OE_PCI_PERR <= CONTROL_STATE(7);
+
+FIFO_RDn <= CONTROL_STATE(8);
+
+
+PCI_DEVSELn <= CONTROL_STATE(3) when CONTROL_STATE(1) = '1' else 'Z';
+PCI_STOPn <= STOPn when CONTROL_STATE(1) = '1' else 'Z';
+PCI_TRDYn <= CONTROL_STATE(5) when CONTROL_STATE(1) = '1' else 'Z';
+
+end architecture CONT_FSM_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: DATA_MUX.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity DATA_MUX is
+ port
+ (
+ READ_SEL :in std_logic_vector( 1 downto 0);
+ ADDR_REG :in std_logic_vector(31 downto 0);
+ CBE_REGn :in std_logic_vector( 3 downto 0);
+ MUX_IN_XX0 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX1 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX2 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX3 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX4 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX5 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX6 :in std_logic_vector( 7 downto 0);
+ MUX_IN_XX7 :in std_logic_vector( 7 downto 0);
+ MUX_OUT :out std_logic_vector(31 downto 0);
+ READ_XX1_0 :out std_logic;
+ READ_XX3_2 :out std_logic;
+ READ_XX5_4 :out std_logic;
+ READ_XX7_6 :out std_logic
+ --READ_FIFO :out std_logic
+ );
+end entity DATA_MUX;
+
+architecture DATA_MUX_DESIGN of DATA_MUX is
+
+ signal MUX :std_logic_vector(31 downto 0);
+ signal SEL :std_logic_vector( 7 downto 0);
+
+ signal SIG_READ_XX1_0 :std_logic;
+ signal SIG_READ_XX3_2 :std_logic;
+ signal SIG_READ_XX5_4 :std_logic;
+ signal SIG_READ_XX7_6 :std_logic;
+
+begin
+
+ SEL <= ADDR_REG(3 downto 2) & CBE_REGn & READ_SEL;
+
+ SIG_READ_XX1_0 <= '1' when SEL = "00110011" else '0';
+ SIG_READ_XX3_2 <= '1' when SEL = "00001111" else '0';
+ SIG_READ_XX5_4 <= '1' when SEL = "01110011" else '0';
+ SIG_READ_XX7_6 <= '1' when SEL = "01001111" else '0';
+
+ MUX <= (X"00" & X"00" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else
+ (MUX_IN_XX3 & MUX_IN_XX2 & X"00" & X"00" ) when SIG_READ_XX3_2 = '1' else
+ (X"00" & X"00" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else
+ (MUX_IN_XX7 & MUX_IN_XX6 & X"00" & X"00" ) when SIG_READ_XX7_6 = '1' else
+ (others => '0');
+
+
+ -- MUX <= (X"01" & X"23" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else
+ -- (MUX_IN_XX3 & MUX_IN_XX2 & X"45" & X"67" ) when SIG_READ_XX3_2 = '1' else
+ -- (X"89" & X"AB" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else
+ -- (MUX_IN_XX7 & MUX_IN_XX6 & X"CD" & X"EF" ) when SIG_READ_XX7_6 = '1' else
+ -- (others => '0');
+
+
+ MUX_OUT <= MUX;
+
+
+ READ_XX1_0 <= SIG_READ_XX1_0;
+ READ_XX3_2 <= SIG_READ_XX3_2;
+ READ_XX5_4 <= SIG_READ_XX5_4;
+ READ_XX7_6 <= SIG_READ_XX7_6;
+
+--READ_FIFO <= SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test
+
+end architecture DATA_MUX_DESIGN;
--- /dev/null
+-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity FIFO_CONTROL is
+ Port ( FIFO_RDn : In std_logic;
+ FLAG_IN_0 : In std_logic;
+ FLAG_IN_4 : In std_logic;
+ HOLD : In std_logic;
+ KONST_1 : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PSC_ENABLE : In std_logic;
+ R_EFn : In std_logic;
+ R_FFn : In std_logic;
+ R_HFn : In std_logic;
+ RESET : In std_logic;
+ S_EFn : In std_logic;
+ S_FFn : In std_logic;
+ S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
+ S_HFn : In std_logic;
+ SERIAL_IN : In std_logic;
+ SPC_ENABLE : In std_logic;
+ SPC_RDY_IN : In std_logic;
+ WRITE_XX1_0 : In std_logic;
+ R_ERROR : Out std_logic;
+ R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
+ R_FIFO_READn : Out std_logic;
+ R_FIFO_RESETn : Out std_logic;
+ R_FIFO_RETRANSMITn : Out std_logic;
+ R_FIFO_WRITEn : Out std_logic;
+ RESERVE : Out std_logic;
+ S_ERROR : Out std_logic;
+ S_FIFO_READn : Out std_logic;
+ S_FIFO_RESETn : Out std_logic;
+ S_FIFO_RETRANSMITn : Out std_logic;
+ S_FIFO_WRITEn : Out std_logic;
+ SERIAL_OUT : Out std_logic;
+ SPC_RDY_OUT : Out std_logic;
+ SR_ERROR : Out std_logic;
+ SYNC_FLAG : Out std_logic_vector (7 downto 0));
+end FIFO_CONTROL;
+
+architecture SCHEMATIC of FIFO_CONTROL is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal XXXR_FIFO_WRITEn : std_logic;
+ signal XXXS_FIFO_READn : std_logic;
+ signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
+ signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
+
+ component SER_PAR_CON
+ Port ( PCI_CLOCK : In std_logic;
+ RESET : In std_logic;
+ SERIAL_IN : In std_logic;
+ SPC_ENABLE : In std_logic;
+ SYNC_R_FIFO_FFn : In std_logic;
+ PAR_OUT : Out std_logic_vector (7 downto 0);
+ R_FIFO_WRITEn : Out std_logic;
+ SPC_RDY_OUT : Out std_logic );
+ end component;
+
+ component PAR_SER_CON
+ Port ( PAR_IN : In std_logic_vector (7 downto 0);
+ PCI_CLOCK : In std_logic;
+ PSC_ENABLE : In std_logic;
+ RESET : In std_logic;
+ SPC_RDY_IN : In std_logic;
+ SYNC_S_FIFO_EFn : In std_logic;
+ S_FIFO_READn : Out std_logic;
+ SER_OUT : Out std_logic );
+ end component;
+
+ component FIFO_IO_CONTROL
+ Port ( FIFO_RDn : In std_logic;
+ PCI_CLOCK : In std_logic;
+ RESET : In std_logic;
+ SYNC_FLAG_1 : In std_logic;
+ SYNC_FLAG_7 : In std_logic;
+ WRITE_XX1_0 : In std_logic;
+ R_ERROR : Out std_logic;
+ R_FIFO_READn : Out std_logic;
+ R_FIFO_RESETn : Out std_logic;
+ R_FIFO_RETRANSMITn : Out std_logic;
+ S_ERROR : Out std_logic;
+ S_FIFO_RESETn : Out std_logic;
+ S_FIFO_RETRANSMITn : Out std_logic;
+ S_FIFO_WRITEn : Out std_logic;
+ SR_ERROR : Out std_logic );
+ end component;
+
+ component CONNECTING_FSM
+ Port ( PCI_CLOCK : In std_logic;
+ PSC_ENABLE : In std_logic;
+ RESET : In std_logic;
+ S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
+ SPC_ENABLE : In std_logic;
+ SYNC_R_FIFO_FFn : In std_logic;
+ SYNC_S_FIFO_EFn : In std_logic;
+ R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
+ R_FIFO_WRITEn : Out std_logic;
+ S_FIFO_READn : Out std_logic );
+ end component;
+
+ component FLAG_BUS
+ Port ( FLAG_IN_0 : In std_logic;
+ FLAG_IN_4 : In std_logic;
+ HOLD : In std_logic;
+ KONS_1 : In std_logic;
+ PCI_CLOCK : In std_logic;
+ R_EFn : In std_logic;
+ R_FFn : In std_logic;
+ R_HFn : In std_logic;
+ S_EFn : In std_logic;
+ S_FFn : In std_logic;
+ S_HFn : In std_logic;
+ SYNC_FLAG : Out std_logic_vector (7 downto 0) );
+ end component;
+
+begin
+
+ SYNC_FLAG <= SYNC_FLAG_DUMMY;
+
+ RESERVE <= gnd;
+ I23 : SER_PAR_CON
+ Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
+ SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
+ SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
+ PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
+ R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
+ I22 : PAR_SER_CON
+ Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
+ RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
+ SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
+ S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
+ I21 : FIFO_IO_CONTROL
+ Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
+ SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
+ SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
+ WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
+ R_FIFO_READn=>R_FIFO_READn,
+ R_FIFO_RESETn=>R_FIFO_RESETn,
+ R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
+ S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
+ S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
+ S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
+ I20 : CONNECTING_FSM
+ Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
+ RESET=>RESET,
+ S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+ SPC_ENABLE=>SPC_ENABLE,
+ SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
+ SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
+ R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
+ R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
+ S_FIFO_READn=>XXXS_FIFO_READn );
+ I19 : FLAG_BUS
+ Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
+ KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
+ R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
+ S_HFn=>S_HFn,
+ SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
+
+end SCHEMATIC;
--- /dev/null
+-- $Id: fifo_io_control.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FIFO_IO_CONTROL is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ WRITE_XX1_0 :in std_logic; -- PCI Write
+ FIFO_RDn :in std_logic; -- FIFO Read (low active)
+ RESET :in std_logic;
+ SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
+ SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
+ S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
+ R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
+ S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
+ R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
+ S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
+ R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
+ S_ERROR :out std_logic; -- Send ERROR
+ R_ERROR :out std_logic; -- Recv ERROR
+ SR_ERROR :out std_logic -- Send / Recv Error
+ );
+end entity FIFO_IO_CONTROL;
+
+architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is
+
+ signal SIG_S_ERROR :std_logic; -- Send Error
+ signal SIG_R_ERROR :std_logic; -- Recv Error
+
+begin
+
+ -- FIFO Write
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if (RESET = '1') then
+ S_FIFO_WRITEn <= '1';
+ SIG_S_ERROR <= '0';
+
+ elsif (WRITE_XX1_0 = '0') then
+ S_FIFO_WRITEn <= '1';
+
+ elsif (WRITE_XX1_0 = '1') then
+ if (SYNC_FLAG_7 = '0') then
+ SIG_S_ERROR <= '1';
+
+ elsif (SYNC_FLAG_7 = '1') then
+ S_FIFO_WRITEn <= '0';
+ SIG_S_ERROR <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ S_ERROR <= SIG_S_ERROR;
+
+ -- FIFO Read
+
+ R_FIFO_READn <= FIFO_RDn;
+
+-- Receive Error
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ if (RESET = '1') then
+ SIG_R_ERROR <= '0';
+
+ elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
+ SIG_R_ERROR <= '1';
+ end if;
+ end if;
+ end process;
+
+ R_ERROR <= SIG_R_ERROR;
+
+-- Send or Receive Error
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;
+ end if;
+ end process;
+
+-- FIFO Reset
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ S_FIFO_RESETn <= not RESET;
+ R_FIFO_RESETn <= not RESET;
+ end if;
+ end process;
+
+
+-- FIFO Retransmit
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+ S_FIFO_RETRANSMITn <= '1';
+ R_FIFO_RETRANSMITn <= '1';
+ end if;
+ end process;
+
+end architecture FIFO_IO_CONTROL_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: FLAG_BUS.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FLAG_BUS is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ KONS_1 :in std_logic;
+ FLAG_IN_0 :in std_logic;
+ R_EFn :in std_logic;
+ R_HFn :in std_logic;
+ R_FFn :in std_logic;
+ FLAG_IN_4 :in std_logic;
+ S_EFn :in std_logic;
+ S_HFn :in std_logic;
+ S_FFn :in std_logic;
+ HOLD :in std_logic;
+ SYNC_FLAG :out std_logic_vector (7 downto 0)
+ );
+end entity FLAG_BUS;
+
+architecture FLAG_BUS_DESIGN of FLAG_BUS is
+
+
+ signal FF1_S_EFn :std_logic;
+ signal FF1_S_HFn :std_logic;
+ signal FF1_S_FFn :std_logic;
+ signal FF1_R_EFn :std_logic;
+ signal FF1_R_HFn :std_logic;
+ signal FF1_R_FFn :std_logic;
+
+ signal FF2_S_EFn :std_logic;
+ signal FF2_S_HFn :std_logic;
+ signal FF2_S_FFn :std_logic;
+ signal FF2_R_EFn :std_logic;
+ signal FF2_R_HFn :std_logic;
+ signal FF2_R_FFn :std_logic;
+
+begin
+
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ FF1_S_EFn <= not S_EFn;
+ FF1_S_HFn <= not S_HFn;
+ FF1_S_FFn <= not S_FFn;
+ FF1_R_EFn <= not R_EFn;
+ FF1_R_HFn <= not R_HFn;
+ FF1_R_FFn <= not R_FFn;
+ end if;
+ end process;
+
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if HOLD = '0' then
+ FF2_S_EFn <= FF1_S_EFn;
+ FF2_S_HFn <= FF1_S_HFn;
+ FF2_S_FFn <= FF1_S_FFn;
+ FF2_R_EFn <= FF1_R_EFn;
+ FF2_R_HFn <= FF1_R_HFn;
+ FF2_R_FFn <= FF1_R_FFn;
+
+ elsif HOLD = '1' then
+ FF2_S_EFn <= FF2_S_EFn;
+ FF2_S_HFn <= FF2_S_HFn;
+ FF2_S_FFn <= FF2_S_FFn;
+ FF2_R_EFn <= FF2_R_EFn;
+ FF2_R_HFn <= FF2_R_HFn;
+ FF2_R_FFn <= FF2_R_FFn;
+ end if;
+ end if;
+ end process;
+
+SYNC_FLAG(0) <= FLAG_IN_0;
+SYNC_FLAG(1) <= FF2_R_EFn;
+SYNC_FLAG(2) <= FF2_R_HFn;
+SYNC_FLAG(3) <= FF2_R_FFn;
+SYNC_FLAG(4) <= FLAG_IN_4;
+SYNC_FLAG(5) <= FF2_S_EFn;
+SYNC_FLAG(6) <= FF2_S_HFn;
+SYNC_FLAG(7) <= FF2_S_FFn;
+
+end architecture FLAG_BUS_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: INTERRUPT.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity INTERRUPT is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ PCI_RSTn :in std_logic; -- PCI reset is asynchron (low active)
+ RESET :in std_logic;
+ TAST_SETn :in std_logic;
+ TAST_RESn :in std_logic;
+ INT_IN_0 :in std_logic;
+ INT_IN_1 :in std_logic;
+ INT_IN_2 :in std_logic;
+ INT_IN_3 :in std_logic;
+ INT_IN_4 :in std_logic;
+ INT_IN_5 :in std_logic;
+ INT_IN_6 :in std_logic;
+ INT_IN_7 :in std_logic;
+ TRDYn :in std_logic; -- event 1 after read of Interrupt status register (low active)
+ READ_XX5_4 :in std_logic; -- event 2 after read of Interrupt status register
+ INT_RES :in std_logic_vector(7 downto 0); -- clear selected interrupts
+ INT_MASKE :in std_logic_vector(7 downto 0); -- interrupt mask register
+ INT_REG :out std_logic_vector(7 downto 0); -- interrupt status register
+ INTAn :out std_logic; -- second interrupt line for PCI analyzer
+ PCI_INTAn :out std_logic -- PCI interrupt line
+ );
+
+end entity INTERRUPT;
+
+architecture INTERRUPT_DESIGN of INTERRUPT is
+
+ signal SIG_TAST_Q :std_logic;
+ signal SIG_TAST_Qn :std_logic;
+
+
+ signal SIG_INTA :std_logic;
+
+ signal FF_A :std_logic_vector(7 downto 0);
+ signal FF_B :std_logic_vector(7 downto 0);
+ signal SET :std_logic_vector(7 downto 0);
+
+ signal SIG_PROPAGATE_INT :std_logic;
+ signal SIG_PROPAGATE_INT_SECOND :std_logic;
+ signal REG :std_logic_vector(7 downto 0);
+
+begin
+
+
+
+
+ ------------------------------------------------------
+ process (PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+
+ -- THIS IS BROKEN (it cycles the interrupt)
+ SIG_TAST_Q <= not (TAST_SETn and SIG_TAST_Qn);
+ SIG_TAST_Qn <= not (TAST_RESn and SIG_TAST_Q);
+
+ end if;
+ end process;
+
+ ------------------------------------------------------
+
+ process (PCI_CLOCK)
+ begin
+ if (PCI_RSTn = '0') then
+ SET <= "00000000";
+ FF_A <= "00000000";
+ FF_B <= "00000000";
+
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if (RESET = '1') then
+ SET <= "00000000";
+ FF_A <= "00000000";
+ FF_B <= "00000000";
+ else
+ FF_A(0) <= INT_IN_0; -- Receive FIFO Empty Flag
+
+ FF_A(1) <= INT_IN_1; -- Send FIFO Half Full
+ FF_A(2) <= INT_IN_2;
+ FF_A(3) <= INT_IN_3;
+
+ FF_A(4) <= INT_IN_4;
+
+ FF_A(5) <= INT_IN_5;
+ FF_A(6) <= INT_IN_6;
+ FF_A(7) <= INT_IN_7;
+
+ FF_B <= FF_A;
+
+ SET <= FF_A AND not FF_B;
+ end if;
+ end if;
+ end process;
+
+ process (PCI_CLOCK,PCI_RSTn)
+ begin
+ if (PCI_RSTn = '0') then
+ REG <= "00000000";
+
+ elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if(RESET = '1') then
+ REG <= "00000000";
+
+ -- elsif(SIG_TAST_Q = '1') then
+ -- REG <= "00000000" or SET;
+
+ elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
+ REG <= (REG AND NOT INT_RES) OR SET;
+ else
+ REG <= REG OR SET;
+ end if;
+ end if;
+ end process;
+
+ SIG_PROPAGATE_INT <=
+ (REG(0) AND INT_MASKE(0))
+ OR (REG(1) AND INT_MASKE(1))
+ OR (REG(2) AND INT_MASKE(2))
+ OR (REG(3) AND INT_MASKE(3))
+ OR (REG(4) AND INT_MASKE(4))
+ OR (REG(5) AND INT_MASKE(5))
+ OR (REG(6) AND INT_MASKE(6))
+ OR (REG(7) AND INT_MASKE(7));
+
+ process (PCI_CLOCK)
+ begin
+ if(PCI_CLOCK'event and PCI_CLOCK = '1') then
+ SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
+ end if;
+ end process;
+
+ INTAn <= not SIG_PROPAGATE_INT_SECOND;
+ PCI_INTAn <= '0' when SIG_PROPAGATE_INT_SECOND = '0' else 'Z';
+ INT_REG <= REG;
+
+end architecture INTERRUPT_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity IO_MUX is
+ port
+ (
+ READ_SEL :in std_logic_vector ( 1 downto 0);
+ USER_DATA :in std_logic_vector (31 downto 0);
+ CONFIG_DATA :in std_logic_vector (31 downto 0);
+ PCI_AD :in std_logic_vector (31 downto 0);
+ IO_DATA :out std_logic_vector (31 downto 0)
+ );
+end entity IO_MUX;
+
+architecture IO_MUX_DESIGN of IO_MUX is
+
+ signal MUX :std_logic_vector (31 downto 0);
+
+begin
+
+ MUX <= PCI_AD when READ_SEL = "00" else -- WRITE_CONFIG
+ PCI_AD when READ_SEL = "01" else -- WRITE_IO
+ CONFIG_DATA when READ_SEL = "10" else -- READ_CONFIG
+ USER_DATA when READ_SEL = "11" else -- READ_IO
+ CONFIG_DATA;
+
+ -- MUX;
+
+ IO_DATA <= MUX;
+
+end architecture IO_MUX_DESIGN;
--- /dev/null
+-- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity IO_MUX_REG is
+ Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
+ LOAD_ADDR_REG : In std_logic;
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_PAR : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_SEL : In std_logic_vector (1 downto 0);
+ USER_DATA : In std_logic_vector (31 downto 0);
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ AD_REG : Out std_logic_vector (31 downto 0);
+ ADDR_REG : Out std_logic_vector (31 downto 0);
+ CBE_REGn : Out std_logic_vector (3 downto 0);
+ FRAME_REGn : Out std_logic;
+ IDSEL_REG : Out std_logic;
+ IRDY_REGn : Out std_logic;
+ PAR_REG : Out std_logic );
+end IO_MUX_REG;
+
+architecture SCHEMATIC of IO_MUX_REG is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal IO_DATA : std_logic_vector (31 downto 0);
+ signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+
+ component ADDRESS_REGISTER
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ LOAD_ADDR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ ADDR_REG : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component IO_REG
+ Port ( IO_DATA : In std_logic_vector (31 downto 0);
+ OE_PCI_AD : In std_logic;
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_PAR : In std_logic;
+ PCI_RSTn : In std_logic;
+ AD_REG : Out std_logic_vector (31 downto 0);
+ CBE_REGn : Out std_logic_vector (3 downto 0);
+ FRAME_REGn : Out std_logic;
+ IDSEL_REG : Out std_logic;
+ IRDY_REGn : Out std_logic;
+ PAR_REG : Out std_logic;
+ PCI_AD : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component IO_MUX
+ Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
+ PCI_AD : In std_logic_vector (31 downto 0);
+ READ_SEL : In std_logic_vector (1 downto 0);
+ USER_DATA : In std_logic_vector (31 downto 0);
+ IO_DATA : Out std_logic_vector (31 downto 0) );
+ end component;
+
+begin
+
+ AD_REG <= AD_REG_DUMMY;
+
+ I5 : ADDRESS_REGISTER
+ Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn,
+ ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );
+ I1 : IO_REG
+ Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),
+ OE_PCI_AD=>READ_SEL(1),
+ PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+ PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+ PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
+ AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+ IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );
+ I2 : IO_MUX
+ Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+ READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
+ USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),
+ IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );
+
+end SCHEMATIC;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity IO_REG is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ PCI_RSTn :in std_logic;
+ PCI_FRAMEn :in std_logic;
+ PCI_IRDYn :in std_logic;
+ PCI_IDSEL :in std_logic;
+ PCI_PAR :in std_logic;
+ PCI_CBEn :in std_logic_vector ( 3 downto 0);
+ OE_PCI_AD :in std_logic;
+ IO_DATA :in std_logic_vector (31 downto 0);
+ AD_REG :out std_logic_vector (31 downto 0);
+ CBE_REGn :out std_logic_vector ( 3 downto 0);
+ FRAME_REGn :out std_logic;
+ IRDY_REGn :out std_logic;
+ IDSEL_REG :out std_logic;
+ PAR_REG :out std_logic;
+ PCI_AD :out std_logic_vector (31 downto 0) -- t/s
+ );
+end entity IO_REG;
+
+architecture IO_REG_DESIGN of IO_REG is
+
+ signal REG_AD :std_logic_vector (31 downto 0);
+ signal REG_CBEn :std_logic_vector ( 3 downto 0);
+ signal REG_FRAMEn :std_logic;
+ signal REG_IRDYn :std_logic;
+ signal REG_IDSEL :std_logic;
+ signal REG_PAR :std_logic;
+
+begin
+
+ process (PCI_CLOCK, PCI_RSTn)
+ begin
+ if PCI_RSTn = '0' then
+ REG_AD <= X"00000000";
+ REG_CBEn <= "0000";
+ REG_FRAMEn <= '1';
+ REG_IRDYn <= '1';
+ REG_IDSEL <= '0';
+ REG_PAR <= '0';
+
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ REG_AD <= IO_DATA;
+ REG_CBEn <= PCI_CBEn;
+ REG_FRAMEn <= PCI_FRAMEn;
+ REG_IRDYn <= PCI_IRDYn;
+ REG_IDSEL <= PCI_IDSEL;
+ REG_PAR <= PCI_PAR;
+ end if;
+ end process;
+
+ PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');
+
+ AD_REG <= REG_AD;
+ CBE_REGn <= REG_CBEn;
+ FRAME_REGn <= REG_FRAMEn;
+ IRDY_REGn <= REG_IRDYn;
+ IDSEL_REG <= REG_IDSEL;
+ PAR_REG <= REG_PAR;
+
+end architecture IO_REG_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_WR_SEL.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity IO_WR_SEL is
+ port
+ (
+ IO_WR_COM :in std_logic;
+ IRDY_REGn :in std_logic;
+ TRDYn :in std_logic;
+ ADDR_REG :in std_logic_vector(31 downto 0);
+ CBE_REGn :in std_logic_vector( 3 downto 0);
+ WRITE_XX1_0 :out std_logic;
+ WRITE_XX3_2 :out std_logic;
+ WRITE_XX5_4 :out std_logic;
+ WRITE_XX7_6 :out std_logic
+ );
+end entity IO_WR_SEL;
+
+--PCI Byte Enable
+--C/BE[3..0] gueltige Datenbits
+-------------------------------
+-- 0000 AD 31..0
+-- 1000 AD 23..0
+-- 1100 AD 15..0
+-- 1110 AD 7..0
+-- 0011 AD 31..16
+
+architecture IO_WR_SEL_DESIGN of IO_WR_SEL is
+
+ signal WR_ENA :std_logic;
+ signal ADDR :std_logic_vector( 5 downto 0);
+
+begin
+
+ WR_ENA <= '1' when
+ IO_WR_COM = '1' and
+ IRDY_REGn = '0' and
+ TRDYn = '0' else '0';
+
+ ADDR <= ADDR_REG(3) & ADDR_REG(2) & CBE_REGn;
+
+ WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0';
+ WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';
+ WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0';
+ WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';
+
+end architecture IO_WR_SEL_DESIGN;
--- /dev/null
+-- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity PARITY is
+ Port ( OE_PCI_PAR : In std_logic;
+ OE_PCI_PERR : In std_logic;
+ PA_ER_RE : In std_logic;
+ PAR_IN : In std_logic_vector (35 downto 0);
+ PAR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR_CHECK : In std_logic;
+ SERR_CHECK : In std_logic;
+ SERR_ENA : In std_logic;
+ PCI_PAR : InOut std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PERR : Out std_logic;
+ SERR : Out std_logic );
+end PARITY;
+
+architecture SCHEMATIC of PARITY is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal PAR_OUT : std_logic_vector (10 downto 0);
+
+ component PARITY_OUT
+ Port ( OE_PCI_PAR : In std_logic;
+ OE_PCI_PERR : In std_logic;
+ PA_ER_RE : In std_logic;
+ PAR_IN : In std_logic_vector (2 downto 0);
+ PAR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_PAR_IN : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR_CHECK : In std_logic;
+ SERR_CHECK : In std_logic;
+ SERR_ENA : In std_logic;
+ PCI_PAR : Out std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PERR : Out std_logic;
+ SERR : Out std_logic );
+ end component;
+
+ component PARITY_4
+ Port ( PAR_IN : In std_logic_vector (3 downto 0);
+ PAR_OUT : Out std_logic );
+ end component;
+
+begin
+
+ I12 : PARITY_OUT
+ Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
+ PA_ER_RE=>PA_ER_RE,
+ PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),
+ PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
+ PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
+ PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,
+ SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,
+ PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,
+ SERR=>SERR );
+ I9 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),
+ PAR_OUT=>PAR_OUT(8) );
+ I11 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),
+ PAR_OUT=>PAR_OUT(10) );
+ I8 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),
+ PAR_OUT=>PAR_OUT(7) );
+ I7 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),
+ PAR_OUT=>PAR_OUT(6) );
+ I6 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),
+ PAR_OUT=>PAR_OUT(5) );
+ I5 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),
+ PAR_OUT=>PAR_OUT(4) );
+ I4 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),
+ PAR_OUT=>PAR_OUT(3) );
+ I3 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),
+ PAR_OUT=>PAR_OUT(2) );
+ I2 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),
+ PAR_OUT=>PAR_OUT(1) );
+ I1 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),
+ PAR_OUT=>PAR_OUT(0) );
+ I10 : PARITY_4
+ Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),
+ PAR_OUT=>PAR_OUT(9) );
+
+end SCHEMATIC;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: PARITY_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity PARITY_4 is
+ port
+ (
+ PAR_IN :in std_logic_vector(3 downto 0);
+ PAR_OUT :out std_logic
+ );
+end entity PARITY_4;
+
+architecture PARITY_4_DESIGN of PARITY_4 is
+
+begin
+
+ PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);
+
+end architecture PARITY_4_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: PARITY_OUT.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity PARITY_OUT is
+ port(
+ PCI_CLOCK :in std_logic;
+ PCI_RSTn :in std_logic;
+ PAR_IN :in std_logic_vector ( 2 downto 0);
+ PAR_REG :in std_logic;
+ SERR_CHECK :in std_logic;
+ PERR_CHECK :in std_logic;
+ OE_PCI_PAR :in std_logic;
+ OE_PCI_PERR :in std_logic;
+ PA_ER_RE :in std_logic;
+ SERR_ENA :in std_logic;
+ PCI_PAR_IN :in std_logic;
+ PERR :out std_logic;
+ SERR :out std_logic;
+ PCI_PERRn :out std_logic; -- s/t/s
+ PCI_SERRn :out std_logic; -- o/d
+ PCI_PAR :out std_logic -- t/s
+ );
+end entity PARITY_OUT;
+
+architecture PARITY_OUT_DESIGN of PARITY_OUT is
+
+ signal PAR :std_logic;
+ signal PAR_FF :std_logic;
+ signal SERR_FF :std_logic;
+ signal PERR_FF :std_logic;
+
+begin
+
+ PAR <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) );
+
+ process (PCI_CLOCK, PCI_RSTn)
+ begin
+ if PCI_RSTn = '0' then PAR_FF <= '0';
+ PERR_FF <= '0';
+ SERR_FF <= '0';
+
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
+ PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
+ end if;
+end process;
+
+SERR <= SERR_FF;
+PERR <= PERR_FF;
+
+PCI_PAR <= PAR_FF when OE_PCI_PAR = '1' else 'Z';
+PCI_SERRn <= '0' when SERR_FF = '1' else 'Z';
+PCI_PERRn <= not PERR_FF when OE_PCI_PERR = '1' and PA_ER_RE = '1' else 'Z';
+
+end architecture PARITY_OUT_DESIGN;
--- /dev/null
+-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity PCI_INTERFACE is
+ Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_FIFO : In std_logic;
+ REVISON_ID : In std_logic_vector (7 downto 0);
+ USER_DATA_OUT : In std_logic_vector (31 downto 0);
+ VENDOR_ID : In std_logic_vector (15 downto 0);
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ PCI_PAR : InOut std_logic;
+ AD_REG : Out std_logic_vector (31 downto 0);
+ ADDR_REG : Out std_logic_vector (31 downto 0);
+ CBE_REGn : Out std_logic_vector (3 downto 0);
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ IO_WR_COM : Out std_logic;
+ IRDY_REGn : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ READ_SEL : Out std_logic_vector (1 downto 0);
+ TRDYn : Out std_logic );
+end PCI_INTERFACE;
+
+architecture SCHEMATIC of PCI_INTERFACE is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal IRDY_REGn_DUMMY : std_logic;
+ signal PAR_REG : std_logic;
+ signal PERR : std_logic;
+ signal SERR : std_logic;
+ signal CF_RD_COM : std_logic;
+ signal CF_WR_COM : std_logic;
+ signal LAR : std_logic;
+ signal MY_ADDR : std_logic;
+ signal SERR_CHECK : std_logic;
+ signal IDSEL_REG : std_logic;
+ signal FRAME_REGn : std_logic;
+ signal PERR_CHECK : std_logic;
+ signal OE_PCI_PAR : std_logic;
+ signal OE_PCI_PERR : std_logic;
+ signal TRDYn_DUMMY : std_logic;
+ signal CONF_DATA_10H : std_logic_vector (31 downto 0);
+ signal CONF_DATA_04H : std_logic_vector (31 downto 0);
+ signal CONF_DATA : std_logic_vector (31 downto 0);
+ signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
+ signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
+ signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+ signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);
+
+ component STEUERUNG
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ FRAME_REGn : In std_logic;
+ IDSEL_REG : In std_logic;
+ IO_SPACE : In std_logic;
+ MY_ADDR : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_FIFO : In std_logic;
+ CF_RD_COM : Out std_logic;
+ CF_WR_COM : Out std_logic;
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ IO_RD_COM : Out std_logic;
+ IO_WR_COM : Out std_logic;
+ LAR : Out std_logic;
+ OE_PCI_PAR : Out std_logic;
+ OE_PCI_PERR : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ PERR_CHECK : Out std_logic;
+ READ : Out std_logic;
+ SERR_CHECK : Out std_logic;
+ TRDYn : Out std_logic );
+ end component;
+
+ component PARITY
+ Port ( OE_PCI_PAR : In std_logic;
+ OE_PCI_PERR : In std_logic;
+ PA_ER_RE : In std_logic;
+ PAR_IN : In std_logic_vector (35 downto 0);
+ PAR_REG : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR_CHECK : In std_logic;
+ SERR_CHECK : In std_logic;
+ SERR_ENA : In std_logic;
+ PCI_PAR : InOut std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PERR : Out std_logic;
+ SERR : Out std_logic );
+ end component;
+
+ component VERGLEICH
+ Port ( IN_A : In std_logic_vector (31 downto 0);
+ IN_B : In std_logic_vector (31 downto 0);
+ GLEICH_OUT : Out std_logic );
+ end component;
+
+ component IO_MUX_REG
+ Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
+ LOAD_ADDR_REG : In std_logic;
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_PAR : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_SEL : In std_logic_vector (1 downto 0);
+ USER_DATA : In std_logic_vector (31 downto 0);
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ AD_REG : Out std_logic_vector (31 downto 0);
+ ADDR_REG : Out std_logic_vector (31 downto 0);
+ CBE_REGn : Out std_logic_vector (3 downto 0);
+ FRAME_REGn : Out std_logic;
+ IDSEL_REG : Out std_logic;
+ IRDY_REGn : Out std_logic;
+ PAR_REG : Out std_logic );
+ end component;
+
+ component CONFIG_SPACE_HEADER
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ ADDR_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ CF_RD_COM : In std_logic;
+ CF_WR_COM : In std_logic;
+ IRDY_REGn : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR : In std_logic;
+ REVISION_ID : In std_logic_vector (7 downto 0);
+ SERR : In std_logic;
+ TRDYn : In std_logic;
+ VENDOR_ID : In std_logic_vector (15 downto 0);
+ CONF_DATA : Out std_logic_vector (31 downto 0);
+ CONF_DATA_04H : Out std_logic_vector (31 downto 0);
+ CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
+ end component;
+
+begin
+
+ ADDR_REG <= ADDR_REG_DUMMY;
+ AD_REG <= AD_REG_DUMMY;
+ CBE_REGn <= CBE_REGn_DUMMY;
+ READ_SEL <= READ_SEL_DUMMY;
+ TRDYn <= TRDYn_DUMMY;
+ IRDY_REGn <= IRDY_REGn_DUMMY;
+
+ I7 : STEUERUNG
+ Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
+ FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+ IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,
+ PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
+ READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,
+ CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,
+ FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),
+ IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,
+ OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
+ PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
+ PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),
+ SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );
+ I5 : PARITY
+ Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
+ PA_ER_RE=>CONF_DATA_04H(6),
+ PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),
+ PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,
+ SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
+ PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
+ PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
+ I4 : VERGLEICH
+ Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
+ IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ GLEICH_OUT=>MY_ADDR );
+ I2 : IO_MUX_REG
+ Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
+ LOAD_ADDR_REG=>LAR,
+ PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+ PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+ PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
+ READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+ USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+ AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
+ FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+ IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );
+ I1 : CONFIG_SPACE_HEADER
+ Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
+ CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,
+ IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn, PERR=>PERR,
+ REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+ SERR=>SERR, TRDYn=>TRDYn_DUMMY,
+ VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+ CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
+ CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
+ CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
+
+end SCHEMATIC;
--- /dev/null
+-- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity PCI_TOP is
+ Port ( FLAG : In std_logic_vector (7 downto 0);
+ INT_REG : In std_logic_vector (7 downto 0);
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_RSTn : In std_logic;
+ R_FIFO_Q : In std_logic_vector (7 downto 0);
+ REVISON_ID : In std_logic_vector (7 downto 0);
+ VENDOR_ID : In std_logic_vector (15 downto 0);
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ PCI_PAR : InOut std_logic;
+ AD_REG : Out std_logic_vector (31 downto 0);
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ READ_SEL : Out std_logic_vector (1 downto 0);
+ READ_XX1_0 : Out std_logic;
+ READ_XX3_2 : Out std_logic;
+ READ_XX5_4 : Out std_logic;
+ READ_XX7_6 : Out std_logic;
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
+ TRDYn : Out std_logic;
+ WRITE_XX1_0 : Out std_logic;
+ WRITE_XX3_2 : Out std_logic;
+ WRITE_XX5_4 : Out std_logic;
+ WRITE_XX7_6 : Out std_logic );
+end PCI_TOP;
+
+architecture SCHEMATIC of PCI_TOP is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal IRDY_REGn : std_logic;
+ signal IO_WR_COM : std_logic;
+ signal TRDYn_DUMMY : std_logic;
+ signal READ_XX3_2_DUMMY : std_logic;
+ signal USER_DATA_OUT : std_logic_vector (31 downto 0);
+ signal CBE_REGn : std_logic_vector (3 downto 0);
+ signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+ signal ADDR_REG : std_logic_vector (31 downto 0);
+ signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
+
+ component USER_IO
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ ADDR_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ FLAG : In std_logic_vector (7 downto 0);
+ INT_REG : In std_logic_vector (7 downto 0);
+ IO_WR_COM : In std_logic;
+ IRDY_REGn : In std_logic;
+ PCI_CLK : In std_logic;
+ R_FIFO_Q : In std_logic_vector (7 downto 0);
+ READ_SEL : In std_logic_vector (1 downto 0);
+ TRDYn : In std_logic;
+ READ_XX1_0 : Out std_logic;
+ READ_XX3_2 : Out std_logic;
+ READ_XX5_4 : Out std_logic;
+ READ_XX7_6 : Out std_logic;
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
+ USER_DATA_OUT : Out std_logic_vector (31 downto 0);
+ WRITE_XX1_0 : Out std_logic;
+ WRITE_XX3_2 : Out std_logic;
+ WRITE_XX5_4 : Out std_logic;
+ WRITE_XX7_6 : Out std_logic );
+ end component;
+
+ component PCI_INTERFACE
+ Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_FIFO : In std_logic;
+ REVISON_ID : In std_logic_vector (7 downto 0);
+ USER_DATA_OUT : In std_logic_vector (31 downto 0);
+ VENDOR_ID : In std_logic_vector (15 downto 0);
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ PCI_PAR : InOut std_logic;
+ AD_REG : Out std_logic_vector (31 downto 0);
+ ADDR_REG : Out std_logic_vector (31 downto 0);
+ CBE_REGn : Out std_logic_vector (3 downto 0);
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ IO_WR_COM : Out std_logic;
+ IRDY_REGn : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ READ_SEL : Out std_logic_vector (1 downto 0);
+ TRDYn : Out std_logic );
+ end component;
+
+begin
+
+ READ_SEL <= READ_SEL_DUMMY;
+ AD_REG <= AD_REG_DUMMY;
+ READ_XX3_2 <= READ_XX3_2_DUMMY;
+ TRDYn <= TRDYn_DUMMY;
+
+ I19 : USER_IO
+ Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ FLAG(7 downto 0)=>FLAG(7 downto 0),
+ INT_REG(7 downto 0)=>INT_REG(7 downto 0),
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+ PCI_CLK=>PCI_CLOCK,
+ R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
+ READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+ TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
+ READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
+ READ_XX7_6=>READ_XX7_6,
+ REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
+ USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+ WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
+ WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
+ I10 : PCI_INTERFACE
+ Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+ PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+ PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
+ REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+ USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+ VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+ PCI_PAR=>PCI_PAR,
+ AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+ ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+ PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
+ PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
+ PCI_TRDYn=>PCI_TRDYn,
+ READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+ TRDYn=>TRDYn_DUMMY );
+
+end SCHEMATIC;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: REG.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity REG is
+ port
+ (
+ CLOCK :in std_logic;
+ RESET :in std_logic;
+ WRITE :in std_logic;
+ REG_IN :in std_logic_vector(7 downto 0);
+ REG_OUT :out std_logic_vector(7 downto 0)
+ );
+end entity REG;
+
+architecture REG_DESIGN of REG is
+
+ signal SIG_REG :std_logic_vector (7 downto 0);
+
+begin
+
+ process (CLOCK)
+ begin
+ if (CLOCK'event and CLOCK = '1') then
+ if RESET = '1' then
+ SIG_REG <= X"00";
+
+ elsif WRITE = '1' then
+ SIG_REG <= REG_IN;
+
+ else
+ SIG_REG <= SIG_REG;
+ end if;
+ end if;
+ end process;
+
+ REG_OUT <= SIG_REG;
+
+end architecture REG_DESIGN;
--- /dev/null
+-- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity REG_IO is
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ PCI_CLOCK : In std_logic;
+ RESET : In std_logic;
+ WRITE_XX1_0 : In std_logic;
+ WRITE_XX7_6 : In std_logic;
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );
+end REG_IO;
+
+architecture SCHEMATIC of REG_IO is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+
+ component REG
+ Port ( CLOCK : In std_logic;
+ REG_IN : In std_logic_vector (7 downto 0);
+ RESET : In std_logic;
+ WRITE : In std_logic;
+ REG_OUT : Out std_logic_vector (7 downto 0) );
+ end component;
+
+begin
+
+ I14 : REG
+ Port Map ( CLOCK=>PCI_CLOCK,
+ REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,
+ WRITE=>WRITE_XX1_0,
+ REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );
+ I15 : REG
+ Port Map ( CLOCK=>PCI_CLOCK,
+ REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,
+ WRITE=>WRITE_XX7_6,
+ REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );
+ I16 : REG
+ Port Map ( CLOCK=>PCI_CLOCK,
+ REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,
+ WRITE=>WRITE_XX7_6,
+ REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );
+
+end SCHEMATIC;
--- /dev/null
+-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity STEUERUNG is
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ FRAME_REGn : In std_logic;
+ IDSEL_REG : In std_logic;
+ IO_SPACE : In std_logic;
+ MY_ADDR : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_FIFO : In std_logic;
+ CF_RD_COM : Out std_logic;
+ CF_WR_COM : Out std_logic;
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ IO_RD_COM : Out std_logic;
+ IO_WR_COM : Out std_logic;
+ LAR : Out std_logic;
+ OE_PCI_PAR : Out std_logic;
+ OE_PCI_PERR : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ PERR_CHECK : Out std_logic;
+ READ : Out std_logic;
+ SERR_CHECK : Out std_logic;
+ TRDYn : Out std_logic );
+end STEUERUNG;
+
+architecture SCHEMATIC of STEUERUNG is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal DEVSELn_DUMMY : std_logic;
+ signal IO_READ : std_logic;
+ signal IO_WRITE : std_logic;
+ signal CONF_READ : std_logic;
+ signal CONF_WRITE : std_logic;
+
+ component CONT_FSM
+ Port ( CONF_READ : In std_logic;
+ CONF_WRITE : In std_logic;
+ FIFO_READ : In std_logic;
+ IO_READ : In std_logic;
+ IO_WRITE : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ OE_PCI_PAR : Out std_logic;
+ OE_PCI_PERR : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ PERR_CHECK : Out std_logic;
+ READ : Out std_logic;
+ TRDYn : Out std_logic );
+ end component;
+
+ component COMM_FSM
+ Port ( CONF_READ : In std_logic;
+ CONF_WRITE : In std_logic;
+ DEVSELn : In std_logic;
+ IO_READ : In std_logic;
+ IO_WRITE : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ CF_RD_COM : Out std_logic;
+ CF_WR_COM : Out std_logic;
+ IO_RD_COM : Out std_logic;
+ IO_WR_COM : Out std_logic );
+ end component;
+
+ component COMM_DEC
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ FRAME_REGn : In std_logic;
+ IDSEL_REG : In std_logic;
+ IO_SPACE : In std_logic;
+ MY_ADDR : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ CONF_READ : Out std_logic;
+ CONF_WRITE : Out std_logic;
+ IO_READ : Out std_logic;
+ IO_WRITE : Out std_logic;
+ LAR : Out std_logic;
+ SERR_CHECK : Out std_logic );
+ end component;
+
+begin
+
+ DEVSELn <= DEVSELn_DUMMY;
+
+ I1 : CONT_FSM
+ Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
+ FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,
+ IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,
+ FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,
+ OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
+ PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
+ PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );
+ I2 : COMM_FSM
+ Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
+ DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,
+ IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,
+ CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,
+ IO_WR_COM=>IO_WR_COM );
+ I3 : COMM_DEC
+ Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+ IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,
+ PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
+ CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
+ IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,
+ SERR_CHECK=>SERR_CHECK );
+
+end SCHEMATIC;
--- /dev/null
+-----------------------------------------------------------------------------
+-- --
+-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
+-- --
+-- This source file may be used and distributed without restriction --
+-- provided that this copyright statement is not removed from the file --
+-- and that any derivative work contains this copyright notice. --
+-- --
+-- Primitive library for post synthesis simulation --
+-- These models are not intended for efficient synthesis --
+-- --
+-----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+entity prim_counter is
+ generic (w : integer := 8);
+ port (
+ q : buffer std_logic_vector(w - 1 downto 0);
+ cout : out std_logic;
+ d : in std_logic_vector(w - 1 downto 0);
+ cin : in std_logic;
+ clk : in std_logic;
+ rst : in std_logic;
+ load : in std_logic;
+ en : in std_logic;
+ updn : in std_logic
+ );
+end prim_counter;
+
+architecture beh of prim_counter is
+ signal nextq : std_logic_vector(w - 1 downto 0);
+begin
+ nxt: process (q, cin, updn)
+ variable i : integer;
+ variable nextc, c : std_logic;
+ begin
+ nextc := cin;
+ for i in 0 to w - 1 loop
+ c := nextc;
+ nextq(i) <= c xor (not updn) xor q(i);
+ nextc := (c and (not updn)) or
+ (c and q(i)) or
+ ((not updn) and q(i));
+ end loop;
+ cout <= nextc;
+ end process;
+
+ ff : process (clk, rst)
+ begin
+ if rst = '1' then
+ q <= (others => '0');
+ elsif rising_edge(clk) then
+ q <= nextq;
+ end if;
+ end process ff;
+end beh;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity prim_dff is
+ port (q : out std_logic;
+ d : in std_logic;
+ clk : in std_logic;
+ r : in std_logic := '0';
+ s : in std_logic := '0');
+end prim_dff;
+
+architecture beh of prim_dff is
+begin
+ ff : process (clk, r, s)
+ begin
+ if r = '1' then
+ q <= '0';
+ elsif s = '1' then
+ q <= '1';
+ elsif rising_edge(clk) then
+ q <= d;
+ end if;
+ end process ff;
+end beh;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity prim_latch is
+ port (q : out std_logic;
+ d : in std_logic;
+ clk : in std_logic;
+ r : in std_logic := '0';
+ s : in std_logic := '0');
+end prim_latch;
+
+architecture beh of prim_latch is
+begin
+ q <= '0' when r = '1' else
+ '1' when s = '1' else
+ d when clk = '1';
+end beh;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity prim_ramd is
+ generic (
+ data_width : integer := 4;
+ addr_width : integer := 5);
+ port (
+ dout : out std_logic_vector(data_width-1 downto 0);
+ aout : in std_logic_vector(addr_width-1 downto 0);
+ din : in std_logic_vector(data_width-1 downto 0);
+ ain : in std_logic_vector(addr_width-1 downto 0);
+ we : in std_logic;
+ clk : in std_logic);
+end prim_ramd;
+
+architecture beh of prim_ramd is
+
+ constant depth : integer := 2** addr_width;
+ type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
+ signal mem: mem_type;
+
+begin
+
+ dout <= mem(conv_integer(aout));
+
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ if (we = '1') then
+ mem(conv_integer(ain)) <= din;
+ end if;
+ end if;
+ end process;
+
+end beh;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+package components is
+ component prim_counter
+ generic (w : integer);
+ port (
+ q : buffer std_logic_vector(w - 1 downto 0);
+ cout : out std_logic;
+ d : in std_logic_vector(w - 1 downto 0);
+ cin : in std_logic;
+ clk : in std_logic;
+ rst : in std_logic;
+ load : in std_logic;
+ en : in std_logic;
+ updn : in std_logic
+ );
+ end component;
+ component prim_dff
+ port (q : out std_logic;
+ d : in std_logic;
+ clk : in std_logic;
+ r : in std_logic := '0';
+ s : in std_logic := '0');
+ end component;
+ component prim_latch
+ port (q : out std_logic;
+ d : in std_logic;
+ clk : in std_logic;
+ r : in std_logic := '0';
+ s : in std_logic := '0');
+ end component;
+
+ component prim_ramd is
+ generic (
+ data_width : integer := 4;
+ addr_width : integer := 5);
+ port (
+ dout : out std_logic_vector(data_width-1 downto 0);
+ aout : in std_logic_vector(addr_width-1 downto 0);
+ din : in std_logic_vector(data_width-1 downto 0);
+ ain : in std_logic_vector(addr_width-1 downto 0);
+ we : in std_logic;
+ clk : in std_logic);
+ end component;
+
+end components;
--- /dev/null
+-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity dhwk is
+ Port ( KONST_1 : In std_logic;
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_RSTn : In std_logic;
+ -- SERIAL_IN : In std_logic;
+ -- SPC_RDY_IN : In std_logic;
+ TAST_RESn : In std_logic;
+ TAST_SETn : In std_logic;
+ LED_2 : out std_logic;
+ LED_3 : out std_logic;
+ LED_4 : out std_logic;
+ LED_5 : out std_logic;
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ PCI_PAR : InOut std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_INTAn : Out std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ PCI_REQn : Out std_logic;
+ PCI_GNTn : In std_logic;
+ -- SERIAL_OUT : Out std_logic;
+ -- SPC_RDY_OUT : Out std_logic;
+ TB_IDSEL : Out std_logic;
+ TB_nDEVSEL : Out std_logic;
+ TB_nINTA : Out std_logic );
+end dhwk;
+
+architecture SCHEMATIC of dhwk is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal READ_XX7_6 : std_logic;
+ signal RESERVE : std_logic;
+ signal SR_ERROR : std_logic;
+ signal R_ERROR : std_logic;
+ signal S_ERROR : std_logic;
+ signal WRITE_XX3_2 : std_logic;
+ signal WRITE_XX5_4 : std_logic;
+ signal WRITE_XX7_6 : std_logic;
+ signal READ_XX1_0 : std_logic;
+ signal READ_XX3_2 : std_logic;
+ signal INTAn : std_logic;
+ signal TRDYn : std_logic;
+ signal READ_XX5_4 : std_logic;
+ signal DEVSELn : std_logic;
+ signal FIFO_RDn : std_logic;
+ signal WRITE_XX1_0 : std_logic;
+ signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
+ signal SYNC_FLAG : std_logic_vector (7 downto 0);
+ signal INT_REG : std_logic_vector (7 downto 0);
+ signal REVISON_ID : std_logic_vector (7 downto 0);
+ signal VENDOR_ID : std_logic_vector (15 downto 0);
+ signal READ_SEL : std_logic_vector (1 downto 0);
+ signal AD_REG : std_logic_vector (31 downto 0);
+ signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
+ signal R_EFn : std_logic;
+ signal R_FFn : std_logic;
+ signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
+ signal R_HFn : std_logic;
+ signal S_EFn : std_logic;
+ signal S_FFn : std_logic;
+ signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
+ signal S_HFn : std_logic;
+ signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
+ signal R_FIFO_READn : std_logic;
+ signal R_FIFO_RESETn : std_logic;
+ signal R_FIFO_RTn : std_logic;
+ signal R_FIFO_WRITEn : std_logic;
+ signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
+ signal S_FIFO_READn : std_logic;
+ signal S_FIFO_RESETn : std_logic;
+ signal S_FIFO_RTn : std_logic;
+ signal S_FIFO_WRITEn : std_logic;
+ signal SERIAL_IN : std_logic;
+ signal SPC_RDY_IN : std_logic;
+ signal SERIAL_OUT : std_logic;
+ signal SPC_RDY_OUT : std_logic;
+ signal watch_PCI_INTAn : std_logic;
+ signal watch_PCI_TRDYn : std_logic;
+ signal watch_PCI_STOPn : std_logic;
+ signal watch_PCI_SERRn : std_logic;
+ signal watch_PCI_PERRn : std_logic;
+ signal watch_PCI_REQn : std_logic;
+ signal control0 : std_logic_vector(35 downto 0);
+ signal data : std_logic_vector(95 downto 0);
+ signal trig0 : std_logic_vector(31 downto 0);
+
+ component MESS_1_TB
+ Port ( DEVSELn : In std_logic;
+ INTAn : In std_logic;
+ KONST_1 : In std_logic;
+ PCI_IDSEL : In std_logic;
+ REG_OUT_XX7 : In std_logic_vector (7 downto 0);
+ TB_DEVSELn : Out std_logic;
+ TB_INTAn : Out std_logic;
+ TB_PCI_IDSEL : Out std_logic );
+ end component;
+
+ component VEN_REV_ID
+ Port ( REV_ID : Out std_logic_vector (7 downto 0);
+ VEN_ID : Out std_logic_vector (15 downto 0) );
+ end component;
+
+ component INTERRUPT
+ Port ( INT_IN_0 : In std_logic;
+ INT_IN_1 : In std_logic;
+ INT_IN_2 : In std_logic;
+ INT_IN_3 : In std_logic;
+ INT_IN_4 : In std_logic;
+ INT_IN_5 : In std_logic;
+ INT_IN_6 : In std_logic;
+ INT_IN_7 : In std_logic;
+ INT_MASKE : In std_logic_vector (7 downto 0);
+ INT_RES : In std_logic_vector (7 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ READ_XX5_4 : In std_logic;
+ RESET : In std_logic;
+ TAST_RESn : In std_logic;
+ TAST_SETn : In std_logic;
+ TRDYn : In std_logic;
+ INT_REG : Out std_logic_vector (7 downto 0);
+ INTAn : Out std_logic;
+ PCI_INTAn : Out std_logic );
+ end component;
+
+ component FIFO_CONTROL
+ Port ( FIFO_RDn : In std_logic;
+ FLAG_IN_0 : In std_logic;
+ FLAG_IN_4 : In std_logic;
+ HOLD : In std_logic;
+ KONST_1 : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PSC_ENABLE : In std_logic;
+ R_EFn : In std_logic;
+ R_FFn : In std_logic;
+ R_HFn : In std_logic;
+ RESET : In std_logic;
+ S_EFn : In std_logic;
+ S_FFn : In std_logic;
+ S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
+ S_HFn : In std_logic;
+ SERIAL_IN : In std_logic;
+ SPC_ENABLE : In std_logic;
+ SPC_RDY_IN : In std_logic;
+ WRITE_XX1_0 : In std_logic;
+ R_ERROR : Out std_logic;
+ R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
+ R_FIFO_READn : Out std_logic;
+ R_FIFO_RESETn : Out std_logic;
+ R_FIFO_RETRANSMITn : Out std_logic;
+ R_FIFO_WRITEn : Out std_logic;
+ RESERVE : Out std_logic;
+ S_ERROR : Out std_logic;
+ S_FIFO_READn : Out std_logic;
+ S_FIFO_RESETn : Out std_logic;
+ S_FIFO_RETRANSMITn : Out std_logic;
+ S_FIFO_WRITEn : Out std_logic;
+ SERIAL_OUT : Out std_logic;
+ SPC_RDY_OUT : Out std_logic;
+ SR_ERROR : Out std_logic;
+ SYNC_FLAG : Out std_logic_vector (7 downto 0) );
+ end component;
+
+ component PCI_TOP
+ Port ( FLAG : In std_logic_vector (7 downto 0);
+ INT_REG : In std_logic_vector (7 downto 0);
+ PCI_CBEn : In std_logic_vector (3 downto 0);
+ PCI_CLOCK : In std_logic;
+ PCI_FRAMEn : In std_logic;
+ PCI_IDSEL : In std_logic;
+ PCI_IRDYn : In std_logic;
+ PCI_RSTn : In std_logic;
+ R_FIFO_Q : In std_logic_vector (7 downto 0);
+ REVISON_ID : In std_logic_vector (7 downto 0);
+ VENDOR_ID : In std_logic_vector (15 downto 0);
+ PCI_AD : InOut std_logic_vector (31 downto 0);
+ PCI_PAR : InOut std_logic;
+ AD_REG : Out std_logic_vector (31 downto 0);
+ DEVSELn : Out std_logic;
+ FIFO_RDn : Out std_logic;
+ PCI_DEVSELn : Out std_logic;
+ PCI_PERRn : Out std_logic;
+ PCI_SERRn : Out std_logic;
+ PCI_STOPn : Out std_logic;
+ PCI_TRDYn : Out std_logic;
+ READ_SEL : Out std_logic_vector (1 downto 0);
+ READ_XX1_0 : Out std_logic;
+ READ_XX3_2 : Out std_logic;
+ READ_XX5_4 : Out std_logic;
+ READ_XX7_6 : Out std_logic;
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
+ TRDYn : Out std_logic;
+ WRITE_XX1_0 : Out std_logic;
+ WRITE_XX3_2 : Out std_logic;
+ WRITE_XX5_4 : Out std_logic;
+ WRITE_XX7_6 : Out std_logic );
+ end component;
+
+ component dhwk_fifo
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ almost_empty: OUT std_logic;
+ almost_full: OUT std_logic;
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+ end component;
+
+ component icon
+ port
+ (
+ control0 : out std_logic_vector(35 downto 0)
+ );
+ end component;
+
+ component ila
+ port
+ (
+ control : in std_logic_vector(35 downto 0);
+ clk : in std_logic;
+ data : in std_logic_vector(95 downto 0);
+ trig0 : in std_logic_vector(31 downto 0)
+ );
+ end component;
+
+
+begin
+ watch_PCI_REQn <= '1';
+ SERIAL_IN <= SERIAL_OUT;
+ SPC_RDY_IN <= SPC_RDY_OUT;
+ LED_2 <= not PCI_RSTn;
+ LED_3 <= PCI_IDSEL;
+ LED_4 <= not PCI_FRAMEn;
+ LED_5 <= not watch_PCI_INTAn;
+ PCI_INTAn <= watch_PCI_INTAn;
+ trig0(31 downto 0) <= (
+ 0 => watch_PCI_INTAn,
+ 1 => R_FIFO_READn,
+ 2 => R_FIFO_WRITEn,
+ 3 => S_FIFO_READn,
+ 4 => S_FIFO_WRITEn,
+ 5 => PCI_RSTn,
+ 16 => PCI_AD(0),
+ 17 => PCI_AD(1),
+ 18 => PCI_AD(2),
+ 19 => PCI_AD(3),
+ 20 => PCI_AD(4),
+ 21 => PCI_AD(5),
+ 22 => PCI_AD(6),
+ 23 => PCI_AD(7),
+ 27 => PCI_FRAMEn,
+ 28 => PCI_CBEn(0),
+ 29 => PCI_CBEn(1),
+ 30 => PCI_CBEn(2),
+ 31 => PCI_CBEn(3),
+ others => '0');
+
+ data(0) <= watch_PCI_INTAn;
+ data(1) <= R_EFn;
+ data(2) <= R_HFn;
+ data(3) <= R_FFn;
+ data(4) <= R_FIFO_READn;
+ data(5) <= R_FIFO_RESETn;
+ data(6) <= R_FIFO_RTn;
+ data(7) <= R_FIFO_WRITEn;
+ data(8) <= S_EFn;
+ data(9) <= S_HFn;
+ data(10) <= S_FFn;
+ data(11) <= S_FIFO_READn;
+ data(12) <= S_FIFO_RESETn;
+ data(13) <= S_FIFO_RTn;
+ data(14) <= S_FIFO_WRITEn;
+ data(15) <= SERIAL_IN;
+ data(16) <= SPC_RDY_IN;
+ data(17) <= SERIAL_OUT;
+ data(18) <= SPC_RDY_OUT;
+ data(26 downto 19) <= S_FIFO_Q_OUT;
+ data(34 downto 27) <= R_FIFO_Q_OUT;
+ data(66 downto 35) <= PCI_AD(31 downto 0);
+ data(70 downto 67) <= PCI_CBEn(3 downto 0);
+ data(71) <= PCI_FRAMEn;
+ data(72) <= PCI_IDSEL;
+ PCI_TRDYn <= watch_PCI_TRDYn;
+ data(73) <= watch_PCI_TRDYn;
+ data(74) <= PCI_IRDYn;
+ PCI_STOPn <= watch_PCI_STOPn;
+ data(75) <= watch_PCI_STOPn;
+ PCI_SERRn <= watch_PCI_SERRn;
+ data(76) <= watch_PCI_SERRn;
+ PCI_PERRn <= watch_PCI_PERRn;
+ data(77) <= watch_PCI_PERRn;
+ PCI_REQn <= watch_PCI_REQn;
+ data(78) <= watch_PCI_REQn;
+ data(79) <= PCI_GNTn;
+
+ I19 : MESS_1_TB
+ Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
+ PCI_IDSEL=>PCI_IDSEL,
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
+ TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
+ TB_PCI_IDSEL=>TB_IDSEL );
+ I18 : VEN_REV_ID
+ Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+ VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
+ I16 : INTERRUPT
+ Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
+ INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
+ INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
+ INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
+ INT_RES(7 downto 0)=>AD_REG(7 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
+ READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
+ TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
+ TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
+ INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
+ I14 : FIFO_CONTROL
+ Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
+ FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
+ PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
+ R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
+ RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
+ S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+ S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
+ SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
+ WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
+ R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
+ R_FIFO_READn=>R_FIFO_READn,
+ R_FIFO_RESETn=>R_FIFO_RESETn,
+ R_FIFO_RETRANSMITn=>R_FIFO_RTn,
+ R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
+ S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
+ S_FIFO_RESETn=>S_FIFO_RESETn,
+ S_FIFO_RETRANSMITn=>S_FIFO_RTn,
+ S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
+ SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
+ SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
+ I1 : PCI_TOP
+ Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
+ INT_REG(7 downto 0)=>INT_REG(7 downto 0),
+ PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+ PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+ PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+ PCI_RSTn=>PCI_RSTn,
+ R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
+ REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+ VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+ PCI_PAR=>PCI_PAR,
+ AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+ DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
+ PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
+ PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
+ PCI_TRDYn=>watch_PCI_TRDYn,
+ READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
+ READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
+ READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
+ REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
+ TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
+ WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
+ WRITE_XX7_6=>WRITE_XX7_6 );
+
+ receive_fifo : dhwk_fifo
+ port map (
+ clk => PCI_CLOCK,
+ din => R_FIFO_D_IN,
+ rd_en => not R_FIFO_READn,
+ rst => not R_FIFO_RESETn,
+ wr_en => not R_FIFO_WRITEn,
+ dout => R_FIFO_Q_OUT,
+ empty => R_EFn,
+ full => R_FFn,
+ prog_full => R_HFn);
+
+ send_fifo : dhwk_fifo
+ port map (
+ clk => PCI_CLOCK,
+ din => S_FIFO_D_IN,
+ rd_en => not S_FIFO_READn,
+ rst => not S_FIFO_RESETn,
+ wr_en => not S_FIFO_WRITEn,
+ dout => S_FIFO_Q_OUT,
+ empty => S_EFn,
+ full => S_FFn,
+ prog_full => S_HFn);
+
+ i_icon : icon
+ port map
+ (
+ control0 => control0
+ );
+
+ i_ila : ila
+ port map
+ (
+ control => control0,
+ clk => PCI_CLOCK,
+ data => data,
+ trig0 => trig0
+ );
+end SCHEMATIC;
--- /dev/null
+-- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity USER_IO is
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ ADDR_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ FLAG : In std_logic_vector (7 downto 0);
+ INT_REG : In std_logic_vector (7 downto 0);
+ IO_WR_COM : In std_logic;
+ IRDY_REGn : In std_logic;
+ PCI_CLK : In std_logic;
+ R_FIFO_Q : In std_logic_vector (7 downto 0);
+ READ_SEL : In std_logic_vector (1 downto 0);
+ TRDYn : In std_logic;
+ READ_XX1_0 : Out std_logic;
+ READ_XX3_2 : Out std_logic;
+ READ_XX5_4 : Out std_logic;
+ READ_XX7_6 : Out std_logic;
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
+ USER_DATA_OUT : Out std_logic_vector (31 downto 0);
+ WRITE_XX1_0 : Out std_logic;
+ WRITE_XX3_2 : Out std_logic;
+ WRITE_XX5_4 : Out std_logic;
+ WRITE_XX7_6 : Out std_logic );
+end USER_IO;
+
+architecture SCHEMATIC of USER_IO is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal WRITE_XX1_0_DUMMY : std_logic;
+ signal WRITE_XX7_6_DUMMY : std_logic;
+ signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);
+ signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);
+ signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);
+
+ component IO_WR_SEL
+ Port ( ADDR_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ IO_WR_COM : In std_logic;
+ IRDY_REGn : In std_logic;
+ TRDYn : In std_logic;
+ WRITE_XX1_0 : Out std_logic;
+ WRITE_XX3_2 : Out std_logic;
+ WRITE_XX5_4 : Out std_logic;
+ WRITE_XX7_6 : Out std_logic );
+ end component;
+
+ component DATA_MUX
+ Port ( ADDR_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ MUX_IN_XX0 : In std_logic_vector (7 downto 0);
+ MUX_IN_XX1 : In std_logic_vector (7 downto 0);
+ MUX_IN_XX2 : In std_logic_vector (7 downto 0);
+ MUX_IN_XX3 : In std_logic_vector (7 downto 0);
+ MUX_IN_XX4 : In std_logic_vector (7 downto 0);
+ MUX_IN_XX5 : In std_logic_vector (7 downto 0);
+ MUX_IN_XX6 : In std_logic_vector (7 downto 0);
+ MUX_IN_XX7 : In std_logic_vector (7 downto 0);
+ READ_SEL : In std_logic_vector (1 downto 0);
+ MUX_OUT : Out std_logic_vector (31 downto 0);
+ READ_XX1_0 : Out std_logic;
+ READ_XX3_2 : Out std_logic;
+ READ_XX5_4 : Out std_logic;
+ READ_XX7_6 : Out std_logic );
+ end component;
+
+ component REG_IO
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ PCI_CLOCK : In std_logic;
+ RESET : In std_logic;
+ WRITE_XX1_0 : In std_logic;
+ WRITE_XX7_6 : In std_logic;
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );
+ end component;
+
+begin
+
+ REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
+ REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
+ REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
+ WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
+ WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
+
+ I4 : IO_WR_SEL
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+ TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
+ WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
+ WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
+ I2 : DATA_MUX
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
+ MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
+ MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
+ MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
+ MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
+ MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
+ MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
+ MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
+ READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
+ MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+ READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
+ READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
+ I1 : REG_IO
+ Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+ PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
+ WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
+ WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
+ REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );
+
+end SCHEMATIC;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VEN_REV_ID.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity VEN_REV_ID is
+ port
+ (
+ VEN_ID :out std_logic_vector(15 downto 0);
+ REV_ID :out std_logic_vector( 7 downto 0)
+ );
+end entity VEN_REV_ID;
+
+architecture VEN_REV_ID_DESIGN of VEN_REV_ID is
+
+begin
+
+ VEN_ID <= X"2222";
+ REV_ID <= X"01";
+
+end architecture VEN_REV_ID_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_2.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_2 is
+ port
+ (
+ IN_A :in std_logic_vector(1 downto 0);
+ IN_B :in std_logic_vector(1 downto 0);
+ GLEICH :out std_logic
+ );
+end entity VERG_2;
+
+architecture VERG_2_DESIGN of VERG_2 is
+
+begin
+
+ process (IN_A,IN_B)
+ begin
+
+ if IN_A = IN_B then
+ GLEICH <= '1';
+ else
+ GLEICH <= '0';
+ end if;
+
+end process;
+
+end architecture VERG_2_DESIGN;
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_4 is
+ port
+ (
+ IN_A :in std_logic_vector(3 downto 0);
+ IN_B :in std_logic_vector(3 downto 0);
+ GLEICH :out std_logic
+ );
+end entity VERG_4;
+
+architecture VERG_4_DESIGN of VERG_4 is
+
+begin
+
+ process (IN_A,IN_B)
+ begin
+
+ if IN_A = IN_B then
+ GLEICH <= '1';
+ else
+ GLEICH <= '0';
+ end if;
+ end process;
+
+end architecture VERG_4_DESIGN;
+
--- /dev/null
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_8.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_8 is
+ port
+ (
+ GLEICH :in std_logic_vector(7 downto 0);
+ GLEICH_OUT :out std_logic
+ );
+
+end entity VERG_8;
+
+architecture VERG_8_DESIGN of VERG_8 is
+
+begin
+
+ -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
+
+ -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0';
+ GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0';
+
+end architecture VERG_8_DESIGN;
--- /dev/null
+-- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity VERGLEICH is
+ Port ( IN_A : In std_logic_vector (31 downto 0);
+ IN_B : In std_logic_vector (31 downto 0);
+ GLEICH_OUT : Out std_logic );
+end VERGLEICH;
+
+architecture SCHEMATIC of VERGLEICH is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal GLEICH : std_logic_vector (7 downto 0);
+
+ component VERG_2
+ Port ( IN_A : In std_logic_vector (1 downto 0);
+ IN_B : In std_logic_vector (1 downto 0);
+ GLEICH : Out std_logic );
+ end component;
+
+ component VERG_8
+ Port ( GLEICH : In std_logic_vector (7 downto 0);
+ GLEICH_OUT : Out std_logic );
+ end component;
+
+ component VERG_4
+ Port ( IN_A : In std_logic_vector (3 downto 0);
+ IN_B : In std_logic_vector (3 downto 0);
+ GLEICH : Out std_logic );
+ end component;
+
+begin
+
+ I11 : VERG_2
+ Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),
+ IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );
+ I9 : VERG_8
+ Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),
+ GLEICH_OUT=>GLEICH_OUT );
+ I8 : VERG_4
+ Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),
+ IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );
+ I7 : VERG_4
+ Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),
+ IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );
+ I6 : VERG_4
+ Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),
+ IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );
+ I5 : VERG_4
+ Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),
+ IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );
+ I4 : VERG_4
+ Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),
+ IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );
+ I3 : VERG_4
+ Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),
+ IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );
+ I2 : VERG_4
+ Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),
+ IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );
+
+end SCHEMATIC;
+++ /dev/null
--- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity PCI_INTERFACE is
- Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_RSTn : In std_logic;
- READ_FIFO : In std_logic;
- REVISON_ID : In std_logic_vector (7 downto 0);
- USER_DATA_OUT : In std_logic_vector (31 downto 0);
- VENDOR_ID : In std_logic_vector (15 downto 0);
- PCI_AD : InOut std_logic_vector (31 downto 0);
- PCI_PAR : InOut std_logic;
- AD_REG : Out std_logic_vector (31 downto 0);
- ADDR_REG : Out std_logic_vector (31 downto 0);
- CBE_REGn : Out std_logic_vector (3 downto 0);
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- IO_WR_COM : Out std_logic;
- IRDY_REGn : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- READ_SEL : Out std_logic_vector (1 downto 0);
- TRDYn : Out std_logic );
-end PCI_INTERFACE;
-
-architecture SCHEMATIC of PCI_INTERFACE is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal IRDY_REGn_DUMMY : std_logic;
- signal PAR_REG : std_logic;
- signal PERR : std_logic;
- signal SERR : std_logic;
- signal CF_RD_COM : std_logic;
- signal CF_WR_COM : std_logic;
- signal LAR : std_logic;
- signal MY_ADDR : std_logic;
- signal SERR_CHECK : std_logic;
- signal IDSEL_REG : std_logic;
- signal FRAME_REGn : std_logic;
- signal PERR_CHECK : std_logic;
- signal OE_PCI_PAR : std_logic;
- signal OE_PCI_PERR : std_logic;
- signal TRDYn_DUMMY : std_logic;
- signal CONF_DATA_10H : std_logic_vector (31 downto 0);
- signal CONF_DATA_04H : std_logic_vector (31 downto 0);
- signal CONF_DATA : std_logic_vector (31 downto 0);
- signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
- signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
- signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
- signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);
-
- component STEUERUNG
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- FRAME_REGn : In std_logic;
- IDSEL_REG : In std_logic;
- IO_SPACE : In std_logic;
- MY_ADDR : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- READ_FIFO : In std_logic;
- CF_RD_COM : Out std_logic;
- CF_WR_COM : Out std_logic;
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- IO_RD_COM : Out std_logic;
- IO_WR_COM : Out std_logic;
- LAR : Out std_logic;
- OE_PCI_PAR : Out std_logic;
- OE_PCI_PERR : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- PERR_CHECK : Out std_logic;
- READ : Out std_logic;
- SERR_CHECK : Out std_logic;
- TRDYn : Out std_logic );
- end component;
-
- component PARITY
- Port ( OE_PCI_PAR : In std_logic;
- OE_PCI_PERR : In std_logic;
- PA_ER_RE : In std_logic;
- PAR_IN : In std_logic_vector (35 downto 0);
- PAR_REG : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- PERR_CHECK : In std_logic;
- SERR_CHECK : In std_logic;
- SERR_ENA : In std_logic;
- PCI_PAR : InOut std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PERR : Out std_logic;
- SERR : Out std_logic );
- end component;
-
- component VERGLEICH
- Port ( IN_A : In std_logic_vector (31 downto 0);
- IN_B : In std_logic_vector (31 downto 0);
- GLEICH_OUT : Out std_logic );
- end component;
-
- component IO_MUX_REG
- Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
- LOAD_ADDR_REG : In std_logic;
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_PAR : In std_logic;
- PCI_RSTn : In std_logic;
- READ_SEL : In std_logic_vector (1 downto 0);
- USER_DATA : In std_logic_vector (31 downto 0);
- PCI_AD : InOut std_logic_vector (31 downto 0);
- AD_REG : Out std_logic_vector (31 downto 0);
- ADDR_REG : Out std_logic_vector (31 downto 0);
- CBE_REGn : Out std_logic_vector (3 downto 0);
- FRAME_REGn : Out std_logic;
- IDSEL_REG : Out std_logic;
- IRDY_REGn : Out std_logic;
- PAR_REG : Out std_logic );
- end component;
-
- component CONFIG_SPACE_HEADER
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- ADDR_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- CF_RD_COM : In std_logic;
- CF_WR_COM : In std_logic;
- IRDY_REGn : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- PERR : In std_logic;
- REVISION_ID : In std_logic_vector (7 downto 0);
- SERR : In std_logic;
- TRDYn : In std_logic;
- VENDOR_ID : In std_logic_vector (15 downto 0);
- CONF_DATA : Out std_logic_vector (31 downto 0);
- CONF_DATA_04H : Out std_logic_vector (31 downto 0);
- CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
- end component;
-
-begin
-
- ADDR_REG <= ADDR_REG_DUMMY;
- AD_REG <= AD_REG_DUMMY;
- CBE_REGn <= CBE_REGn_DUMMY;
- READ_SEL <= READ_SEL_DUMMY;
- TRDYn <= TRDYn_DUMMY;
- IRDY_REGn <= IRDY_REGn_DUMMY;
-
- I7 : STEUERUNG
- Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
- FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
- IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,
- PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
- READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,
- CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,
- FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),
- IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,
- OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
- PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
- PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),
- SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );
- I5 : PARITY
- Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
- PA_ER_RE=>CONF_DATA_04H(6),
- PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),
- PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
- PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,
- SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
- PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
- PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
- I4 : VERGLEICH
- Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
- IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- GLEICH_OUT=>MY_ADDR );
- I2 : IO_MUX_REG
- Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
- LOAD_ADDR_REG=>LAR,
- PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
- PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
- PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
- PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
- READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
- USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),
- PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
- AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
- FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
- IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );
- I1 : CONFIG_SPACE_HEADER
- Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
- CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,
- IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,
- PCI_RSTn=>PCI_RSTn, PERR=>PERR,
- REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),
- SERR=>SERR, TRDYn=>TRDYn_DUMMY,
- VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
- CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
- CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
- CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
-
-end SCHEMATIC;
+++ /dev/null
--- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity PCI_TOP is
- Port ( FLAG : In std_logic_vector (7 downto 0);
- INT_REG : In std_logic_vector (7 downto 0);
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_RSTn : In std_logic;
- R_FIFO_Q : In std_logic_vector (7 downto 0);
- REVISON_ID : In std_logic_vector (7 downto 0);
- VENDOR_ID : In std_logic_vector (15 downto 0);
- PCI_AD : InOut std_logic_vector (31 downto 0);
- PCI_PAR : InOut std_logic;
- AD_REG : Out std_logic_vector (31 downto 0);
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- READ_SEL : Out std_logic_vector (1 downto 0);
- READ_XX1_0 : Out std_logic;
- READ_XX3_2 : Out std_logic;
- READ_XX5_4 : Out std_logic;
- READ_XX7_6 : Out std_logic;
- REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
- TRDYn : Out std_logic;
- WRITE_XX1_0 : Out std_logic;
- WRITE_XX3_2 : Out std_logic;
- WRITE_XX5_4 : Out std_logic;
- WRITE_XX7_6 : Out std_logic );
-end PCI_TOP;
-
-architecture SCHEMATIC of PCI_TOP is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal IRDY_REGn : std_logic;
- signal IO_WR_COM : std_logic;
- signal TRDYn_DUMMY : std_logic;
- signal READ_XX3_2_DUMMY : std_logic;
- signal USER_DATA_OUT : std_logic_vector (31 downto 0);
- signal CBE_REGn : std_logic_vector (3 downto 0);
- signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
- signal ADDR_REG : std_logic_vector (31 downto 0);
- signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
-
- component USER_IO
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- ADDR_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- FLAG : In std_logic_vector (7 downto 0);
- INT_REG : In std_logic_vector (7 downto 0);
- IO_WR_COM : In std_logic;
- IRDY_REGn : In std_logic;
- PCI_CLK : In std_logic;
- R_FIFO_Q : In std_logic_vector (7 downto 0);
- READ_SEL : In std_logic_vector (1 downto 0);
- TRDYn : In std_logic;
- READ_XX1_0 : Out std_logic;
- READ_XX3_2 : Out std_logic;
- READ_XX5_4 : Out std_logic;
- READ_XX7_6 : Out std_logic;
- REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
- USER_DATA_OUT : Out std_logic_vector (31 downto 0);
- WRITE_XX1_0 : Out std_logic;
- WRITE_XX3_2 : Out std_logic;
- WRITE_XX5_4 : Out std_logic;
- WRITE_XX7_6 : Out std_logic );
- end component;
-
- component PCI_INTERFACE
- Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_RSTn : In std_logic;
- READ_FIFO : In std_logic;
- REVISON_ID : In std_logic_vector (7 downto 0);
- USER_DATA_OUT : In std_logic_vector (31 downto 0);
- VENDOR_ID : In std_logic_vector (15 downto 0);
- PCI_AD : InOut std_logic_vector (31 downto 0);
- PCI_PAR : InOut std_logic;
- AD_REG : Out std_logic_vector (31 downto 0);
- ADDR_REG : Out std_logic_vector (31 downto 0);
- CBE_REGn : Out std_logic_vector (3 downto 0);
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- IO_WR_COM : Out std_logic;
- IRDY_REGn : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- READ_SEL : Out std_logic_vector (1 downto 0);
- TRDYn : Out std_logic );
- end component;
-
-begin
-
- READ_SEL <= READ_SEL_DUMMY;
- AD_REG <= AD_REG_DUMMY;
- READ_XX3_2 <= READ_XX3_2_DUMMY;
- TRDYn <= TRDYn_DUMMY;
-
- I19 : USER_IO
- Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- FLAG(7 downto 0)=>FLAG(7 downto 0),
- INT_REG(7 downto 0)=>INT_REG(7 downto 0),
- IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
- PCI_CLK=>PCI_CLOCK,
- R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
- READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
- TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
- READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
- READ_XX7_6=>READ_XX7_6,
- REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
- REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
- REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
- USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
- WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
- WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
- I10 : PCI_INTERFACE
- Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
- PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
- PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
- PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
- REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
- USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
- VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
- PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
- PCI_PAR=>PCI_PAR,
- AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
- ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
- IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
- PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
- PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
- PCI_TRDYn=>PCI_TRDYn,
- READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
- TRDYn=>TRDYn_DUMMY );
-
-end SCHEMATIC;
+++ /dev/null
--- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity REG_IO is
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- PCI_CLOCK : In std_logic;
- RESET : In std_logic;
- WRITE_XX1_0 : In std_logic;
- WRITE_XX7_6 : In std_logic;
- REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );
-end REG_IO;
-
-architecture SCHEMATIC of REG_IO is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
-
- component REG
- Port ( CLOCK : In std_logic;
- REG_IN : In std_logic_vector (7 downto 0);
- RESET : In std_logic;
- WRITE : In std_logic;
- REG_OUT : Out std_logic_vector (7 downto 0) );
- end component;
-
-begin
-
- I14 : REG
- Port Map ( CLOCK=>PCI_CLOCK,
- REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,
- WRITE=>WRITE_XX1_0,
- REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );
- I15 : REG
- Port Map ( CLOCK=>PCI_CLOCK,
- REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,
- WRITE=>WRITE_XX7_6,
- REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );
- I16 : REG
- Port Map ( CLOCK=>PCI_CLOCK,
- REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,
- WRITE=>WRITE_XX7_6,
- REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );
-
-end SCHEMATIC;
--- /dev/null
+-- $Id: ser_par_con.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity SER_PAR_CON is
+ port
+ (
+ PCI_CLOCK :in std_logic;
+ RESET :in std_logic;
+ SPC_ENABLE :in std_logic; -- Driver Enable Sender/Receiver
+ SYNC_R_FIFO_FFn :in std_logic; -- FIFO Full Flag (low active)
+ SERIAL_IN :in std_logic; -- Serial Input
+ R_FIFO_WRITEn :out std_logic; -- FIFO Write (low active)
+ SPC_RDY_OUT :out std_logic; -- Ready to Receive Data
+ PAR_OUT :out std_logic_vector(7 downto 0)
+ );
+end entity SER_PAR_CON;
+
+
+architecture SER_PAR_CON_DESIGN of SER_PAR_CON is
+
+-- constant STATE_RECV :std_logic_vector(3 downto 0) := "0001";
+ constant STATE_RECV_START_BIT :std_logic_vector(3 downto 0) := "0010";
+ constant STATE_RECV_BIT_0 :std_logic_vector(3 downto 0) := "0011";
+ constant STATE_RECV_BIT_1 :std_logic_vector(3 downto 0) := "0100";
+ constant STATE_RECV_BIT_2 :std_logic_vector(3 downto 0) := "0101";
+ constant STATE_RECV_BIT_3 :std_logic_vector(3 downto 0) := "0110";
+ constant STATE_RECV_BIT_4 :std_logic_vector(3 downto 0) := "0111";
+ constant STATE_RECV_BIT_5 :std_logic_vector(3 downto 0) := "1000";
+ constant STATE_RECV_BIT_6 :std_logic_vector(3 downto 0) := "1001";
+ constant STATE_RECV_BIT_7 :std_logic_vector(3 downto 0) := "1010";
+ constant STATE_RECV_FIFOFULL :std_logic_vector(3 downto 0) := "1011";
+
+ signal COUNT :std_logic_vector (3 downto 0);
+ signal STATE :std_logic_vector (3 downto 0);
+ signal STARTBIT :std_logic_vector (3 downto 0);
+
+
+ attribute syn_state_machine:boolean;
+ attribute syn_state_machine of STATE: signal is false;
+ attribute syn_state_machine of COUNT: signal is false;
+
+begin
+
+ process(PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if ("0000" < COUNT) then
+ COUNT <= COUNT - 1;
+ end if;
+
+ -- war nicht das Problem des Datenverlusts
+ -- if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
+ -- R_FIFO_WRITEn <= '1';
+ --- end if;
+
+ if (RESET = '1') then
+ STATE <= STATE_RECV_START_BIT;
+ COUNT <= "0000";
+ R_FIFO_WRITEn <= '1';
+
+ elsif (SPC_ENABLE = '1') then
+
+ if (STATE = STATE_RECV_START_BIT) then
+ R_FIFO_WRITEn <= '1';
+ if (STARTBIT = "0011") then
+ COUNT <= "0011";
+ STATE <= STATE_RECV_BIT_0;
+ end if;
+
+ elsif (STATE = STATE_RECV_FIFOFULL) then
+ if (SYNC_R_FIFO_FFn = '1') then
+ R_FIFO_WRITEn <= '0';
+ STATE <= STATE_RECV_START_BIT;
+ end if;
+
+ elsif (COUNT = "0000") then
+ COUNT <= "0011";
+ case STATE is
+
+ when STATE_RECV_BIT_0 =>
+ PAR_OUT(0) <= STARTBIT(0);
+ STATE <= STATE_RECV_BIT_1;
+
+ when STATE_RECV_BIT_1 =>
+ PAR_OUT(1) <= STARTBIT(0);
+ STATE <= STATE_RECV_BIT_2;
+
+ when STATE_RECV_BIT_2 =>
+ PAR_OUT(2) <= STARTBIT(0);
+ STATE <= STATE_RECV_BIT_3;
+
+ when STATE_RECV_BIT_3 =>
+ PAR_OUT(3) <= STARTBIT(0);
+ STATE <= STATE_RECV_BIT_4;
+
+ when STATE_RECV_BIT_4 =>
+ PAR_OUT(4) <= STARTBIT(0);
+ STATE <= STATE_RECV_BIT_5;
+
+ when STATE_RECV_BIT_5 =>
+ PAR_OUT(5) <= STARTBIT(0);
+ STATE <= STATE_RECV_BIT_6;
+
+ when STATE_RECV_BIT_6 =>
+ PAR_OUT(6) <= STARTBIT(0);
+ STATE <= STATE_RECV_BIT_7;
+
+ when STATE_RECV_BIT_7 =>
+ PAR_OUT(7) <= STARTBIT(0);
+
+ if (SYNC_R_FIFO_FFn = '1') then
+ STATE <= STATE_RECV_START_BIT;
+ R_FIFO_WRITEn <= '0';
+ else
+ STATE <= STATE_RECV_FIFOFULL;
+ end if;
+
+ when others =>
+ STATE <= STATE_RECV_START_BIT;
+
+ end case;
+ end if; -- COUNT
+ end if; -- RESET ... / SPC_ENABLE ...
+ end if; -- PCI_CLOCK ...
+ end process;
+
+ process(PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
+ end if;
+ end process;
+
+
+ process(PCI_CLOCK)
+ begin
+ if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ if (RESET = '1') then
+ STARTBIT <= "0000";
+ else
+ STARTBIT(0) <= SERIAL_IN;
+ STARTBIT(1) <= STARTBIT(0);
+ STARTBIT(2) <= STARTBIT(1);
+ STARTBIT(3) <= STARTBIT(2);
+ end if;
+ end if;
+ end process;
+
+end architecture SER_PAR_CON_DESIGN;
+++ /dev/null
--- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-entity STEUERUNG is
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- FRAME_REGn : In std_logic;
- IDSEL_REG : In std_logic;
- IO_SPACE : In std_logic;
- MY_ADDR : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- READ_FIFO : In std_logic;
- CF_RD_COM : Out std_logic;
- CF_WR_COM : Out std_logic;
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- IO_RD_COM : Out std_logic;
- IO_WR_COM : Out std_logic;
- LAR : Out std_logic;
- OE_PCI_PAR : Out std_logic;
- OE_PCI_PERR : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- PERR_CHECK : Out std_logic;
- READ : Out std_logic;
- SERR_CHECK : Out std_logic;
- TRDYn : Out std_logic );
-end STEUERUNG;
-
-architecture SCHEMATIC of STEUERUNG is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal DEVSELn_DUMMY : std_logic;
- signal IO_READ : std_logic;
- signal IO_WRITE : std_logic;
- signal CONF_READ : std_logic;
- signal CONF_WRITE : std_logic;
-
- component CONT_FSM
- Port ( CONF_READ : In std_logic;
- CONF_WRITE : In std_logic;
- FIFO_READ : In std_logic;
- IO_READ : In std_logic;
- IO_WRITE : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- OE_PCI_PAR : Out std_logic;
- OE_PCI_PERR : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- PERR_CHECK : Out std_logic;
- READ : Out std_logic;
- TRDYn : Out std_logic );
- end component;
-
- component COMM_FSM
- Port ( CONF_READ : In std_logic;
- CONF_WRITE : In std_logic;
- DEVSELn : In std_logic;
- IO_READ : In std_logic;
- IO_WRITE : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- CF_RD_COM : Out std_logic;
- CF_WR_COM : Out std_logic;
- IO_RD_COM : Out std_logic;
- IO_WR_COM : Out std_logic );
- end component;
-
- component COMM_DEC
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- FRAME_REGn : In std_logic;
- IDSEL_REG : In std_logic;
- IO_SPACE : In std_logic;
- MY_ADDR : In std_logic;
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- CONF_READ : Out std_logic;
- CONF_WRITE : Out std_logic;
- IO_READ : Out std_logic;
- IO_WRITE : Out std_logic;
- LAR : Out std_logic;
- SERR_CHECK : Out std_logic );
- end component;
-
-begin
-
- DEVSELn <= DEVSELn_DUMMY;
-
- I1 : CONT_FSM
- Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
- FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,
- IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
- PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,
- FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,
- OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
- PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
- PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );
- I2 : COMM_FSM
- Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
- DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,
- IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
- PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,
- CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,
- IO_WR_COM=>IO_WR_COM );
- I3 : COMM_DEC
- Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
- IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,
- PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
- CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
- IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,
- SERR_CHECK=>SERR_CHECK );
-
-end SCHEMATIC;
+++ /dev/null
------------------------------------------------------------------------------
--- --
--- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
--- --
--- This source file may be used and distributed without restriction --
--- provided that this copyright statement is not removed from the file --
--- and that any derivative work contains this copyright notice. --
--- --
--- Primitive library for post synthesis simulation --
--- These models are not intended for efficient synthesis --
--- --
------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-entity prim_counter is
- generic (w : integer := 8);
- port (
- q : buffer std_logic_vector(w - 1 downto 0);
- cout : out std_logic;
- d : in std_logic_vector(w - 1 downto 0);
- cin : in std_logic;
- clk : in std_logic;
- rst : in std_logic;
- load : in std_logic;
- en : in std_logic;
- updn : in std_logic
- );
-end prim_counter;
-
-architecture beh of prim_counter is
- signal nextq : std_logic_vector(w - 1 downto 0);
-begin
- nxt: process (q, cin, updn)
- variable i : integer;
- variable nextc, c : std_logic;
- begin
- nextc := cin;
- for i in 0 to w - 1 loop
- c := nextc;
- nextq(i) <= c xor (not updn) xor q(i);
- nextc := (c and (not updn)) or
- (c and q(i)) or
- ((not updn) and q(i));
- end loop;
- cout <= nextc;
- end process;
-
- ff : process (clk, rst)
- begin
- if rst = '1' then
- q <= (others => '0');
- elsif rising_edge(clk) then
- q <= nextq;
- end if;
- end process ff;
-end beh;
-
-library ieee;
-use ieee.std_logic_1164.all;
-entity prim_dff is
- port (q : out std_logic;
- d : in std_logic;
- clk : in std_logic;
- r : in std_logic := '0';
- s : in std_logic := '0');
-end prim_dff;
-
-architecture beh of prim_dff is
-begin
- ff : process (clk, r, s)
- begin
- if r = '1' then
- q <= '0';
- elsif s = '1' then
- q <= '1';
- elsif rising_edge(clk) then
- q <= d;
- end if;
- end process ff;
-end beh;
-
-library ieee;
-use ieee.std_logic_1164.all;
-entity prim_latch is
- port (q : out std_logic;
- d : in std_logic;
- clk : in std_logic;
- r : in std_logic := '0';
- s : in std_logic := '0');
-end prim_latch;
-
-architecture beh of prim_latch is
-begin
- q <= '0' when r = '1' else
- '1' when s = '1' else
- d when clk = '1';
-end beh;
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity prim_ramd is
- generic (
- data_width : integer := 4;
- addr_width : integer := 5);
- port (
- dout : out std_logic_vector(data_width-1 downto 0);
- aout : in std_logic_vector(addr_width-1 downto 0);
- din : in std_logic_vector(data_width-1 downto 0);
- ain : in std_logic_vector(addr_width-1 downto 0);
- we : in std_logic;
- clk : in std_logic);
-end prim_ramd;
-
-architecture beh of prim_ramd is
-
- constant depth : integer := 2** addr_width;
- type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
- signal mem: mem_type;
-
-begin
-
- dout <= mem(conv_integer(aout));
-
- process (clk)
- begin
- if rising_edge(clk) then
- if (we = '1') then
- mem(conv_integer(ain)) <= din;
- end if;
- end if;
- end process;
-
-end beh;
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-package components is
- component prim_counter
- generic (w : integer);
- port (
- q : buffer std_logic_vector(w - 1 downto 0);
- cout : out std_logic;
- d : in std_logic_vector(w - 1 downto 0);
- cin : in std_logic;
- clk : in std_logic;
- rst : in std_logic;
- load : in std_logic;
- en : in std_logic;
- updn : in std_logic
- );
- end component;
- component prim_dff
- port (q : out std_logic;
- d : in std_logic;
- clk : in std_logic;
- r : in std_logic := '0';
- s : in std_logic := '0');
- end component;
- component prim_latch
- port (q : out std_logic;
- d : in std_logic;
- clk : in std_logic;
- r : in std_logic := '0';
- s : in std_logic := '0');
- end component;
-
- component prim_ramd is
- generic (
- data_width : integer := 4;
- addr_width : integer := 5);
- port (
- dout : out std_logic_vector(data_width-1 downto 0);
- aout : in std_logic_vector(addr_width-1 downto 0);
- din : in std_logic_vector(data_width-1 downto 0);
- ain : in std_logic_vector(addr_width-1 downto 0);
- we : in std_logic;
- clk : in std_logic);
- end component;
-
-end components;
+++ /dev/null
--- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity dhwk is
- Port ( KONST_1 : In std_logic;
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_RSTn : In std_logic;
- -- SERIAL_IN : In std_logic;
- -- SPC_RDY_IN : In std_logic;
- TAST_RESn : In std_logic;
- TAST_SETn : In std_logic;
- LED_2 : out std_logic;
- LED_3 : out std_logic;
- LED_4 : out std_logic;
- LED_5 : out std_logic;
- PCI_AD : InOut std_logic_vector (31 downto 0);
- PCI_PAR : InOut std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_INTAn : Out std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- PCI_REQn : Out std_logic;
- PCI_GNTn : In std_logic;
- -- SERIAL_OUT : Out std_logic;
- -- SPC_RDY_OUT : Out std_logic;
- TB_IDSEL : Out std_logic;
- TB_nDEVSEL : Out std_logic;
- TB_nINTA : Out std_logic );
-end dhwk;
-
-architecture SCHEMATIC of dhwk is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal READ_XX7_6 : std_logic;
- signal RESERVE : std_logic;
- signal SR_ERROR : std_logic;
- signal R_ERROR : std_logic;
- signal S_ERROR : std_logic;
- signal WRITE_XX3_2 : std_logic;
- signal WRITE_XX5_4 : std_logic;
- signal WRITE_XX7_6 : std_logic;
- signal READ_XX1_0 : std_logic;
- signal READ_XX3_2 : std_logic;
- signal INTAn : std_logic;
- signal TRDYn : std_logic;
- signal READ_XX5_4 : std_logic;
- signal DEVSELn : std_logic;
- signal FIFO_RDn : std_logic;
- signal WRITE_XX1_0 : std_logic;
- signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
- signal SYNC_FLAG : std_logic_vector (7 downto 0);
- signal INT_REG : std_logic_vector (7 downto 0);
- signal REVISON_ID : std_logic_vector (7 downto 0);
- signal VENDOR_ID : std_logic_vector (15 downto 0);
- signal READ_SEL : std_logic_vector (1 downto 0);
- signal AD_REG : std_logic_vector (31 downto 0);
- signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
- signal R_EFn : std_logic;
- signal R_FFn : std_logic;
- signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
- signal R_HFn : std_logic;
- signal S_EFn : std_logic;
- signal S_FFn : std_logic;
- signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
- signal S_HFn : std_logic;
- signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
- signal R_FIFO_READn : std_logic;
- signal R_FIFO_RESETn : std_logic;
- signal R_FIFO_RTn : std_logic;
- signal R_FIFO_WRITEn : std_logic;
- signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
- signal S_FIFO_READn : std_logic;
- signal S_FIFO_RESETn : std_logic;
- signal S_FIFO_RTn : std_logic;
- signal S_FIFO_WRITEn : std_logic;
- signal SERIAL_IN : std_logic;
- signal SPC_RDY_IN : std_logic;
- signal SERIAL_OUT : std_logic;
- signal SPC_RDY_OUT : std_logic;
- signal watch_PCI_INTAn : std_logic;
- signal watch_PCI_TRDYn : std_logic;
- signal watch_PCI_STOPn : std_logic;
- signal watch_PCI_SERRn : std_logic;
- signal watch_PCI_PERRn : std_logic;
- signal watch_PCI_REQn : std_logic;
- signal control0 : std_logic_vector(35 downto 0);
- signal data : std_logic_vector(95 downto 0);
- signal trig0 : std_logic_vector(31 downto 0);
-
- component MESS_1_TB
- Port ( DEVSELn : In std_logic;
- INTAn : In std_logic;
- KONST_1 : In std_logic;
- PCI_IDSEL : In std_logic;
- REG_OUT_XX7 : In std_logic_vector (7 downto 0);
- TB_DEVSELn : Out std_logic;
- TB_INTAn : Out std_logic;
- TB_PCI_IDSEL : Out std_logic );
- end component;
-
- component VEN_REV_ID
- Port ( REV_ID : Out std_logic_vector (7 downto 0);
- VEN_ID : Out std_logic_vector (15 downto 0) );
- end component;
-
- component INTERRUPT
- Port ( INT_IN_0 : In std_logic;
- INT_IN_1 : In std_logic;
- INT_IN_2 : In std_logic;
- INT_IN_3 : In std_logic;
- INT_IN_4 : In std_logic;
- INT_IN_5 : In std_logic;
- INT_IN_6 : In std_logic;
- INT_IN_7 : In std_logic;
- INT_MASKE : In std_logic_vector (7 downto 0);
- INT_RES : In std_logic_vector (7 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_RSTn : In std_logic;
- READ_XX5_4 : In std_logic;
- RESET : In std_logic;
- TAST_RESn : In std_logic;
- TAST_SETn : In std_logic;
- TRDYn : In std_logic;
- INT_REG : Out std_logic_vector (7 downto 0);
- INTAn : Out std_logic;
- PCI_INTAn : Out std_logic );
- end component;
-
- component FIFO_CONTROL
- Port ( FIFO_RDn : In std_logic;
- FLAG_IN_0 : In std_logic;
- FLAG_IN_4 : In std_logic;
- HOLD : In std_logic;
- KONST_1 : In std_logic;
- PCI_CLOCK : In std_logic;
- PSC_ENABLE : In std_logic;
- R_EFn : In std_logic;
- R_FFn : In std_logic;
- R_HFn : In std_logic;
- RESET : In std_logic;
- S_EFn : In std_logic;
- S_FFn : In std_logic;
- S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
- S_HFn : In std_logic;
- SERIAL_IN : In std_logic;
- SPC_ENABLE : In std_logic;
- SPC_RDY_IN : In std_logic;
- WRITE_XX1_0 : In std_logic;
- R_ERROR : Out std_logic;
- R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
- R_FIFO_READn : Out std_logic;
- R_FIFO_RESETn : Out std_logic;
- R_FIFO_RETRANSMITn : Out std_logic;
- R_FIFO_WRITEn : Out std_logic;
- RESERVE : Out std_logic;
- S_ERROR : Out std_logic;
- S_FIFO_READn : Out std_logic;
- S_FIFO_RESETn : Out std_logic;
- S_FIFO_RETRANSMITn : Out std_logic;
- S_FIFO_WRITEn : Out std_logic;
- SERIAL_OUT : Out std_logic;
- SPC_RDY_OUT : Out std_logic;
- SR_ERROR : Out std_logic;
- SYNC_FLAG : Out std_logic_vector (7 downto 0) );
- end component;
-
- component PCI_TOP
- Port ( FLAG : In std_logic_vector (7 downto 0);
- INT_REG : In std_logic_vector (7 downto 0);
- PCI_CBEn : In std_logic_vector (3 downto 0);
- PCI_CLOCK : In std_logic;
- PCI_FRAMEn : In std_logic;
- PCI_IDSEL : In std_logic;
- PCI_IRDYn : In std_logic;
- PCI_RSTn : In std_logic;
- R_FIFO_Q : In std_logic_vector (7 downto 0);
- REVISON_ID : In std_logic_vector (7 downto 0);
- VENDOR_ID : In std_logic_vector (15 downto 0);
- PCI_AD : InOut std_logic_vector (31 downto 0);
- PCI_PAR : InOut std_logic;
- AD_REG : Out std_logic_vector (31 downto 0);
- DEVSELn : Out std_logic;
- FIFO_RDn : Out std_logic;
- PCI_DEVSELn : Out std_logic;
- PCI_PERRn : Out std_logic;
- PCI_SERRn : Out std_logic;
- PCI_STOPn : Out std_logic;
- PCI_TRDYn : Out std_logic;
- READ_SEL : Out std_logic_vector (1 downto 0);
- READ_XX1_0 : Out std_logic;
- READ_XX3_2 : Out std_logic;
- READ_XX5_4 : Out std_logic;
- READ_XX7_6 : Out std_logic;
- REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
- TRDYn : Out std_logic;
- WRITE_XX1_0 : Out std_logic;
- WRITE_XX3_2 : Out std_logic;
- WRITE_XX5_4 : Out std_logic;
- WRITE_XX7_6 : Out std_logic );
- end component;
-
- component dhwk_fifo
- port (
- clk: IN std_logic;
- din: IN std_logic_VECTOR(7 downto 0);
- rd_en: IN std_logic;
- rst: IN std_logic;
- wr_en: IN std_logic;
- almost_empty: OUT std_logic;
- almost_full: OUT std_logic;
- dout: OUT std_logic_VECTOR(7 downto 0);
- empty: OUT std_logic;
- full: OUT std_logic;
- prog_full: OUT std_logic);
- end component;
-
- component icon
- port
- (
- control0 : out std_logic_vector(35 downto 0)
- );
- end component;
-
- component ila
- port
- (
- control : in std_logic_vector(35 downto 0);
- clk : in std_logic;
- data : in std_logic_vector(95 downto 0);
- trig0 : in std_logic_vector(31 downto 0)
- );
- end component;
-
-
-begin
- watch_PCI_REQn <= '1';
- SERIAL_IN <= SERIAL_OUT;
- SPC_RDY_IN <= SPC_RDY_OUT;
- LED_2 <= not PCI_RSTn;
- LED_3 <= PCI_IDSEL;
- LED_4 <= not PCI_FRAMEn;
- LED_5 <= not watch_PCI_INTAn;
- PCI_INTAn <= watch_PCI_INTAn;
- trig0(31 downto 0) <= (
- 0 => watch_PCI_INTAn,
- 1 => R_FIFO_READn,
- 2 => R_FIFO_WRITEn,
- 3 => S_FIFO_READn,
- 4 => S_FIFO_WRITEn,
- 5 => PCI_RSTn,
- 16 => PCI_AD(0),
- 17 => PCI_AD(1),
- 18 => PCI_AD(2),
- 19 => PCI_AD(3),
- 20 => PCI_AD(4),
- 21 => PCI_AD(5),
- 22 => PCI_AD(6),
- 23 => PCI_AD(7),
- 27 => PCI_FRAMEn,
- 28 => PCI_CBEn(0),
- 29 => PCI_CBEn(1),
- 30 => PCI_CBEn(2),
- 31 => PCI_CBEn(3),
- others => '0');
-
- data(0) <= watch_PCI_INTAn;
- data(1) <= R_EFn;
- data(2) <= R_HFn;
- data(3) <= R_FFn;
- data(4) <= R_FIFO_READn;
- data(5) <= R_FIFO_RESETn;
- data(6) <= R_FIFO_RTn;
- data(7) <= R_FIFO_WRITEn;
- data(8) <= S_EFn;
- data(9) <= S_HFn;
- data(10) <= S_FFn;
- data(11) <= S_FIFO_READn;
- data(12) <= S_FIFO_RESETn;
- data(13) <= S_FIFO_RTn;
- data(14) <= S_FIFO_WRITEn;
- data(15) <= SERIAL_IN;
- data(16) <= SPC_RDY_IN;
- data(17) <= SERIAL_OUT;
- data(18) <= SPC_RDY_OUT;
- data(26 downto 19) <= S_FIFO_Q_OUT;
- data(34 downto 27) <= R_FIFO_Q_OUT;
- data(66 downto 35) <= PCI_AD(31 downto 0);
- data(70 downto 67) <= PCI_CBEn(3 downto 0);
- data(71) <= PCI_FRAMEn;
- data(72) <= PCI_IDSEL;
- PCI_TRDYn <= watch_PCI_TRDYn;
- data(73) <= watch_PCI_TRDYn;
- data(74) <= PCI_IRDYn;
- PCI_STOPn <= watch_PCI_STOPn;
- data(75) <= watch_PCI_STOPn;
- PCI_SERRn <= watch_PCI_SERRn;
- data(76) <= watch_PCI_SERRn;
- PCI_PERRn <= watch_PCI_PERRn;
- data(77) <= watch_PCI_PERRn;
- PCI_REQn <= watch_PCI_REQn;
- data(78) <= watch_PCI_REQn;
- data(79) <= PCI_GNTn;
-
- I19 : MESS_1_TB
- Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
- PCI_IDSEL=>PCI_IDSEL,
- REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
- TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
- TB_PCI_IDSEL=>TB_IDSEL );
- I18 : VEN_REV_ID
- Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
- VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
- I16 : INTERRUPT
- Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
- INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
- INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
- INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
- INT_RES(7 downto 0)=>AD_REG(7 downto 0),
- PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
- READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
- TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
- TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
- INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
- I14 : FIFO_CONTROL
- Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
- FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
- PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
- R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
- RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
- S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
- S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
- SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
- WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
- R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
- R_FIFO_READn=>R_FIFO_READn,
- R_FIFO_RESETn=>R_FIFO_RESETn,
- R_FIFO_RETRANSMITn=>R_FIFO_RTn,
- R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
- S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
- S_FIFO_RESETn=>S_FIFO_RESETn,
- S_FIFO_RETRANSMITn=>S_FIFO_RTn,
- S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
- SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
- SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
- I1 : PCI_TOP
- Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
- INT_REG(7 downto 0)=>INT_REG(7 downto 0),
- PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
- PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
- PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
- PCI_RSTn=>PCI_RSTn,
- R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
- REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
- VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
- PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
- PCI_PAR=>PCI_PAR,
- AD_REG(31 downto 0)=>AD_REG(31 downto 0),
- DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
- PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
- PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
- PCI_TRDYn=>watch_PCI_TRDYn,
- READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
- READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
- READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
- REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
- REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
- REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
- TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
- WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
- WRITE_XX7_6=>WRITE_XX7_6 );
-
- receive_fifo : dhwk_fifo
- port map (
- clk => PCI_CLOCK,
- din => R_FIFO_D_IN,
- rd_en => not R_FIFO_READn,
- rst => not R_FIFO_RESETn,
- wr_en => not R_FIFO_WRITEn,
- dout => R_FIFO_Q_OUT,
- empty => R_EFn,
- full => R_FFn,
- prog_full => R_HFn);
-
- send_fifo : dhwk_fifo
- port map (
- clk => PCI_CLOCK,
- din => S_FIFO_D_IN,
- rd_en => not S_FIFO_READn,
- rst => not S_FIFO_RESETn,
- wr_en => not S_FIFO_WRITEn,
- dout => S_FIFO_Q_OUT,
- empty => S_EFn,
- full => S_FFn,
- prog_full => S_HFn);
-
- i_icon : icon
- port map
- (
- control0 => control0
- );
-
- i_ila : ila
- port map
- (
- control => control0,
- clk => PCI_CLOCK,
- data => data,
- trig0 => trig0
- );
-end SCHEMATIC;
+++ /dev/null
--- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity USER_IO is
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- ADDR_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- FLAG : In std_logic_vector (7 downto 0);
- INT_REG : In std_logic_vector (7 downto 0);
- IO_WR_COM : In std_logic;
- IRDY_REGn : In std_logic;
- PCI_CLK : In std_logic;
- R_FIFO_Q : In std_logic_vector (7 downto 0);
- READ_SEL : In std_logic_vector (1 downto 0);
- TRDYn : In std_logic;
- READ_XX1_0 : Out std_logic;
- READ_XX3_2 : Out std_logic;
- READ_XX5_4 : Out std_logic;
- READ_XX7_6 : Out std_logic;
- REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
- USER_DATA_OUT : Out std_logic_vector (31 downto 0);
- WRITE_XX1_0 : Out std_logic;
- WRITE_XX3_2 : Out std_logic;
- WRITE_XX5_4 : Out std_logic;
- WRITE_XX7_6 : Out std_logic );
-end USER_IO;
-
-architecture SCHEMATIC of USER_IO is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal WRITE_XX1_0_DUMMY : std_logic;
- signal WRITE_XX7_6_DUMMY : std_logic;
- signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);
- signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);
- signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);
-
- component IO_WR_SEL
- Port ( ADDR_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- IO_WR_COM : In std_logic;
- IRDY_REGn : In std_logic;
- TRDYn : In std_logic;
- WRITE_XX1_0 : Out std_logic;
- WRITE_XX3_2 : Out std_logic;
- WRITE_XX5_4 : Out std_logic;
- WRITE_XX7_6 : Out std_logic );
- end component;
-
- component DATA_MUX
- Port ( ADDR_REG : In std_logic_vector (31 downto 0);
- CBE_REGn : In std_logic_vector (3 downto 0);
- MUX_IN_XX0 : In std_logic_vector (7 downto 0);
- MUX_IN_XX1 : In std_logic_vector (7 downto 0);
- MUX_IN_XX2 : In std_logic_vector (7 downto 0);
- MUX_IN_XX3 : In std_logic_vector (7 downto 0);
- MUX_IN_XX4 : In std_logic_vector (7 downto 0);
- MUX_IN_XX5 : In std_logic_vector (7 downto 0);
- MUX_IN_XX6 : In std_logic_vector (7 downto 0);
- MUX_IN_XX7 : In std_logic_vector (7 downto 0);
- READ_SEL : In std_logic_vector (1 downto 0);
- MUX_OUT : Out std_logic_vector (31 downto 0);
- READ_XX1_0 : Out std_logic;
- READ_XX3_2 : Out std_logic;
- READ_XX5_4 : Out std_logic;
- READ_XX7_6 : Out std_logic );
- end component;
-
- component REG_IO
- Port ( AD_REG : In std_logic_vector (31 downto 0);
- PCI_CLOCK : In std_logic;
- RESET : In std_logic;
- WRITE_XX1_0 : In std_logic;
- WRITE_XX7_6 : In std_logic;
- REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
- REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );
- end component;
-
-begin
-
- REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
- REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
- REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
- WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
- WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
-
- I4 : IO_WR_SEL
- Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
- TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
- WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
- WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
- I2 : DATA_MUX
- Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
- MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
- MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
- MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
- MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
- MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
- MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
- MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
- MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
- READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
- MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
- READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
- READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
- I1 : REG_IO
- Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
- PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
- WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
- WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
- REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
- REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
- REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );
-
-end SCHEMATIC;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VEN_REV_ID.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity VEN_REV_ID is
- port
- (
- VEN_ID :out std_logic_vector(15 downto 0);
- REV_ID :out std_logic_vector( 7 downto 0)
- );
-end entity VEN_REV_ID;
-
-architecture VEN_REV_ID_DESIGN of VEN_REV_ID is
-
-begin
-
- VEN_ID <= X"2222";
- REV_ID <= X"01";
-
-end architecture VEN_REV_ID_DESIGN;
+++ /dev/null
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: VERG_8.VHD
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity VERG_8 is
- port
- (
- GLEICH :in std_logic_vector(7 downto 0);
- GLEICH_OUT :out std_logic
- );
-
-end entity VERG_8;
-
-architecture VERG_8_DESIGN of VERG_8 is
-
-begin
-
- -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
-
- -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0';
- GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0';
-
-end architecture VERG_8_DESIGN;
+++ /dev/null
--- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity VERGLEICH is
- Port ( IN_A : In std_logic_vector (31 downto 0);
- IN_B : In std_logic_vector (31 downto 0);
- GLEICH_OUT : Out std_logic );
-end VERGLEICH;
-
-architecture SCHEMATIC of VERGLEICH is
-
- SIGNAL gnd : std_logic := '0';
- SIGNAL vcc : std_logic := '1';
-
- signal GLEICH : std_logic_vector (7 downto 0);
-
- component VERG_2
- Port ( IN_A : In std_logic_vector (1 downto 0);
- IN_B : In std_logic_vector (1 downto 0);
- GLEICH : Out std_logic );
- end component;
-
- component VERG_8
- Port ( GLEICH : In std_logic_vector (7 downto 0);
- GLEICH_OUT : Out std_logic );
- end component;
-
- component VERG_4
- Port ( IN_A : In std_logic_vector (3 downto 0);
- IN_B : In std_logic_vector (3 downto 0);
- GLEICH : Out std_logic );
- end component;
-
-begin
-
- I11 : VERG_2
- Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),
- IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );
- I9 : VERG_8
- Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),
- GLEICH_OUT=>GLEICH_OUT );
- I8 : VERG_4
- Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),
- IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );
- I7 : VERG_4
- Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),
- IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );
- I6 : VERG_4
- Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),
- IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );
- I5 : VERG_4
- Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),
- IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );
- I4 : VERG_4
- Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),
- IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );
- I3 : VERG_4
- Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),
- IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );
- I2 : VERG_4
- Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),
- IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );
-
-end SCHEMATIC;
projects / raggedstone / commitdiff