all files to lowercase,

[raggedstone] / dhwk / source / ser_par_con.vhd

diff --git a/dhwk/source/ser_par_con.vhd b/dhwk/source/ser_par_con.vhd
new file mode 100644 (file)
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+++ b/dhwk/source/ser_par_con.vhd
@@ -0,0 +1,152 @@
+-- $Id: ser_par_con.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity SER_PAR_CON is
+        port
+        (
+                PCI_CLOCK :in std_logic;
+                RESET :in std_logic;
+                SPC_ENABLE :in std_logic; -- Driver Enable Sender/Receiver
+                SYNC_R_FIFO_FFn :in std_logic; -- FIFO Full Flag (low active)
+                SERIAL_IN :in std_logic; -- Serial Input
+                R_FIFO_WRITEn :out std_logic; -- FIFO Write (low active)
+                SPC_RDY_OUT :out std_logic; -- Ready to Receive Data
+                PAR_OUT :out std_logic_vector(7 downto 0)
+        );
+end entity SER_PAR_CON;
+
+
+architecture SER_PAR_CON_DESIGN of SER_PAR_CON is
+
+-- constant STATE_RECV :std_logic_vector(3 downto 0) := "0001";
+        constant STATE_RECV_START_BIT :std_logic_vector(3 downto 0) := "0010";
+        constant STATE_RECV_BIT_0 :std_logic_vector(3 downto 0) := "0011";
+        constant STATE_RECV_BIT_1 :std_logic_vector(3 downto 0) := "0100";
+        constant STATE_RECV_BIT_2 :std_logic_vector(3 downto 0) := "0101";
+        constant STATE_RECV_BIT_3 :std_logic_vector(3 downto 0) := "0110";
+        constant STATE_RECV_BIT_4 :std_logic_vector(3 downto 0) := "0111";
+        constant STATE_RECV_BIT_5 :std_logic_vector(3 downto 0) := "1000";
+        constant STATE_RECV_BIT_6 :std_logic_vector(3 downto 0) := "1001";
+        constant STATE_RECV_BIT_7 :std_logic_vector(3 downto 0) := "1010";
+        constant STATE_RECV_FIFOFULL :std_logic_vector(3 downto 0) := "1011";
+
+        signal COUNT :std_logic_vector (3 downto 0);
+        signal STATE :std_logic_vector (3 downto 0);
+        signal STARTBIT :std_logic_vector (3 downto 0);
+
+
+        attribute syn_state_machine:boolean;
+        attribute syn_state_machine of STATE: signal is false;
+        attribute syn_state_machine of COUNT: signal is false;
+
+begin
+
+        process(PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                        if ("0000" < COUNT) then
+                                COUNT <= COUNT - 1;
+                        end if;
+
+ -- war nicht das Problem des Datenverlusts
+ -- if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
+ -- R_FIFO_WRITEn <= '1';
+ --- end if;
+
+                        if (RESET = '1') then
+                                STATE <= STATE_RECV_START_BIT;
+                                COUNT <= "0000";
+                                R_FIFO_WRITEn <= '1';
+
+                        elsif (SPC_ENABLE = '1') then
+
+                                if (STATE = STATE_RECV_START_BIT) then
+                                        R_FIFO_WRITEn <= '1';
+                                        if (STARTBIT = "0011") then
+                                                COUNT <= "0011";
+                                                STATE <= STATE_RECV_BIT_0;
+                                        end if;
+
+                                elsif (STATE = STATE_RECV_FIFOFULL) then
+                                        if (SYNC_R_FIFO_FFn = '1') then
+                                                R_FIFO_WRITEn <= '0';
+                                                STATE <= STATE_RECV_START_BIT;
+                                        end if;
+
+                                elsif (COUNT = "0000") then
+                                        COUNT <= "0011";
+                                        case STATE is
+
+                                        when STATE_RECV_BIT_0 =>
+                                                PAR_OUT(0) <= STARTBIT(0);
+                                                STATE <= STATE_RECV_BIT_1;
+
+                                        when STATE_RECV_BIT_1 =>
+                                                PAR_OUT(1) <= STARTBIT(0);
+                                                STATE <= STATE_RECV_BIT_2;
+
+                                        when STATE_RECV_BIT_2 =>
+                                                PAR_OUT(2) <= STARTBIT(0);
+                                                STATE <= STATE_RECV_BIT_3;
+
+                                        when STATE_RECV_BIT_3 =>
+                                                PAR_OUT(3) <= STARTBIT(0);
+                                                STATE <= STATE_RECV_BIT_4;
+
+                                        when STATE_RECV_BIT_4 =>
+                                                PAR_OUT(4) <= STARTBIT(0);
+                                                STATE <= STATE_RECV_BIT_5;
+
+                                        when STATE_RECV_BIT_5 =>
+                                                PAR_OUT(5) <= STARTBIT(0);
+                                                STATE <= STATE_RECV_BIT_6;
+
+                                        when STATE_RECV_BIT_6 =>
+                                                PAR_OUT(6) <= STARTBIT(0);
+                                                STATE <= STATE_RECV_BIT_7;
+
+                                        when STATE_RECV_BIT_7 =>
+                                                PAR_OUT(7) <= STARTBIT(0);
+
+                                                if (SYNC_R_FIFO_FFn = '1') then
+                                                        STATE <= STATE_RECV_START_BIT;
+                                                        R_FIFO_WRITEn <= '0';
+                                                else
+                                                        STATE <= STATE_RECV_FIFOFULL;
+                                                end if;
+
+                                        when others =>
+                                                STATE <= STATE_RECV_START_BIT;
+
+                                        end case;
+                                end if; -- COUNT
+                        end if; -- RESET ... / SPC_ENABLE ...
+                end if; -- PCI_CLOCK ...
+        end process;
+
+        process(PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                        SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
+                end if;
+        end process;
+
+
+        process(PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                        if (RESET = '1') then
+                                STARTBIT <= "0000";
+                        else
+                                STARTBIT(0) <= SERIAL_IN;
+                                STARTBIT(1) <= STARTBIT(0);
+                                STARTBIT(2) <= STARTBIT(1);
+                                STARTBIT(3) <= STARTBIT(2);
+                        end if;
+                end if;
+        end process;
+
+end architecture SER_PAR_CON_DESIGN;