rename pci_7seg to raggedstone

[raggedstone] / heartbeat / source / top_raggedstone.vhd

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 73fefb15d8298f6eaf34a6a9804a2b87ba067da8..283495995ddebc28b886d24c23870a0316705b0b 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -38,7 +38,7 @@ use ieee.std_logic_unsigned.all;
 --|                                                                    ENTITY                                                                          |\r
 --+-----------------------------------------------------------------------------+\r
 \r
 --|                                                                    ENTITY                                                                          |\r
 --+-----------------------------------------------------------------------------+\r
 \r

-entity pci_7seg is\r
+entity raggedstone is\r

 port (\r
 \r
     -- General \r
 port (\r
 \r
     -- General \r


@@ -65,14 +65,14 @@ port (
        LED_ALIVE : out std_logic\r
 \r
 );\r
        LED_ALIVE : out std_logic\r
 \r
 );\r

-end pci_7seg;\r
+end raggedstone;\r

 \r
 \r
 --+-----------------------------------------------------------------------------+\r
 --|                                                                    ARCHITECTURE                                                            |\r
 --+-----------------------------------------------------------------------------+\r
 \r
 \r
 \r
 --+-----------------------------------------------------------------------------+\r
 --|                                                                    ARCHITECTURE                                                            |\r
 --+-----------------------------------------------------------------------------+\r
 \r

-architecture pci_7seg_arch of pci_7seg is\r
+architecture raggedstone_arch of raggedstone is\r

 \r
 \r
 --+-----------------------------------------------------------------------------+\r
 \r
 \r
 --+-----------------------------------------------------------------------------+\r


@@ -194,4 +194,4 @@ port map(
        led_o => LED_ALIVE\r
 );\r
 \r
        led_o => LED_ALIVE\r
 );\r
 \r

-end pci_7seg_arch;\r
+end raggedstone_arch;\r