rename pci_7seg to raggedstone
authormichael <michael>
Sat, 10 Feb 2007 19:41:07 +0000 (19:41 +0000)
committermichael <michael>
Sat, 10 Feb 2007 19:41:07 +0000 (19:41 +0000)
source files also moved, so be sure to do a cvs update -dp _without_
modified files!

common/xc3s1500.batch
heartbeat/Makefile
heartbeat/raggedstone.prj
heartbeat/raggedstone.xst
heartbeat/source/top_raggedstone.vhd

index b1fcb83b5ec80e52124eed3d9342502f93a78376..09751c333d5ae0e052b98728757bcb3e316e7a15 100644 (file)
@@ -1,6 +1,6 @@
 setmode -bscan 
 setcable -p auto 
 identify
-assignFile -p 3 -file pci_7seg.bit
+assignFile -p 3 -file raggedstone.bit
 program -p 3
 quit
index 66afb83751ee96c13bd1910b35d4a5a467718ebb..ac41e7363f797adbfc5b1d53ff2fef2044e9ccb9 100644 (file)
@@ -5,7 +5,7 @@ XST := $(shell which xst)
 TMP = tmp/
 $(shell mkdir tmp)
 
-PROJECT := pci_7seg
+PROJECT := raggedstone
 
 all: xst ngdbuild map par trace prom final
 
index e0adeacf61bce8970c3cc36d43d6937d70eeb7cf..4b24f2b6ce18541d60438a1b43a72ab8a07139b0 100644 (file)
@@ -10,5 +10,5 @@ vhdl work "source/pfs.vhd"
 vhdl work "source/new_pciregs.vhd"
 vhdl work "source/pcipargen.vhd"
 vhdl work "source/new_pci32tlite.vhd"
-vhdl work "source/top_pci_7seg.vhd"
+vhdl work "source/top_raggedstone.vhd"
 vhdl work "source/heartbeat.vhd"
index 33f30fa06089026a95eeaff33dae94625c591f7e..b94c962233b415e5ab6882f4faabb52a19f11444 100644 (file)
@@ -1,15 +1,15 @@
 set -xsthdpdir ./xst
 run
--ifn pci_7seg.prj
+-ifn raggedstone.prj
 -ifmt mixed
--ofn pci_7seg
+-ofn raggedstone
 -ofmt NGC
 -p xc3s1500-4-fg456
--top pci_7seg
+-top raggedstone
 -opt_mode Speed
 -opt_level 1
 -iuc NO
--lso pci_7seg.lso
+-lso raggedstone.lso
 -keep_hierarchy NO
 -glob_opt AllClockNets
 -rtlview Yes
index 73fefb15d8298f6eaf34a6a9804a2b87ba067da8..283495995ddebc28b886d24c23870a0316705b0b 100644 (file)
@@ -38,7 +38,7 @@ use ieee.std_logic_unsigned.all;
 --|                                                                    ENTITY                                                                          |\r
 --+-----------------------------------------------------------------------------+\r
 \r
-entity pci_7seg is\r
+entity raggedstone is\r
 port (\r
 \r
     -- General \r
@@ -65,14 +65,14 @@ port (
        LED_ALIVE : out std_logic\r
 \r
 );\r
-end pci_7seg;\r
+end raggedstone;\r
 \r
 \r
 --+-----------------------------------------------------------------------------+\r
 --|                                                                    ARCHITECTURE                                                            |\r
 --+-----------------------------------------------------------------------------+\r
 \r
-architecture pci_7seg_arch of pci_7seg is\r
+architecture raggedstone_arch of raggedstone is\r
 \r
 \r
 --+-----------------------------------------------------------------------------+\r
@@ -194,4 +194,4 @@ port map(
        led_o => LED_ALIVE\r
 );\r
 \r
-end pci_7seg_arch;\r
+end raggedstone_arch;\r
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