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[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 3036632d887cda9c8b64cf59059f195c65b0dbd8..a79c47032468b8b59def86cd4406abdbf882ad5f 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -16,10 +16,14 @@ entity dhwk is
              PCI_IDSEL : In    std_logic;\r
              PCI_IRDYn : In    std_logic;\r
              PCI_RSTn : In    std_logic;\r
-             SERIAL_IN : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
+--             SERIAL_IN : In    std_logic;\r
+--             SPC_RDY_IN : In    std_logic;\r
              TAST_RESn : In    std_logic;\r
              TAST_SETn : In    std_logic;\r
+             LED_2 : out    std_logic;\r
+             LED_3 : out    std_logic;\r
+             LED_4 : out    std_logic;\r
+             LED_5 : out    std_logic;\r
               PCI_AD : InOut std_logic_vector (31 downto 0);\r
              PCI_PAR : InOut std_logic;\r
              PCI_DEVSELn : Out   std_logic;\r
@@ -28,8 +32,8 @@ entity dhwk is
              PCI_SERRn : Out   std_logic;\r
              PCI_STOPn : Out   std_logic;\r
              PCI_TRDYn : Out   std_logic;\r
-             SERIAL_OUT : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic;\r
+--             SERIAL_OUT : Out   std_logic;\r
+--             SPC_RDY_OUT : Out   std_logic;\r
              TB_IDSEL : Out   std_logic;\r
              TB_nDEVSEL : Out   std_logic;\r
              TB_nINTA : Out   std_logic );\r
@@ -82,6 +86,11 @@ architecture SCHEMATIC of dhwk is
    signal S_FIFO_RESETn : std_logic;\r
    signal S_FIFO_RTn : std_logic;\r
    signal S_FIFO_WRITEn : std_logic;\r
+   signal SERIAL_IN : std_logic;\r
+   signal SPC_RDY_IN : std_logic;\r
+   signal SERIAL_OUT : std_logic;\r
+   signal SPC_RDY_OUT : std_logic;\r
+   signal watch : std_logic;\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
@@ -213,6 +222,13 @@ component fifo_generator_v3_2
 end component;\r
 \r
 begin\r
+       SERIAL_IN <= SERIAL_OUT;\r
+       SPC_RDY_IN <= SPC_RDY_OUT;\r
+       LED_2 <= TAST_RESn;\r
+       LED_3 <= TAST_SETn;\r
+       LED_4 <= '0';\r
+       LED_5 <= not watch;\r
+       PCI_INTAn <= watch;\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
@@ -233,7 +249,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
-                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
+                 INTAn=>INTAn, PCI_INTAn=>watch);\r
    I14 : FIFO_CONTROL\r
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r