--- /dev/null
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: COMM_DEC.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity COMM_DEC is\r
+ port\r
+ (\r
+ PCI_CLOCK :in std_logic; \r
+ PCI_RSTn :in std_logic; \r
+ MY_ADDR :in std_logic;\r
+ IDSEL_REG :in std_logic;\r
+ FRAME_REGn :in std_logic;\r
+ IO_SPACE :in std_logic;\r
+ AD_REG :in std_logic_vector(31 downto 0);\r
+ CBE_REGn :in std_logic_vector( 3 downto 0);\r
+ LAR :out std_logic;--LOAD_ADDR_REG\r
+ IO_READ :out std_logic;\r
+ IO_WRITE :out std_logic;\r
+ CONF_READ :out std_logic;\r
+ CONF_WRITE :out std_logic;\r
+ SERR_CHECK :out std_logic\r
+ );\r
+end entity COMM_DEC ;\r
+\r
+architecture COMM_DEC_DESIGN of COMM_DEC is\r
+\r
+\r
+--PCI Bus Commands \r
+--C/BE[3..0] Command Type\r
+--------------------------------------\r
+-- 0000 Interrupt Acknowledge\r
+-- 0001 Special Cycle\r
+-- 0010 I/O Read\r
+-- 0011 I/O Write\r
+-- 0100 Reserved\r
+-- 0101 Reserved\r
+-- 0110 Memory Read\r
+-- 0111 Memory Write\r
+--\r
+-- 1000 Reserved\r
+-- 1001 Reserved\r
+-- 1010 Configuration Read\r
+-- 1011 Configuration Write\r
+-- 1100 Memory Read Multiple \r
+-- 1101 Dual Address Cycle\r
+-- 1110 Memory Read Line\r
+-- 1111 Memory Write and Invalidate\r
+\r
+\r
+--PCI Byte Enable \r
+--C/BE[3..0] gueltige Datenbits \r
+-------------------------------\r
+-- 0000 AD 31..0\r
+-- 1000 AD 23..0\r
+-- 1100 AD 15..0\r
+-- 1110 AD 7..0\r
+\r
+ constant cmd_int_ack :std_logic_vector(3 downto 0) := "0000";\r
+ constant cmd_sp_cyc :std_logic_vector(3 downto 0) := "0001";\r
+ constant cmd_io_read :std_logic_vector(3 downto 0) := "0010";\r
+ constant cmd_io_write :std_logic_vector(3 downto 0) := "0011";\r
+ constant cmd_res_4 :std_logic_vector(3 downto 0) := "0100";\r
+ constant cmd_res_5 :std_logic_vector(3 downto 0) := "0101";\r
+ constant cmd_mem_read :std_logic_vector(3 downto 0) := "0110";\r
+ constant cmd_mem_write :std_logic_vector(3 downto 0) := "0111";\r
+ constant cmd_res_8 :std_logic_vector(3 downto 0) := "1000";\r
+ constant cmd_res_9 :std_logic_vector(3 downto 0) := "1001";\r
+ constant cmd_conf_read :std_logic_vector(3 downto 0) := "1010";\r
+ constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";\r
+ constant cmd_mem_read_m :std_logic_vector(3 downto 0) := "1100";\r
+ constant cmd_du_adr_cyc :std_logic_vector(3 downto 0) := "1101";\r
+ constant cmd_mem_read_l :std_logic_vector(3 downto 0) := "1110";\r
+ constant cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";\r
+\r
+ signal START :std_logic; \r
+ signal FRAME_REG_REGn :std_logic; \r
+\r
+ signal SIG_IO_READ :std_logic; \r
+ signal SIG_IO_WRITE :std_logic; \r
+ signal SIG_CONF_READ :std_logic; \r
+ signal SIG_CONF_WRITE :std_logic; \r
+\r
+begin\r
+\r
+ process (PCI_CLOCK, PCI_RSTn) \r
+ begin\r
+ if PCI_RSTn = '0' then FRAME_REG_REGn <= '1'; \r
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+ FRAME_REG_REGn <= FRAME_REGn; \r
+\r
+ end if;\r
+ end process;\r
+\r
+\r
+ START <= (not FRAME_REGn) and FRAME_REG_REGn; \r
+\r
+\r
+\r
+ SIG_IO_READ <= '1' when START = '1'\r
+ and IO_SPACE = '1'\r
+ and CBE_REGn = cmd_io_read \r
+ and MY_ADDR = '1'\r
+ else '0'; \r
+\r
+\r
+ SIG_IO_WRITE <= '1' when START = '1'\r
+ and IO_SPACE = '1'\r
+ and CBE_REGn = cmd_io_write\r
+ and MY_ADDR = '1'\r
+ else '0'; \r
+\r
+\r
+ SIG_CONF_READ <= '1' when START = '1'\r
+ and AD_REG(1 downto 0) = "00"\r
+ and CBE_REGn = cmd_conf_read\r
+ and IDSEL_REG = '1'\r
+ \r
+ else '0'; \r
+\r
+\r
+ SIG_CONF_WRITE <= '1' when START = '1'\r
+ and AD_REG(1 downto 0) = "00"\r
+ and CBE_REGn = cmd_conf_write\r
+ and IDSEL_REG = '1'\r
+ else '0'; \r
+\r
+ LAR <= START;\r
+\r
+ SERR_CHECK <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE; \r
+\r
+ IO_READ <= SIG_IO_READ;\r
+ IO_WRITE <= SIG_IO_WRITE; \r
+ CONF_READ <= SIG_CONF_READ; \r
+ CONF_WRITE <= SIG_CONF_WRITE;\r
+\r
+end architecture COMM_DEC_DESIGN ;\r
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