first import of dhwk.

[raggedstone] / dhwk / source / COMM_FSM.vhd

diff --git a/dhwk/source/COMM_FSM.vhd b/dhwk/source/COMM_FSM.vhd
new file mode 100644 (file)
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--- /dev/null
+++ b/dhwk/source/COMM_FSM.vhd
@@ -0,0 +1,98 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: COMM_FSM.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity COMM_FSM is\r
+       port\r
+       (\r
+       PCI_CLOCK               :in             std_logic; \r
+       PCI_RSTn                :in             std_logic; \r
+       IO_READ                 :in             std_logic;\r
+       IO_WRITE                :in             std_logic;\r
+       CONF_READ               :in             std_logic;\r
+       CONF_WRITE      :in             std_logic;\r
+       DEVSELn                 :in             std_logic;      \r
+\r
+       IO_RD_COM       :       out     std_logic;--> MUX_SEL(0)                                                      \r
+       CF_RD_COM       :out    std_logic; \r
+       IO_WR_COM               :out    std_logic;     \r
+       CF_WR_COM               :out    std_logic \r
+       );\r
+end entity COMM_FSM ;\r
+\r
+architecture COMM_FSM_DESIGN of COMM_FSM is\r
+\r
+\r
+--**********************************************************\r
+--***            COMMAND FSM CODIERUNG                   ***\r
+--**********************************************************\r
+--\r
+--\r
+--                                                                        |--------- IO_RD_COM                                                    \r
+--                                                                        ||-------- CF_RD_COM   \r
+--                                                                                    |||------- IO_WR_COM   \r
+--                                                                                ||||------ CF_WR_COM   \r
+--                                                                            ||||     \r
+       constant        ST_IDLE_COMM    :std_logic_vector (3 downto 0) := "0000" ;-- \r
+       constant        ST_CONF_WRITE   :std_logic_vector (3 downto 0) := "0001" ;-- \r
+       constant        ST_IO_WRITE             :std_logic_vector (3 downto 0) := "0010" ;-- \r
+       constant        ST_CONF_READ    :std_logic_vector (3 downto 0) := "0100" ;-- \r
+       constant        ST_IO_READ              :std_logic_vector (3 downto 0) := "1000" ;--\r
+\r
+       signal          COMM_STATE              :std_logic_vector (3 downto 0);\r
+\r
+--************************************************************\r
+--***             FSM SPEICHER-AUTOMAT                     ***\r
+--************************************************************\r
+\r
+       attribute syn_state_machine : boolean;\r
+       attribute syn_state_machine of COMM_STATE : signal is false;\r
+\r
+begin\r
+\r
+--**********************************************************\r
+--***                   COMMAND FSM                        ***\r
+--**********************************************************\r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then    COMM_STATE      <= "0000";\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+ \r
+                       case COMM_STATE is\r
+       \r
+                               when ST_IDLE_COMM => \r
+                                       if              IO_READ                         = '1' then                                                      COMM_STATE <= ST_IO_READ;\r
+\r
+                               elsif   CONF_READ               = '1' then                                                      COMM_STATE <= ST_CONF_READ; \r
+\r
+                                               elsif   IO_WRITE                = '1' then                                                      COMM_STATE <= ST_IO_WRITE;   \r
+  \r
+                               elsif   CONF_WRITE      = '1' then                                                      COMM_STATE <= ST_CONF_WRITE;     \r
+\r
+                   else                                                                                                                                                COMM_STATE <= ST_IDLE_COMM;\r
+                                       end if;                                                 \r
+       \r
+                               when ST_IO_READ                 => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
+                               when ST_CONF_READ               => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
+                               when ST_IO_WRITE                => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
+                               when ST_CONF_WRITE      => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;\r
+       \r
+                               when others =>                                                                                                                          COMM_STATE <= ST_IDLE_COMM; \r
+\r
+                       end case;               -- COMM_STATE    \r
+               end if;                         -- CLOCK   \r
+       end process;            -- PROCESS\r
+\r
+       IO_RD_COM       <=      COMM_STATE(3);                                                     \r
+       CF_RD_COM       <=      COMM_STATE(2);      \r
+       IO_WR_COM       <=      COMM_STATE(1);      \r
+       CF_WR_COM       <=      COMM_STATE(0);      \r
+       \r
+end architecture COMM_FSM_DESIGN ;\r
+\r