first import of dhwk.

[raggedstone] / dhwk / source / INTERRUPT.vhd

diff --git a/dhwk/source/INTERRUPT.vhd b/dhwk/source/INTERRUPT.vhd
new file mode 100644 (file)
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--- /dev/null
+++ b/dhwk/source/INTERRUPT.vhd
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+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: INTERRUPT.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity INTERRUPT is\r
+       port\r
+       (\r
+       PCI_CLOCK               :in             std_logic;\r
+       PCI_RSTn                :in     std_logic; -- PCI reset is asynchron (low active)\r
+       RESET                           :in     std_logic;\r
+       TAST_SETn               :in     std_logic;\r
+       TAST_RESn               :in     std_logic;\r
+       INT_IN_0                :in             std_logic;\r
+       INT_IN_1                :in             std_logic;\r
+       INT_IN_2                :in             std_logic;\r
+       INT_IN_3                :in             std_logic;\r
+       INT_IN_4                :in             std_logic;\r
+       INT_IN_5                :in             std_logic;\r
+       INT_IN_6                :in             std_logic;\r
+       INT_IN_7                :in             std_logic;\r
+       TRDYn                           :in     std_logic;  -- event 1 after read of Interrupt status register (low active)\r
+       READ_XX5_4      :in     std_logic;      -- event 2 after read of Interrupt status register\r
+       INT_RES                 :in             std_logic_vector(7 downto 0); -- clear selected interrupts\r
+       INT_MASKE               :in             std_logic_vector(7 downto 0);   -- interrupt mask register\r
+       INT_REG                 :out    std_logic_vector(7 downto 0); -- interrupt status register\r
+       INTAn                           :out    std_logic;      -- second interrupt line for PCI analyzer\r
+       PCI_INTAn               :out    std_logic               -- PCI interrupt line \r
+       );\r
+\r
+end entity INTERRUPT;\r
+\r
+architecture INTERRUPT_DESIGN of INTERRUPT is\r
+\r
+       signal  SIG_TAST_Q              :std_logic;\r
+       signal  SIG_TAST_Qn             :std_logic;\r
+\r
+\r
+       signal  SIG_INTA                        :std_logic; \r
+\r
+       signal FF_A                     :std_logic_vector(7 downto 0);\r
+       signal FF_B                     :std_logic_vector(7 downto 0);  \r
+       signal SET                      :std_logic_vector(7 downto 0);  \r
+\r
+       signal  SIG_PROPAGATE_INT :std_logic;\r
+       signal  SIG_PROPAGATE_INT_SECOND :std_logic;\r
+       signal  REG :std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+\r
+\r
+\r
+------------------------------------------------------\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
+\r
+                       SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);\r
+                       \r
+                       SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);\r
+       \r
+               end if;\r
+       end process;    \r
+\r
+------------------------------------------------------\r
+\r
+       process (PCI_CLOCK)\r
+       begin\r
+    if (PCI_RSTn = '0') then\r
+                                       SET <= "00000000";\r
+          FF_A <= "00000000";\r
+          FF_B <= "00000000";\r
+\r
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
+               if(RESET = '1') then\r
+                                               SET <= "00000000";\r
+            FF_A       <= "00000000";\r
+            FF_B       <= "00000000";\r
+      else     \r
+\r
+                       FF_A(0) <=                      INT_IN_0 ;  -- Receive FIFO Empty Flag\r
+\r
+                       FF_A(1) <=                      INT_IN_1 ;  -- Send FIFO Half Full\r
+                       FF_A(2) <=                      INT_IN_2 ; \r
+                       FF_A(3) <=                      INT_IN_3 ; \r
+\r
+                       FF_A(4) <=                      INT_IN_4 ; \r
+\r
+                       FF_A(5) <=                      INT_IN_5 ; \r
+                       FF_A(6) <=                      INT_IN_6 ; \r
+                       FF_A(7) <=                      INT_IN_7 ; \r
+\r
+                       FF_B    <= FF_A ;\r
+\r
+                       SET <= FF_A AND not FF_B;\r
+               end if;\r
+               end if;\r
+       end process;\r
+\r
+       process (PCI_CLOCK,PCI_RSTn)\r
+       begin\r
+               if (PCI_RSTn = '0') then\r
+                       REG <= "00000000";\r
+\r
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
+                               if(RESET = '1') then\r
+                                       REG <= "00000000";\r
+\r
+               elsif(SIG_TAST_Q = '1') then\r
+                       REG <= "00000000" or SET;\r
+\r
+        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
+            REG <= (REG AND NOT INT_RES) OR SET;\r
+        else\r
+            REG <= REG OR SET;\r
+        end if;\r
+    end if;\r
+       end process;\r
+\r
+       SIG_PROPAGATE_INT <= SIG_TAST_Q \r
+            OR (REG(0) AND INT_MASKE(0)) \r
+            OR (REG(1) AND INT_MASKE(1))\r
+            OR (REG(2) AND INT_MASKE(2))\r
+            OR (REG(3) AND INT_MASKE(3))\r
+            OR (REG(4) AND INT_MASKE(4))\r
+            OR (REG(5) AND INT_MASKE(5))\r
+            OR (REG(6) AND INT_MASKE(6))\r
+            OR (REG(7) AND INT_MASKE(7));\r
+\r
+       process (PCI_CLOCK)\r
+       begin\r
+               if(PCI_CLOCK'event      and     PCI_CLOCK       =       '1')    then\r
+       SIG_PROPAGATE_INT_SECOND        <= not SIG_PROPAGATE_INT;\r
+    end if;\r
+  end process;\r
+\r
+\r
+         INTAn <= not SIG_PROPAGATE_INT_SECOND;\r
+       PCI_INTAn       <= '0'  when SIG_PROPAGATE_INT_SECOND = '0'     else    'Z';\r
+\r
+       INT_REG <= REG;\r
+\r
+end architecture INTERRUPT_DESIGN;\r