first import of dhwk.

[raggedstone] / dhwk / source / IO_RW_SEL.vhd

diff --git a/dhwk/source/IO_RW_SEL.vhd b/dhwk/source/IO_RW_SEL.vhd
new file mode 100644 (file)
index 0000000..44419d8
--- /dev/null
+++ b/dhwk/source/IO_RW_SEL.vhd
@@ -0,0 +1,54 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_WR_SEL.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity IO_WR_SEL is\r
+       port\r
+       (\r
+       IO_WR_COM               :in             std_logic;\r
+       IRDY_REGn               :in             std_logic;\r
+       TRDYn                           :in             std_logic;\r
+       ADDR_REG                :in             std_logic_vector(31 downto 0);\r
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
+       WRITE_XX1_0     :out    std_logic;\r
+       WRITE_XX3_2     :out    std_logic;\r
+       WRITE_XX5_4     :out    std_logic;\r
+       WRITE_XX7_6     :out    std_logic \r
+       );\r
+end entity IO_WR_SEL;\r
+\r
+--PCI Byte Enable \r
+--C/BE[3..0] gueltige Datenbits \r
+-------------------------------\r
+--     0000            AD 31..0\r
+--     1000            AD 23..0\r
+--     1100            AD 15..0\r
+--     1110            AD  7..0\r
+--     0011            AD 31..16\r
+\r
+architecture IO_WR_SEL_DESIGN of IO_WR_SEL is\r
+\r
+       signal  WR_ENA  :std_logic;\r
+       signal  ADDR            :std_logic_vector( 5 downto 0); \r
+\r
+begin\r
+\r
+               WR_ENA  <=      '1' when\r
+                                                                               IO_WR_COM = '1' and\r
+                                                                               IRDY_REGn       =       '0' and\r
+                                                                               TRDYn                   =       '0'     else    '0';\r
+\r
+\r
+               ADDR    <=       ADDR_REG(3) &  ADDR_REG(2)     &       CBE_REGn;\r
+\r
+\r
+               WRITE_XX1_0     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "001100"        else '0';        \r
+               WRITE_XX3_2     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "000011"        else '0';\r
+               WRITE_XX5_4     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "011100"        else '0';        \r
+               WRITE_XX7_6     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "010011"        else '0';\r
+       \r
+end architecture IO_WR_SEL_DESIGN;\r