first import of dhwk.

[raggedstone] / dhwk / source / Io_mux.vhd

diff --git a/dhwk/source/Io_mux.vhd b/dhwk/source/Io_mux.vhd
new file mode 100644 (file)
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+++ b/dhwk/source/Io_mux.vhd
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+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: IO_MUX.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity IO_MUX is\r
+       port\r
+       (\r
+       READ_SEL                        :in             std_logic_vector ( 1 downto 0);\r
+       USER_DATA                       :in             std_logic_vector (31 downto 0);\r
+       CONFIG_DATA             :in             std_logic_vector (31 downto 0);\r
+       PCI_AD                          :in             std_logic_vector (31 downto 0);\r
+       IO_DATA                         :out    std_logic_vector (31 downto 0)\r
+       );\r
+end entity IO_MUX;\r
+\r
+architecture IO_MUX_DESIGN of IO_MUX is\r
+\r
+       signal  MUX             :std_logic_vector (31 downto 0); \r
+\r
+begin \r
+\r
+       MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG \r
+                                       PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO\r
+                                       CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG \r
+                                       USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO      \r
+                                       CONFIG_DATA;\r
+\r
+--                                     MUX;\r
+\r
+       IO_DATA <= MUX;\r
+\r
+end architecture IO_MUX_DESIGN;\r