--- /dev/null
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: PARITY_4.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity PARITY_4 is\r
+ port\r
+ (\r
+ PAR_IN :in std_logic_vector(3 downto 0); \r
+ PAR_OUT :out std_logic\r
+ );\r
+end entity PARITY_4 ; \r
+\r
+architecture PARITY_4_DESIGN of PARITY_4 is\r
+\r
+begin\r
+\r
+ PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;\r
+\r
+end architecture PARITY_4_DESIGN;\r