+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_04H.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_04H is\r
+ port\r
+ (\r
+ PCI_CLOCK :in std_logic;\r
+ PCI_RSTn :in std_logic;\r
+ SERR :in std_logic;\r
+ PERR :in std_logic;\r
+ AD_REG :in std_logic_vector(31 downto 0);\r
+ CBE_REGn :in std_logic_vector( 3 downto 0);\r
+ CONF_WR_04H :in std_logic;\r
+ CONF_DATA_04H :out std_logic_vector(31 downto 0)\r
+ );\r
+end entity CONFIG_04H;\r
+\r
+architecture CONFIG_04H_DESIGN of CONFIG_04H is\r
+\r
+ signal CONF_STATUS :std_logic_vector(31 downto 16);\r
+ signal CONF_COMMAND :std_logic_vector(15 downto 0);\r
+\r
+\r
+begin\r
+\r
+--*******************************************************************\r
+--************* PCI Configuration Space Header "STATUS" *************\r
+--*******************************************************************\r
+\r
+ CONF_STATUS(20 downto 16) <= "00000" ;-- Reserved\r
+ CONF_STATUS(21 ) <= '0' ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz\r
+ CONF_STATUS(22 ) <= '0' ;-- MAS/TAR: "R_O" \r
+ CONF_STATUS(23 ) <= '0' ;-- ???/???: "R_O" : fast back-to-back\r
+ CONF_STATUS(24 ) <= '0' ;-- Master :\r
+--CONF_STATUS(26 downto 25) <= "00" ;-- Mas/Tar: "R_O" : timing fast for "DEVSEL"\r
+ CONF_STATUS(26 downto 25) <= "01" ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"\r
+--CONF_STATUS(26 downto 25) <= "10" ;-- Mas/Tar: "R_O" : timing slow for "DEVSEL"\r
+--CONF_STATUS(26 downto 25) <= "11" ;-- Mas/Tar: "R_O" : reserved\r
+ CONF_STATUS(27 ) <= '0' ;-- Target : "R_W" : Taget-Abort\r
+ CONF_STATUS(28 ) <= '0' ;-- Master : "R_W" : Taget-Abort\r
+ CONF_STATUS(29 ) <= '0' ;-- Master : "R_W" : Master-Abort\r
+--CONF_STATUS(30 ) <= SERR ;-- Mas/Tar: "R_W" : SERR\r
+--CONF_STATUS(31 ) <= PERR ;-- Mas/Tar: "R_W" : PERR\r
+\r
+ process (PCI_CLOCK,PCI_RSTn) \r
+ begin\r
+ if PCI_RSTn = '0' then CONF_STATUS(30) <= '0';\r
+ CONF_STATUS(31) <= '0';\r
+\r
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+ if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then \r
+\r
+ CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); \r
+ CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));\r
+\r
+ else CONF_STATUS(30) <= SERR or CONF_STATUS(30);\r
+ CONF_STATUS(31) <= PERR or CONF_STATUS(31);\r
+\r
+ end if; \r
+ end if; \r
+ end process;\r
+\r
+--*******************************************************************\r
+--*********** PCI Configuration Space Header "COMMAND" **************\r
+--*******************************************************************\r
+\r
+-- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???\r
+-- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???\r
+-- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus \r
+-- CONF_COMMAND( 3) <= '0';-- Special Cycle ???\r
+-- CONF_COMMAND( 4) <= '0';-- Master ??? \r
+-- CONF_COMMAND( 5) <= '0';-- VGA ???\r
+-- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable\r
+ CONF_COMMAND( 7) <= '0';-- address/data stepping ???\r
+-- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"\r
+-- CONF_COMMAND( 9) <= '0';-- fast back-to-back\r
+-- CONF_COMMAND(10) <= '0';-- Reserved\r
+-- CONF_COMMAND(11) <= '0';-- Reserved\r
+-- CONF_COMMAND(12) <= '0';-- Reserved\r
+-- CONF_COMMAND(13) <= '0';-- Reserved\r
+-- CONF_COMMAND(14) <= '0';-- Reserved\r
+-- CONF_COMMAND(15) <= '0';-- Reserved\r
+\r
+ process (PCI_CLOCK,PCI_RSTn) \r
+ begin\r
+ if PCI_RSTn = '0' then CONF_COMMAND(15 downto 8) <= (others =>'0');\r
+ CONF_COMMAND( 6 downto 0) <= (others =>'0');\r
+\r
+ elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+ if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then \r
+\r
+ CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);\r
+ else CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);\r
+ end if;\r
+\r
+\r
+ if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then \r
+\r
+ CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);\r
+ else CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);\r
+ end if;\r
+\r
+ end if;\r
+ end process;\r
+\r
+ CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND; \r
+\r
+end architecture CONFIG_04H_DESIGN;\r
projects / raggedstone / blobdiff