first import of dhwk.

[raggedstone] / dhwk / source / config_10h.vhd

diff --git a/dhwk/source/config_10h.vhd b/dhwk/source/config_10h.vhd
new file mode 100644 (file)
index 0000000..6621607
--- /dev/null
+++ b/dhwk/source/config_10h.vhd
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+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_10H.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_10H is\r
+       port\r
+       (\r
+       PCI_CLOCK                       :in             std_logic;\r
+       PCI_RSTn                        :in             std_logic;\r
+       AD_REG                          :in             std_logic_vector(31 downto 0);\r
+       CBE_REGn                        :in             std_logic_vector( 3 downto 0);\r
+       CONF_WR_10H             :in             std_logic;\r
+       CONF_DATA_10H   :out    std_logic_vector(31 downto 0)\r
+       );\r
+end entity CONFIG_10H;\r
+\r
+architecture CONFIG_10H_DESIGN of CONFIG_10H is\r
+\r
+       signal          CONF_BAS_ADDR_REG       :std_logic_vector(31 downto  0);\r
+\r
+begin\r
+\r
+--*******************************************************************\r
+--***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******\r
+--*******************************************************************\r
+\r
+       CONF_BAS_ADDR_REG(1 downto 0) <= "01"   ;-- Base Address Register for "I/O"\r
+       CONF_BAS_ADDR_REG(3 downto 2)   <= "00" ;-- IO Bereich = 16 BYTE\r
+\r
+       process (PCI_CLOCK,PCI_RSTn) \r
+       begin\r
+\r
+--     if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');\r
+               if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');\r
+                                                               \r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(3) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);\r
+\r
+                               else    CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);\r
+                       end if;\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(2) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);\r
+\r
+                               else    CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);\r
+                       end if;\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(1) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG(15 downto  8) <= AD_REG(15 downto  8);\r
+\r
+                               else    CONF_BAS_ADDR_REG(15 downto  8) <= CONF_BAS_ADDR_REG(15 downto  8);\r
+                       end if;\r
+\r
+--                     if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
+--\r
+--                                                     CONF_BAS_ADDR_REG( 7 downto  2) <= AD_REG( 7 downto  2);\r
+--\r
+--                             else    CONF_BAS_ADDR_REG( 7 downto  2) <= CONF_BAS_ADDR_REG( 7 downto  2);\r
+--                     end if;\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG( 7 downto  4) <= AD_REG( 7 downto  4);\r
+\r
+                               else    CONF_BAS_ADDR_REG( 7 downto  4) <= CONF_BAS_ADDR_REG( 7 downto  4);\r
+                       end if;\r
+\r
+\r
+               end if;\r
+\r
+       end process;\r
+\r
+       CONF_DATA_10H   <= CONF_BAS_ADDR_REG;\r
+\r
+end architecture CONFIG_10H_DESIGN;\r
+\r
+\r
+\r