first import of dhwk.

[raggedstone] / dhwk / source / fifo_io_control.vhd

diff --git a/dhwk/source/fifo_io_control.vhd b/dhwk/source/fifo_io_control.vhd
new file mode 100644 (file)
index 0000000..514f078
--- /dev/null
+++ b/dhwk/source/fifo_io_control.vhd
@@ -0,0 +1,110 @@
+-- $Id: fifo_io_control.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity FIFO_IO_CONTROL is\r
+       port\r
+       (\r
+       PCI_CLOCK                               :in     std_logic;\r
+       WRITE_XX1_0                             :in     std_logic; -- PCI Write\r
+       FIFO_RDn                                :in     std_logic; -- FIFO Read (low active)\r
+       RESET                                   :in     std_logic;\r
+       SYNC_FLAG_1                             :in     std_logic; -- Recv FIFO Empty (low active)\r
+       SYNC_FLAG_7                             :in     std_logic; -- Send FIFO Full (low active)\r
+       S_FIFO_RESETn                           :out    std_logic; -- Send FIFO Reset (low active)\r
+       R_FIFO_RESETn                           :out    std_logic; -- Recv FIFO Reset (low active)\r
+       S_FIFO_WRITEn                           :out    std_logic; -- Send FIFO Write (low active)\r
+       R_FIFO_READn                            :out    std_logic; -- Recv FIFO Read (low active)\r
+       S_FIFO_RETRANSMITn                      :out    std_logic; -- Send FIFO Retransmit (low active)\r
+       R_FIFO_RETRANSMITn                      :out    std_logic; -- Recv FIFO Retransmit (low active)\r
+       S_ERROR                                 :out    std_logic; -- Send ERROR\r
+       R_ERROR                                 :out    std_logic; -- Recv ERROR\r
+       SR_ERROR                                :out    std_logic  -- Send / Recv Error\r
+       );      \r
+end entity FIFO_IO_CONTROL;\r
+\r
+architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is\r
+\r
+signal SIG_S_ERROR     :std_logic; -- Send Error\r
+signal SIG_R_ERROR     :std_logic; -- Recv Error\r
+\r
+begin\r
+\r
+-- FIFO Write\r
+\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if (PCI_CLOCK'event and PCI_CLOCK = '1')  then  \r
+                        if (RESET = '1') then\r
+                                S_FIFO_WRITEn <= '1';\r
+                                SIG_S_ERROR   <= '0';\r
+\r
+                        elsif (WRITE_XX1_0 = '0') then\r
+                                S_FIFO_WRITEn <= '1';\r
+\r
+                        elsif (WRITE_XX1_0 = '1') then\r
+                                if (SYNC_FLAG_7 = '0') then\r
+                                        SIG_S_ERROR <= '1';\r
+\r
+                                elsif (SYNC_FLAG_7 = '1') then\r
+                                        S_FIFO_WRITEn <= '0';\r
+                                        SIG_S_ERROR <= '0';\r
+                                end if;\r
+                                                                                               end if;\r
+               end if;\r
+       end process;    \r
+\r
+       S_ERROR <= SIG_S_ERROR;\r
+               \r
+-- FIFO Read\r
+\r
+       R_FIFO_READn <= FIFO_RDn;       \r
+\r
+-- Receive Error\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
+                if (RESET = '1') then\r
+                        SIG_R_ERROR <= '0';\r
+\r
+                elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then\r
+                        SIG_R_ERROR <= '1';\r
+                end if;\r
+        end if;\r
+end process; \r
+\r
+       R_ERROR <=      SIG_R_ERROR;            \r
+\r
+-- Send or Receive Error\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
+                SR_ERROR       <= SIG_S_ERROR or SIG_R_ERROR;\r
+        end if;\r
+end process; \r
+\r
+-- FIFO Reset\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
+                S_FIFO_RESETn <= not RESET;    \r
+                R_FIFO_RESETn <= not RESET;    \r
+        end if;\r
+end process;   \r
+\r
+\r
+-- FIFO Retransmit\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
+                S_FIFO_RETRANSMITn <= '1';     \r
+                R_FIFO_RETRANSMITn <= '1';     \r
+        end if;\r
+end process; \r
+       \r
+end architecture FIFO_IO_CONTROL_DESIGN;\r