first import of dhwk.

[raggedstone] / dhwk / source / parity.vhd

diff --git a/dhwk/source/parity.vhd b/dhwk/source/parity.vhd
new file mode 100644 (file)
index 0000000..b0dce43
--- /dev/null
+++ b/dhwk/source/parity.vhd
@@ -0,0 +1,106 @@
+-- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007\r
+\r
+--LIBRARY vanmacro;\r
+--USE vanmacro.components.ALL;\r
+LIBRARY ieee;\r
+--LIBRARY generics;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+--USE generics.components.ALL;\r
+\r
+entity PARITY is\r
+      Port ( OE_PCI_PAR : In    std_logic;\r
+             OE_PCI_PERR : In    std_logic;\r
+             PA_ER_RE : In    std_logic;\r
+              PAR_IN : In    std_logic_vector (35 downto 0);\r
+             PAR_REG : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             PERR_CHECK : In    std_logic;\r
+             SERR_CHECK : In    std_logic;\r
+             SERR_ENA : In    std_logic;\r
+             PCI_PAR : InOut std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+                PERR : Out   std_logic;\r
+                SERR : Out   std_logic );\r
+end PARITY;\r
+\r
+architecture SCHEMATIC of PARITY is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal  PAR_OUT : std_logic_vector (10 downto 0);\r
+\r
+   component PARITY_OUT\r
+      Port ( OE_PCI_PAR : In    std_logic;\r
+             OE_PCI_PERR : In    std_logic;\r
+             PA_ER_RE : In    std_logic;\r
+              PAR_IN : In    std_logic_vector (2 downto 0);\r
+             PAR_REG : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_PAR_IN : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             PERR_CHECK : In    std_logic;\r
+             SERR_CHECK : In    std_logic;\r
+             SERR_ENA : In    std_logic;\r
+             PCI_PAR : Out   std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+                PERR : Out   std_logic;\r
+                SERR : Out   std_logic );\r
+   end component;\r
+\r
+   component PARITY_4\r
+      Port (  PAR_IN : In    std_logic_vector (3 downto 0);\r
+             PAR_OUT : Out   std_logic );\r
+   end component;\r
+\r
+begin\r
+\r
+   I12 : PARITY_OUT\r
+      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
+                 PA_ER_RE=>PA_ER_RE,\r
+                 PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),\r
+                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
+                 PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,\r
+                 SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,\r
+                 PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,\r
+                 SERR=>SERR );\r
+   I9 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),\r
+                 PAR_OUT=>PAR_OUT(8) );\r
+   I11 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),\r
+                 PAR_OUT=>PAR_OUT(10) );\r
+   I8 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),\r
+                 PAR_OUT=>PAR_OUT(7) );\r
+   I7 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),\r
+                 PAR_OUT=>PAR_OUT(6) );\r
+   I6 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),\r
+                 PAR_OUT=>PAR_OUT(5) );\r
+   I5 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),\r
+                 PAR_OUT=>PAR_OUT(4) );\r
+   I4 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),\r
+                 PAR_OUT=>PAR_OUT(3) );\r
+   I3 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),\r
+                 PAR_OUT=>PAR_OUT(2) );\r
+   I2 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),\r
+                 PAR_OUT=>PAR_OUT(1) );\r
+   I1 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),\r
+                 PAR_OUT=>PAR_OUT(0) );\r
+   I10 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),\r
+                 PAR_OUT=>PAR_OUT(9) );\r
+\r
+end SCHEMATIC;\r