--- /dev/null
+-- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity PCI_TOP is\r
+ Port ( FLAG : In std_logic_vector (7 downto 0);\r
+ INT_REG : In std_logic_vector (7 downto 0);\r
+ PCI_CBEn : In std_logic_vector (3 downto 0);\r
+ PCI_CLOCK : In std_logic;\r
+ PCI_FRAMEn : In std_logic;\r
+ PCI_IDSEL : In std_logic;\r
+ PCI_IRDYn : In std_logic;\r
+ PCI_RSTn : In std_logic;\r
+ R_FIFO_Q : In std_logic_vector (7 downto 0);\r
+ REVISON_ID : In std_logic_vector (7 downto 0);\r
+ VENDOR_ID : In std_logic_vector (15 downto 0);\r
+ PCI_AD : InOut std_logic_vector (31 downto 0);\r
+ PCI_PAR : InOut std_logic;\r
+ AD_REG : Out std_logic_vector (31 downto 0);\r
+ DEVSELn : Out std_logic;\r
+ FIFO_RDn : Out std_logic;\r
+ PCI_DEVSELn : Out std_logic;\r
+ PCI_PERRn : Out std_logic;\r
+ PCI_SERRn : Out std_logic;\r
+ PCI_STOPn : Out std_logic;\r
+ PCI_TRDYn : Out std_logic;\r
+ READ_SEL : Out std_logic_vector (1 downto 0);\r
+ READ_XX1_0 : Out std_logic;\r
+ READ_XX3_2 : Out std_logic;\r
+ READ_XX5_4 : Out std_logic;\r
+ READ_XX7_6 : Out std_logic;\r
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
+ TRDYn : Out std_logic;\r
+ WRITE_XX1_0 : Out std_logic;\r
+ WRITE_XX3_2 : Out std_logic;\r
+ WRITE_XX5_4 : Out std_logic;\r
+ WRITE_XX7_6 : Out std_logic );\r
+end PCI_TOP;\r
+\r
+architecture SCHEMATIC of PCI_TOP is\r
+\r
+ SIGNAL gnd : std_logic := '0';\r
+ SIGNAL vcc : std_logic := '1';\r
+\r
+ signal IRDY_REGn : std_logic;\r
+ signal IO_WR_COM : std_logic;\r
+ signal TRDYn_DUMMY : std_logic;\r
+ signal READ_XX3_2_DUMMY : std_logic;\r
+ signal USER_DATA_OUT : std_logic_vector (31 downto 0);\r
+ signal CBE_REGn : std_logic_vector (3 downto 0);\r
+ signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
+ signal ADDR_REG : std_logic_vector (31 downto 0);\r
+ signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
+\r
+ component USER_IO\r
+ Port ( AD_REG : In std_logic_vector (31 downto 0);\r
+ ADDR_REG : In std_logic_vector (31 downto 0);\r
+ CBE_REGn : In std_logic_vector (3 downto 0);\r
+ FLAG : In std_logic_vector (7 downto 0);\r
+ INT_REG : In std_logic_vector (7 downto 0);\r
+ IO_WR_COM : In std_logic;\r
+ IRDY_REGn : In std_logic;\r
+ PCI_CLK : In std_logic;\r
+ R_FIFO_Q : In std_logic_vector (7 downto 0);\r
+ READ_SEL : In std_logic_vector (1 downto 0);\r
+ TRDYn : In std_logic;\r
+ READ_XX1_0 : Out std_logic;\r
+ READ_XX3_2 : Out std_logic;\r
+ READ_XX5_4 : Out std_logic;\r
+ READ_XX7_6 : Out std_logic;\r
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
+ USER_DATA_OUT : Out std_logic_vector (31 downto 0);\r
+ WRITE_XX1_0 : Out std_logic;\r
+ WRITE_XX3_2 : Out std_logic;\r
+ WRITE_XX5_4 : Out std_logic;\r
+ WRITE_XX7_6 : Out std_logic );\r
+ end component;\r
+\r
+ component PCI_INTERFACE\r
+ Port ( PCI_CBEn : In std_logic_vector (3 downto 0);\r
+ PCI_CLOCK : In std_logic;\r
+ PCI_FRAMEn : In std_logic;\r
+ PCI_IDSEL : In std_logic;\r
+ PCI_IRDYn : In std_logic;\r
+ PCI_RSTn : In std_logic;\r
+ READ_FIFO : In std_logic;\r
+ REVISON_ID : In std_logic_vector (7 downto 0);\r
+ USER_DATA_OUT : In std_logic_vector (31 downto 0);\r
+ VENDOR_ID : In std_logic_vector (15 downto 0);\r
+ PCI_AD : InOut std_logic_vector (31 downto 0);\r
+ PCI_PAR : InOut std_logic;\r
+ AD_REG : Out std_logic_vector (31 downto 0);\r
+ ADDR_REG : Out std_logic_vector (31 downto 0);\r
+ CBE_REGn : Out std_logic_vector (3 downto 0);\r
+ DEVSELn : Out std_logic;\r
+ FIFO_RDn : Out std_logic;\r
+ IO_WR_COM : Out std_logic;\r
+ IRDY_REGn : Out std_logic;\r
+ PCI_DEVSELn : Out std_logic;\r
+ PCI_PERRn : Out std_logic;\r
+ PCI_SERRn : Out std_logic;\r
+ PCI_STOPn : Out std_logic;\r
+ PCI_TRDYn : Out std_logic;\r
+ READ_SEL : Out std_logic_vector (1 downto 0);\r
+ TRDYn : Out std_logic );\r
+ end component;\r
+\r
+begin\r
+\r
+ READ_SEL <= READ_SEL_DUMMY;\r
+ AD_REG <= AD_REG_DUMMY;\r
+ READ_XX3_2 <= READ_XX3_2_DUMMY;\r
+ TRDYn <= TRDYn_DUMMY;\r
+\r
+ I19 : USER_IO\r
+ Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+ ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+ FLAG(7 downto 0)=>FLAG(7 downto 0),\r
+ INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
+ PCI_CLK=>PCI_CLOCK,\r
+ R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
+ READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
+ TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,\r
+ READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,\r
+ READ_XX7_6=>READ_XX7_6,\r
+ REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),\r
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
+ USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
+ WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,\r
+ WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );\r
+ I10 : PCI_INTERFACE\r
+ Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
+ PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
+ PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
+ PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,\r
+ REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
+ USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
+ VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
+ PCI_PAR=>PCI_PAR,\r
+ AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+ ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+ DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
+ IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
+ PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
+ PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
+ PCI_TRDYn=>PCI_TRDYn,\r
+ READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
+ TRDYn=>TRDYn_DUMMY );\r
+\r
+end SCHEMATIC;\r