first import of dhwk.

[raggedstone] / dhwk / source / steuerung.vhd

diff --git a/dhwk/source/steuerung.vhd b/dhwk/source/steuerung.vhd
new file mode 100644 (file)
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--- /dev/null
+++ b/dhwk/source/steuerung.vhd
@@ -0,0 +1,131 @@
+-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007\r
+\r
+-- LIBRARY vanmacro;\r
+-- USE vanmacro.components.ALL;\r
+LIBRARY ieee;\r
+--LIBRARY generics;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+--USE generics.components.ALL;\r
+\r
+entity STEUERUNG is\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             FRAME_REGn : In    std_logic;\r
+             IDSEL_REG : In    std_logic;\r
+             IO_SPACE : In    std_logic;\r
+             MY_ADDR : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_FIFO : In    std_logic;\r
+             CF_RD_COM : Out   std_logic;\r
+             CF_WR_COM : Out   std_logic;\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             IO_RD_COM : Out   std_logic;\r
+             IO_WR_COM : Out   std_logic;\r
+                 LAR : Out   std_logic;\r
+             OE_PCI_PAR : Out   std_logic;\r
+             OE_PCI_PERR : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             PERR_CHECK : Out   std_logic;\r
+                READ : Out   std_logic;\r
+             SERR_CHECK : Out   std_logic;\r
+               TRDYn : Out   std_logic );\r
+end STEUERUNG;\r
+\r
+architecture SCHEMATIC of STEUERUNG is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal DEVSELn_DUMMY : std_logic;\r
+   signal  IO_READ : std_logic;\r
+   signal IO_WRITE : std_logic;\r
+   signal CONF_READ : std_logic;\r
+   signal CONF_WRITE : std_logic;\r
+\r
+   component CONT_FSM\r
+      Port ( CONF_READ : In    std_logic;\r
+             CONF_WRITE : In    std_logic;\r
+             FIFO_READ : In    std_logic;\r
+             IO_READ : In    std_logic;\r
+             IO_WRITE : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             OE_PCI_PAR : Out   std_logic;\r
+             OE_PCI_PERR : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             PERR_CHECK : Out   std_logic;\r
+                READ : Out   std_logic;\r
+               TRDYn : Out   std_logic );\r
+   end component;\r
+\r
+   component COMM_FSM\r
+      Port ( CONF_READ : In    std_logic;\r
+             CONF_WRITE : In    std_logic;\r
+             DEVSELn : In    std_logic;\r
+             IO_READ : In    std_logic;\r
+             IO_WRITE : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             CF_RD_COM : Out   std_logic;\r
+             CF_WR_COM : Out   std_logic;\r
+             IO_RD_COM : Out   std_logic;\r
+             IO_WR_COM : Out   std_logic );\r
+   end component;\r
+\r
+   component COMM_DEC\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             FRAME_REGn : In    std_logic;\r
+             IDSEL_REG : In    std_logic;\r
+             IO_SPACE : In    std_logic;\r
+             MY_ADDR : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             CONF_READ : Out   std_logic;\r
+             CONF_WRITE : Out   std_logic;\r
+             IO_READ : Out   std_logic;\r
+             IO_WRITE : Out   std_logic;\r
+                 LAR : Out   std_logic;\r
+             SERR_CHECK : Out   std_logic );\r
+   end component;\r
+\r
+begin\r
+\r
+   DEVSELn <= DEVSELn_DUMMY;\r
+\r
+   I1 : CONT_FSM\r
+      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
+                 FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,\r
+                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,\r
+                 FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,\r
+                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
+                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
+                 PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );\r
+   I2 : COMM_FSM\r
+      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
+                 DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,\r
+                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,\r
+                 CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,\r
+                 IO_WR_COM=>IO_WR_COM );\r
+   I3 : COMM_DEC\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
+                 IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
+                 CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
+                 IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,\r
+                 SERR_CHECK=>SERR_CHECK );\r
+\r
+end SCHEMATIC;\r