+-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity TOP is\r
+ Port ( KONST_1 : In std_logic;\r
+ PCI_CBEn : In std_logic_vector (3 downto 0);\r
+ PCI_CLOCK : In std_logic;\r
+ PCI_FRAMEn : In std_logic;\r
+ PCI_IDSEL : In std_logic;\r
+ PCI_IRDYn : In std_logic;\r
+ PCI_RSTn : In std_logic;\r
+ R_EFn : In std_logic;\r
+ R_FFn : In std_logic;\r
+ R_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
+ R_HFn : In std_logic;\r
+ S_EFn : In std_logic;\r
+ S_FFn : In std_logic;\r
+ S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
+ S_HFn : In std_logic;\r
+ SERIAL_IN : In std_logic;\r
+ SPC_RDY_IN : In std_logic;\r
+ TAST_RESn : In std_logic;\r
+ TAST_SETn : In std_logic;\r
+ PCI_AD : InOut std_logic_vector (31 downto 0);\r
+ PCI_PAR : InOut std_logic;\r
+ PCI_DEVSELn : Out std_logic;\r
+ PCI_INTAn : Out std_logic;\r
+ PCI_PERRn : Out std_logic;\r
+ PCI_SERRn : Out std_logic;\r
+ PCI_STOPn : Out std_logic;\r
+ PCI_TRDYn : Out std_logic;\r
+ R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
+ R_FIFO_READn : Out std_logic;\r
+ R_FIFO_RESETn : Out std_logic;\r
+ R_FIFO_RTn : Out std_logic;\r
+ R_FIFO_WRITEn : Out std_logic;\r
+ S_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
+ S_FIFO_READn : Out std_logic;\r
+ S_FIFO_RESETn : Out std_logic;\r
+ S_FIFO_RTn : Out std_logic;\r
+ S_FIFO_WRITEn : Out std_logic;\r
+ SERIAL_OUT : Out std_logic;\r
+ SPC_RDY_OUT : Out std_logic;\r
+ TB_IDSEL : Out std_logic;\r
+ TB_nDEVSEL : Out std_logic;\r
+ TB_nINTA : Out std_logic );\r
+end TOP;\r
+\r
+architecture SCHEMATIC of TOP is\r
+\r
+ SIGNAL gnd : std_logic := '0';\r
+ SIGNAL vcc : std_logic := '1';\r
+\r
+ signal READ_XX7_6 : std_logic;\r
+ signal RESERVE : std_logic;\r
+ signal SR_ERROR : std_logic;\r
+ signal R_ERROR : std_logic;\r
+ signal S_ERROR : std_logic;\r
+ signal WRITE_XX3_2 : std_logic;\r
+ signal WRITE_XX5_4 : std_logic;\r
+ signal WRITE_XX7_6 : std_logic;\r
+ signal READ_XX1_0 : std_logic;\r
+ signal READ_XX3_2 : std_logic;\r
+ signal INTAn : std_logic;\r
+ signal TRDYn : std_logic;\r
+ signal READ_XX5_4 : std_logic;\r
+ signal DEVSELn : std_logic;\r
+ signal FIFO_RDn : std_logic;\r
+ signal WRITE_XX1_0 : std_logic;\r
+ signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
+ signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
+ signal INT_REG : std_logic_vector (7 downto 0);\r
+ signal REVISON_ID : std_logic_vector (7 downto 0);\r
+ signal VENDOR_ID : std_logic_vector (15 downto 0);\r
+ signal READ_SEL : std_logic_vector (1 downto 0);\r
+ signal AD_REG : std_logic_vector (31 downto 0);\r
+ signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
+\r
+ component MESS_1_TB\r
+ Port ( DEVSELn : In std_logic;\r
+ INTAn : In std_logic;\r
+ KONST_1 : In std_logic;\r
+ PCI_IDSEL : In std_logic;\r
+ REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
+ TB_DEVSELn : Out std_logic;\r
+ TB_INTAn : Out std_logic;\r
+ TB_PCI_IDSEL : Out std_logic );\r
+ end component;\r
+\r
+ component VEN_REV_ID\r
+ Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
+ VEN_ID : Out std_logic_vector (15 downto 0) );\r
+ end component;\r
+\r
+ component INTERRUPT\r
+ Port ( INT_IN_0 : In std_logic;\r
+ INT_IN_1 : In std_logic;\r
+ INT_IN_2 : In std_logic;\r
+ INT_IN_3 : In std_logic;\r
+ INT_IN_4 : In std_logic;\r
+ INT_IN_5 : In std_logic;\r
+ INT_IN_6 : In std_logic;\r
+ INT_IN_7 : In std_logic;\r
+ INT_MASKE : In std_logic_vector (7 downto 0);\r
+ INT_RES : In std_logic_vector (7 downto 0);\r
+ PCI_CLOCK : In std_logic;\r
+ PCI_RSTn : In std_logic;\r
+ READ_XX5_4 : In std_logic;\r
+ RESET : In std_logic;\r
+ TAST_RESn : In std_logic;\r
+ TAST_SETn : In std_logic;\r
+ TRDYn : In std_logic;\r
+ INT_REG : Out std_logic_vector (7 downto 0);\r
+ INTAn : Out std_logic;\r
+ PCI_INTAn : Out std_logic );\r
+ end component;\r
+\r
+ component FIFO_CONTROL\r
+ Port ( FIFO_RDn : In std_logic;\r
+ FLAG_IN_0 : In std_logic;\r
+ FLAG_IN_4 : In std_logic;\r
+ HOLD : In std_logic;\r
+ KONST_1 : In std_logic;\r
+ PCI_CLOCK : In std_logic;\r
+ PSC_ENABLE : In std_logic;\r
+ R_EFn : In std_logic;\r
+ R_FFn : In std_logic;\r
+ R_HFn : In std_logic;\r
+ RESET : In std_logic;\r
+ S_EFn : In std_logic;\r
+ S_FFn : In std_logic;\r
+ S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
+ S_HFn : In std_logic;\r
+ SERIAL_IN : In std_logic;\r
+ SPC_ENABLE : In std_logic;\r
+ SPC_RDY_IN : In std_logic;\r
+ WRITE_XX1_0 : In std_logic;\r
+ R_ERROR : Out std_logic;\r
+ R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
+ R_FIFO_READn : Out std_logic;\r
+ R_FIFO_RESETn : Out std_logic;\r
+ R_FIFO_RETRANSMITn : Out std_logic;\r
+ R_FIFO_WRITEn : Out std_logic;\r
+ RESERVE : Out std_logic;\r
+ S_ERROR : Out std_logic;\r
+ S_FIFO_READn : Out std_logic;\r
+ S_FIFO_RESETn : Out std_logic;\r
+ S_FIFO_RETRANSMITn : Out std_logic;\r
+ S_FIFO_WRITEn : Out std_logic;\r
+ SERIAL_OUT : Out std_logic;\r
+ SPC_RDY_OUT : Out std_logic;\r
+ SR_ERROR : Out std_logic;\r
+ SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
+ end component;\r
+\r
+ component PCI_TOP\r
+ Port ( FLAG : In std_logic_vector (7 downto 0);\r
+ INT_REG : In std_logic_vector (7 downto 0);\r
+ PCI_CBEn : In std_logic_vector (3 downto 0);\r
+ PCI_CLOCK : In std_logic;\r
+ PCI_FRAMEn : In std_logic;\r
+ PCI_IDSEL : In std_logic;\r
+ PCI_IRDYn : In std_logic;\r
+ PCI_RSTn : In std_logic;\r
+ R_FIFO_Q : In std_logic_vector (7 downto 0);\r
+ REVISON_ID : In std_logic_vector (7 downto 0);\r
+ VENDOR_ID : In std_logic_vector (15 downto 0);\r
+ PCI_AD : InOut std_logic_vector (31 downto 0);\r
+ PCI_PAR : InOut std_logic;\r
+ AD_REG : Out std_logic_vector (31 downto 0);\r
+ DEVSELn : Out std_logic;\r
+ FIFO_RDn : Out std_logic;\r
+ PCI_DEVSELn : Out std_logic;\r
+ PCI_PERRn : Out std_logic;\r
+ PCI_SERRn : Out std_logic;\r
+ PCI_STOPn : Out std_logic;\r
+ PCI_TRDYn : Out std_logic;\r
+ READ_SEL : Out std_logic_vector (1 downto 0);\r
+ READ_XX1_0 : Out std_logic;\r
+ READ_XX3_2 : Out std_logic;\r
+ READ_XX5_4 : Out std_logic;\r
+ READ_XX7_6 : Out std_logic;\r
+ REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
+ REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
+ TRDYn : Out std_logic;\r
+ WRITE_XX1_0 : Out std_logic;\r
+ WRITE_XX3_2 : Out std_logic;\r
+ WRITE_XX5_4 : Out std_logic;\r
+ WRITE_XX7_6 : Out std_logic );\r
+ end component;\r
+\r
+begin\r
+\r
+ I19 : MESS_1_TB\r
+ Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
+ PCI_IDSEL=>PCI_IDSEL,\r
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
+ TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
+ TB_PCI_IDSEL=>TB_IDSEL );\r
+ I18 : VEN_REV_ID\r
+ Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
+ VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
+ I16 : INTERRUPT\r
+ Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
+ INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
+ INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
+ INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
+ INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
+ PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
+ READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
+ TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
+ TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
+ INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
+ I14 : FIFO_CONTROL\r
+ Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
+ FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
+ PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
+ R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
+ RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
+ S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
+ S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
+ SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
+ WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
+ R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
+ R_FIFO_READn=>R_FIFO_READn,\r
+ R_FIFO_RESETn=>R_FIFO_RESETn,\r
+ R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
+ R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
+ S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
+ S_FIFO_RESETn=>S_FIFO_RESETn,\r
+ S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
+ S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
+ SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
+ SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
+ I1 : PCI_TOP\r
+ Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
+ INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
+ PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
+ PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
+ PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
+ PCI_RSTn=>PCI_RSTn,\r
+ R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
+ REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
+ VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
+ PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
+ PCI_PAR=>PCI_PAR,\r
+ AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+ DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
+ PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
+ PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
+ PCI_TRDYn=>PCI_TRDYn,\r
+ READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
+ READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
+ READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
+ REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
+ REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
+ REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
+ TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
+ WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
+ WRITE_XX7_6=>WRITE_XX7_6 );\r
+\r
+end SCHEMATIC;\r
projects / raggedstone / blobdiff