move config space header into pci core directory
[raggedstone] / dhwk / source / fifo_io_control.vhd
index 514f0780b494a38aa02b2aed55d49e54465f9001..04c37f966002d5c47a702f2470b605cb54bb6e98 100644 (file)
--- $Id: fifo_io_control.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity FIFO_IO_CONTROL is\r
-       port\r
-       (\r
-       PCI_CLOCK                               :in     std_logic;\r
-       WRITE_XX1_0                             :in     std_logic; -- PCI Write\r
-       FIFO_RDn                                :in     std_logic; -- FIFO Read (low active)\r
-       RESET                                   :in     std_logic;\r
-       SYNC_FLAG_1                             :in     std_logic; -- Recv FIFO Empty (low active)\r
-       SYNC_FLAG_7                             :in     std_logic; -- Send FIFO Full (low active)\r
-       S_FIFO_RESETn                           :out    std_logic; -- Send FIFO Reset (low active)\r
-       R_FIFO_RESETn                           :out    std_logic; -- Recv FIFO Reset (low active)\r
-       S_FIFO_WRITEn                           :out    std_logic; -- Send FIFO Write (low active)\r
-       R_FIFO_READn                            :out    std_logic; -- Recv FIFO Read (low active)\r
-       S_FIFO_RETRANSMITn                      :out    std_logic; -- Send FIFO Retransmit (low active)\r
-       R_FIFO_RETRANSMITn                      :out    std_logic; -- Recv FIFO Retransmit (low active)\r
-       S_ERROR                                 :out    std_logic; -- Send ERROR\r
-       R_ERROR                                 :out    std_logic; -- Recv ERROR\r
-       SR_ERROR                                :out    std_logic  -- Send / Recv Error\r
-       );      \r
-end entity FIFO_IO_CONTROL;\r
-\r
-architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is\r
-\r
-signal SIG_S_ERROR     :std_logic; -- Send Error\r
-signal SIG_R_ERROR     :std_logic; -- Recv Error\r
-\r
-begin\r
-\r
--- FIFO Write\r
-\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if (PCI_CLOCK'event and PCI_CLOCK = '1')  then  \r
-                        if (RESET = '1') then\r
-                                S_FIFO_WRITEn <= '1';\r
-                                SIG_S_ERROR   <= '0';\r
-\r
-                        elsif (WRITE_XX1_0 = '0') then\r
-                                S_FIFO_WRITEn <= '1';\r
-\r
-                        elsif (WRITE_XX1_0 = '1') then\r
-                                if (SYNC_FLAG_7 = '0') then\r
-                                        SIG_S_ERROR <= '1';\r
-\r
-                                elsif (SYNC_FLAG_7 = '1') then\r
-                                        S_FIFO_WRITEn <= '0';\r
-                                        SIG_S_ERROR <= '0';\r
-                                end if;\r
-                                                                                               end if;\r
-               end if;\r
-       end process;    \r
-\r
-       S_ERROR <= SIG_S_ERROR;\r
-               \r
--- FIFO Read\r
-\r
-       R_FIFO_READn <= FIFO_RDn;       \r
-\r
--- Receive Error\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
-                if (RESET = '1') then\r
-                        SIG_R_ERROR <= '0';\r
-\r
-                elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then\r
-                        SIG_R_ERROR <= '1';\r
-                end if;\r
-        end if;\r
-end process; \r
-\r
-       R_ERROR <=      SIG_R_ERROR;            \r
-\r
--- Send or Receive Error\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
-                SR_ERROR       <= SIG_S_ERROR or SIG_R_ERROR;\r
-        end if;\r
-end process; \r
-\r
--- FIFO Reset\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
-                S_FIFO_RESETn <= not RESET;    \r
-                R_FIFO_RESETn <= not RESET;    \r
-        end if;\r
-end process;   \r
-\r
-\r
--- FIFO Retransmit\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
-                S_FIFO_RETRANSMITn <= '1';     \r
-                R_FIFO_RETRANSMITn <= '1';     \r
-        end if;\r
-end process; \r
-       \r
-end architecture FIFO_IO_CONTROL_DESIGN;\r
+-- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 08:44:31 sithglan Exp $
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FIFO_IO_CONTROL is
+        port
+        (
+                PCI_CLOCK :in std_logic;
+                WRITE_XX1_0 :in std_logic; -- PCI Write
+                FIFO_RDn :in std_logic; -- FIFO Read (low active)
+                RESET :in std_logic;
+                SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)
+                SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)
+                S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)
+                R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)
+                S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)
+                R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)
+                S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)
+                R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)
+                S_ERROR :out std_logic; -- Send ERROR
+                R_ERROR :out std_logic; -- Recv ERROR
+                SR_ERROR :out std_logic -- Send / Recv Error
+        );
+end entity FIFO_IO_CONTROL;
+
+architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is
+
+        signal SIG_S_ERROR :std_logic; -- Send Error
+        signal SIG_R_ERROR :std_logic; -- Recv Error
+
+begin
+
+ -- FIFO Write
+
+        process (PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                        if (RESET = '1') then
+                                S_FIFO_WRITEn <= '1';
+                                SIG_S_ERROR <= '0';
+
+                        elsif (WRITE_XX1_0 = '0') then
+                                S_FIFO_WRITEn <= '1';
+
+                        elsif (WRITE_XX1_0 = '1') then
+                                if (SYNC_FLAG_7 = '0') then
+                                        SIG_S_ERROR <= '1';
+
+                                elsif (SYNC_FLAG_7 = '1') then
+                                        S_FIFO_WRITEn <= '0';
+                                        SIG_S_ERROR <= '0';
+                                end if;
+                        end if;
+                end if;
+        end process;
+
+        S_ERROR <= SIG_S_ERROR;
+
+ -- FIFO Read
+
+        R_FIFO_READn <= FIFO_RDn;
+
+-- Receive Error
+
+        process (PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+                        if (RESET = '1') then
+                                SIG_R_ERROR <= '0';
+
+                        elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
+                                SIG_R_ERROR <= '1';
+                        end if;
+                end if;
+        end process;
+
+        R_ERROR <= SIG_R_ERROR;
+
+-- Send or Receive Error
+
+        process (PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+                        SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;
+                end if;
+        end process;
+
+-- FIFO Reset
+
+        process (PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+                        S_FIFO_RESETn <= not RESET;
+                        R_FIFO_RESETn <= not RESET;
+                end if;
+        end process;
+
+
+-- FIFO Retransmit
+
+        process (PCI_CLOCK)
+        begin
+                if (PCI_CLOCK'event and PCI_CLOCK ='1') then
+                        S_FIFO_RETRANSMITn <= '1';
+                        R_FIFO_RETRANSMITn <= '1';
+                end if;
+        end process;
+
+end architecture FIFO_IO_CONTROL_DESIGN;
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