MD_PAD_IO : INOUT std_logic;
MDC_PAD_O : OUT std_logic;
+ PHY_CLOCK : OUT std_logic;
+
LED_2 : OUT std_logic
);
end ethernet;
PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
end generate;
-wb_adr_i(11 downto 2) <= (others => '0');
-wb_adr_i <= wbm_adr_o (7 downto 2);
+wb_adr_i(11 downto 8) <= (others => '0');
+wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2);
wb_clk_i <= PCI_CLOCK;
+PHY_CLOCK <= PCI_CLOCK;
data(31 downto 0) <= wbm_adr_o;
data(40 downto 33) <= wbm_adr_o (7 downto 0);