all files to lowercase,

[raggedstone] / dhwk / source / user_io.vhd

diff --git a/dhwk/source/user_io.vhd b/dhwk/source/user_io.vhd
deleted file mode 100644 (file)
index d7616be..0000000
--- a/dhwk/source/user_io.vhd
+++ /dev/null
@@ -1,129 +0,0 @@
--- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007
-
-
-
-LIBRARY ieee;
-
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-entity USER_IO is
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);
-             ADDR_REG : In    std_logic_vector (31 downto 0);
-             CBE_REGn : In    std_logic_vector (3 downto 0);
-                FLAG : In    std_logic_vector (7 downto 0);
-             INT_REG : In    std_logic_vector (7 downto 0);
-             IO_WR_COM : In    std_logic;
-             IRDY_REGn : In    std_logic;
-             PCI_CLK : In    std_logic;
-             R_FIFO_Q : In    std_logic_vector (7 downto 0);
-             READ_SEL : In    std_logic_vector (1 downto 0);
-               TRDYn : In    std_logic;
-             READ_XX1_0 : Out   std_logic;
-             READ_XX3_2 : Out   std_logic;
-             READ_XX5_4 : Out   std_logic;
-             READ_XX7_6 : Out   std_logic;
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);
-             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);
-             WRITE_XX1_0 : Out   std_logic;
-             WRITE_XX3_2 : Out   std_logic;
-             WRITE_XX5_4 : Out   std_logic;
-             WRITE_XX7_6 : Out   std_logic );
-end USER_IO;
-
-architecture SCHEMATIC of USER_IO is
-
-   SIGNAL gnd : std_logic := '0';
-   SIGNAL vcc : std_logic := '1';
-
-   signal WRITE_XX1_0_DUMMY : std_logic;
-   signal WRITE_XX7_6_DUMMY : std_logic;
-   signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);
-   signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);
-   signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);
-
-   component IO_WR_SEL
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
-             CBE_REGn : In    std_logic_vector (3 downto 0);
-             IO_WR_COM : In    std_logic;
-             IRDY_REGn : In    std_logic;
-               TRDYn : In    std_logic;
-             WRITE_XX1_0 : Out   std_logic;
-             WRITE_XX3_2 : Out   std_logic;
-             WRITE_XX5_4 : Out   std_logic;
-             WRITE_XX7_6 : Out   std_logic );
-   end component;
-
-   component DATA_MUX
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
-             CBE_REGn : In    std_logic_vector (3 downto 0);
-             MUX_IN_XX0 : In    std_logic_vector (7 downto 0);
-             MUX_IN_XX1 : In    std_logic_vector (7 downto 0);
-             MUX_IN_XX2 : In    std_logic_vector (7 downto 0);
-             MUX_IN_XX3 : In    std_logic_vector (7 downto 0);
-             MUX_IN_XX4 : In    std_logic_vector (7 downto 0);
-             MUX_IN_XX5 : In    std_logic_vector (7 downto 0);
-             MUX_IN_XX6 : In    std_logic_vector (7 downto 0);
-             MUX_IN_XX7 : In    std_logic_vector (7 downto 0);
-             READ_SEL : In    std_logic_vector (1 downto 0);
-             MUX_OUT : Out   std_logic_vector (31 downto 0);
-             READ_XX1_0 : Out   std_logic;
-             READ_XX3_2 : Out   std_logic;
-             READ_XX5_4 : Out   std_logic;
-             READ_XX7_6 : Out   std_logic );
-   end component;
-
-   component REG_IO
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);
-             PCI_CLOCK : In    std_logic;
-               RESET : In    std_logic;
-             WRITE_XX1_0 : In    std_logic;
-             WRITE_XX7_6 : In    std_logic;
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );
-   end component;
-
-begin
-
-   REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
-   REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
-   REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
-   WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
-   WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
-
-   I4 : IO_WR_SEL
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
-                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
-                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
-                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
-                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
-   I2 : DATA_MUX
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
-                 MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
-                 MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
-                 MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
-                 MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
-                 MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
-                 MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
-                 MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
-                 MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
-                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
-                 MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
-                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
-                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
-   I1 : REG_IO
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
-                 PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
-                 WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
-                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
-                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
-                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
-                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );
-
-end SCHEMATIC;