-fifo_control stuff

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c0e6266ff027978c13b07d9ba352ff5594..4becb68de5b660595716589d730a2a40835bba91 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -169,7 +169,6 @@ architecture SCHEMATIC of dhwk is
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
-            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r
@@ -251,7 +250,7 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
-       trig0(7 downto 0) <= (0 => watch, others => '0');\r
+       trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r
@@ -272,6 +271,8 @@ begin
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r
+       data(26 downto 19) <= S_FIFO_Q_OUT;\r
+       data(34 downto 27) <= R_FIFO_Q_OUT;\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
@@ -313,7 +314,6 @@ begin
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
-                PAR_SER_IN(7 downto 0)=>data(26 downto 19),\r
                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
    I1 : PCI_TOP\r
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r