a bit better

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 480de0a9aa128293e2b85699971bef38ec295a42..1617eee849ab9d826f2c772d6e921d5bd7122aae 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -175,7 +175,6 @@ component phydcm is
 port ( CLKIN_IN        : in    std_logic;
        RST_IN          : in    std_logic;
        CLKFX_OUT       : out   std_logic;
-       CLKIN_IBUFG_OUT : out   std_logic;
        CLK0_OUT        : out   std_logic;
        LOCKED_OUT      : out   std_logic);
 end component;
@@ -406,10 +405,9 @@ eth_dcm : phydcm
 port map (
        CLKIN_IN => PCI_CLOCK,
        RST_IN => not PCI_RSTn,
-       CLKFX_OUT => PHY_CLOCK
---     CLKIN_IBUFG_OUT
---     CLK0_OUT
---     LOCKED_OUT
+       CLKFX_OUT => PHY_CLOCK,
+       CLK0_OUT => open,
+       LOCKED_OUT => open
        );
 
 end architecture ethernet_arch;