--- /dev/null
+--+-------------------------------------------------------------------------------------------------+\r
+--| |\r
+--| File: pci32tlite.vhd |\r
+--| |\r
+--| Components: pcidec_new.vhd |\r
+--| pciwbsequ.vhd |\r
+--| pcidmux.vhd |\r
+--| pciregs.vhd |\r
+--| pcipargen.vhd |\r
+--| -- Libs -- |\r
+--| ona.vhd |\r
+--| |\r
+--| Description: TARGET PCI : |\r
+--| |\r
+--| * PCI Target 32 Bits |\r
+--| * BAR0 32MByte address space |\r
+--| * Whisbone compatible: D16, 32MB address space |\r
+--| |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--| |\r
+--| Revision history : |\r
+--| Date Version Author Description |\r
+--| 2005-05-13 R00A00 PAU First alfa revision (eng) |\r
+--| 2006-01-05 R00B00 MS inverted reset nres |\r
+--| and added debug signals debug_init and debug_access | |\r
+--| |\r
+--| To do: |\r
+--| |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------+\r
+--| |\r
+--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | \r
+--| |\r
+--| This source file may be used and distributed without |\r
+--| restriction provided that this copyright statement is not |\r
+--| removed from the file and that any derivative work contains |\r
+--| the original copyright notice and the associated disclaimer. |\r
+--| |\r
+--| This source file is free software; you can redistribute it |\r
+--| and/or modify it under the terms of the GNU Lesser General |\r
+--| Public License as published by the Free Software Foundation; |\r
+--| either version 2.1 of the License, or (at your option) any |\r
+--| later version. |\r
+--| |\r
+--| This source is distributed in the hope that it will be |\r
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |\r
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |\r
+--| PURPOSE. See the GNU Lesser General Public License for more |\r
+--| details. |\r
+--| |\r
+--| You should have received a copy of the GNU Lesser General |\r
+--| Public License along with this source; if not, download it |\r
+--| from http://www.opencores.org/lgpl.shtml |\r
+--| |\r
+--+-----------------------------------------------------------------+ \r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| LIBRARIES |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| ENTITY |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity pci32tlite is\r
+generic (\r
+\r
+ vendorID : std_logic_vector(15 downto 0) := x"10EE";\r
+ deviceID : std_logic_vector(15 downto 0) := x"0100";\r
+ revisionID : std_logic_vector(7 downto 0) := x"37";\r
+ subsystemID : std_logic_vector(15 downto 0) := x"1558";\r
+ subsystemvID : std_logic_vector(15 downto 0) := x"0480";\r
+ jcarr1ID : std_logic_vector(31 downto 0) := x"12345671";\r
+ jcarr2ID : std_logic_vector(31 downto 0) := x"12345672";\r
+ jcarr3ID : std_logic_vector(31 downto 0) := x"12345673";\r
+ jcarr4ID : std_logic_vector(31 downto 0) := x"12345674";\r
+ jcarr5ID : std_logic_vector(31 downto 0) := x"12345675";\r
+ jcarr6ID : std_logic_vector(31 downto 0) := x"12345676";\r
+ jcarr7ID : std_logic_vector(31 downto 0) := x"12345677";\r
+ jcarr8ID : std_logic_vector(31 downto 0) := x"12345678";\r
+ jcarr9ID : std_logic_vector(31 downto 0) := x"12345679";\r
+ jcarr10ID : std_logic_vector(31 downto 0) := x"12345680";\r
+ jcarr11ID : std_logic_vector(31 downto 0) := x"12345681";\r
+ jcarr12ID : std_logic_vector(31 downto 0) := x"12345682";\r
+ jcarr13ID : std_logic_vector(31 downto 0) := x"12345683";\r
+ jcarr14ID : std_logic_vector(31 downto 0) := x"12345684";\r
+ jcarr15ID : std_logic_vector(31 downto 0) := x"12345685";\r
+ jcarr16ID : std_logic_vector(31 downto 0) := x"12345686";\r
+ jcarr17ID : std_logic_vector(31 downto 0) := x"12345687";\r
+ jcarr18ID : std_logic_vector(31 downto 0) := x"12345688";\r
+ jcarr19ID : std_logic_vector(31 downto 0) := x"12345689";\r
+ jcarr20ID : std_logic_vector(31 downto 0) := x"12345690";\r
+ jcarr21ID : std_logic_vector(31 downto 0) := x"12345691";\r
+ jcarr22ID : std_logic_vector(31 downto 0) := x"12345692";\r
+ jcarr23ID : std_logic_vector(31 downto 0) := x"12345693";\r
+ jcarr24ID : std_logic_vector(31 downto 0) := x"12345694";\r
+ jcarr25ID : std_logic_vector(31 downto 0) := x"12345695";\r
+ jcarr26ID : std_logic_vector(31 downto 0) := x"12345696";\r
+ jcarr27ID : std_logic_vector(31 downto 0) := x"12345697";\r
+ jcarr28ID : std_logic_vector(31 downto 0) := x"12345698";\r
+ jcarr29ID : std_logic_vector(31 downto 0) := x"12345699";\r
+ jcarr30ID : std_logic_vector(31 downto 0) := x"12345700";\r
+ jcarr31ID : std_logic_vector(31 downto 0) := x"12345701";\r
+ jcarr32ID : std_logic_vector(31 downto 0) := x"12345702";\r
+ jcarr33ID : std_logic_vector(31 downto 0) := x"12345703";\r
+ jcarr34ID : std_logic_vector(31 downto 0) := x"12345704";\r
+ jcarr35ID : std_logic_vector(31 downto 0) := x"12345705";\r
+ jcarr36ID : std_logic_vector(31 downto 0) := x"12345706";\r
+ jcarr37ID : std_logic_vector(31 downto 0) := x"12345707";\r
+ jcarr38ID : std_logic_vector(31 downto 0) := x"12345708";\r
+ jcarr39ID : std_logic_vector(31 downto 0) := x"12345709";\r
+ jcarr40ID : std_logic_vector(31 downto 0) := x"12345710";\r
+ jcarr41ID : std_logic_vector(31 downto 0) := x"12345711";\r
+ jcarr42ID : std_logic_vector(31 downto 0) := x"12345712"\r
+\r
+);\r
+port (\r
+\r
+ -- General \r
+ clk33 : in std_logic;\r
+ nrst : in std_logic;\r
+ \r
+ -- PCI target 32bits\r
+ ad : inout std_logic_vector(31 downto 0);\r
+ cbe : in std_logic_vector(3 downto 0);\r
+ par : out std_logic; \r
+ frame : in std_logic;\r
+ irdy : in std_logic;\r
+ trdy : out std_logic;\r
+ devsel : out std_logic;\r
+ stop : out std_logic;\r
+ idsel : in std_logic;\r
+ perr : out std_logic;\r
+ serr : out std_logic;\r
+ intb : out std_logic;\r
+ \r
+ -- Master whisbone\r
+ wb_adr_o : out std_logic_vector(24 downto 1); \r
+ wb_dat_i : in std_logic_vector(15 downto 0);\r
+ wb_dat_o : out std_logic_vector(15 downto 0);\r
+ wb_sel_o : out std_logic_vector(1 downto 0);\r
+ wb_we_o : out std_logic;\r
+ wb_stb_o : inout std_logic;\r
+ wb_cyc_o : out std_logic;\r
+ wb_ack_i : in std_logic;\r
+ wb_err_i : in std_logic;\r
+ wb_int_i : in std_logic;\r
+\r
+ -- debug signals\r
+ debug_init : out std_logic;\r
+ debug_access : out std_logic \r
+\r
+);\r
+end pci32tlite;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| ARCHITECTURE |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+architecture rtl of pci32tlite is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| COMPONENTS |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+\r
+ component pcidec_new\r
+ port (\r
+ \r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ --\r
+ ad_i : in std_logic_vector(31 downto 0);\r
+ cbe_i : in std_logic_vector(3 downto 0);\r
+ idsel_i : in std_logic;\r
+ bar0_i : in std_logic_vector(31 downto 25);\r
+ memEN_i : in std_logic;\r
+ pciadrLD_i : in std_logic;\r
+ adrcfg_o : out std_logic;\r
+ adrmem_o : out std_logic;\r
+ adr_o : out std_logic_vector(24 downto 1);\r
+ cmd_o : out std_logic_vector(3 downto 0)\r
+ \r
+ );\r
+ end component;\r
+\r
+ \r
+ component pciwbsequ\r
+ port (\r
+ \r
+ -- General \r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ -- pci \r
+ cmd_i : in std_logic_vector(3 downto 0);\r
+ cbe_i : in std_logic_vector(3 downto 0);\r
+ frame_i : in std_logic;\r
+ irdy_i : in std_logic;\r
+ devsel_o : out std_logic;\r
+ trdy_o : out std_logic;\r
+ -- control\r
+ adrcfg_i : in std_logic;\r
+ adrmem_i : in std_logic;\r
+ pciadrLD_o : out std_logic;\r
+ pcidOE_o : out std_logic;\r
+ parOE_o : out std_logic; \r
+ wbdatLD_o : out std_logic;\r
+ wbrgdMX_o : out std_logic;\r
+ wbd16MX_o : out std_logic;\r
+ wrcfg_o : out std_logic;\r
+ rdcfg_o : out std_logic;\r
+ -- whisbone\r
+ wb_sel_o : out std_logic_vector(1 downto 0);\r
+ wb_we_o : out std_logic;\r
+ wb_stb_o : inout std_logic; \r
+ wb_cyc_o : out std_logic;\r
+ wb_ack_i : in std_logic;\r
+ wb_err_i : in std_logic; \r
+ -- debug signals\r
+ debug_init : out std_logic;\r
+ debug_access : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component pcidmux\r
+ port (\r
+ \r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ --\r
+ d_io : inout std_logic_vector(31 downto 0);\r
+ pcidatout_o : out std_logic_vector(31 downto 0);\r
+ pcidOE_i : in std_logic;\r
+ wbdatLD_i : in std_logic;\r
+ wbrgdMX_i : in std_logic;\r
+ wbd16MX_i : in std_logic;\r
+ wb_dat_i : in std_logic_vector(15 downto 0);\r
+ wb_dat_o : out std_logic_vector(15 downto 0);\r
+ rg_dat_i : in std_logic_vector(31 downto 0);\r
+ rg_dat_o : out std_logic_vector(31 downto 0)\r
+ \r
+ );\r
+ end component;\r
+\r
+\r
+ component pciregs\r
+ generic (\r
+\r
+ vendorID : std_logic_vector(15 downto 0);\r
+ deviceID : std_logic_vector(15 downto 0);\r
+ revisionID : std_logic_vector(7 downto 0);\r
+ subsystemID : std_logic_vector(15 downto 0);\r
+ subsystemvID : std_logic_vector(15 downto 0);\r
+ jcarr1ID : std_logic_vector(31 downto 0);\r
+ jcarr2ID : std_logic_vector(31 downto 0);\r
+ jcarr3ID : std_logic_vector(31 downto 0);\r
+ jcarr4ID : std_logic_vector(31 downto 0);\r
+ jcarr5ID : std_logic_vector(31 downto 0);\r
+ jcarr6ID : std_logic_vector(31 downto 0);\r
+ jcarr7ID : std_logic_vector(31 downto 0);\r
+ jcarr8ID : std_logic_vector(31 downto 0);\r
+ jcarr9ID : std_logic_vector(31 downto 0);\r
+ jcarr10ID : std_logic_vector(31 downto 0);\r
+ jcarr11ID : std_logic_vector(31 downto 0);\r
+ jcarr12ID : std_logic_vector(31 downto 0);\r
+ jcarr13ID : std_logic_vector(31 downto 0);\r
+ jcarr14ID : std_logic_vector(31 downto 0);\r
+ jcarr15ID : std_logic_vector(31 downto 0);\r
+ jcarr16ID : std_logic_vector(31 downto 0);\r
+ jcarr17ID : std_logic_vector(31 downto 0);\r
+ jcarr18ID : std_logic_vector(31 downto 0);\r
+ jcarr19ID : std_logic_vector(31 downto 0);\r
+ jcarr20ID : std_logic_vector(31 downto 0);\r
+ jcarr21ID : std_logic_vector(31 downto 0);\r
+ jcarr22ID : std_logic_vector(31 downto 0);\r
+ jcarr23ID : std_logic_vector(31 downto 0);\r
+ jcarr24ID : std_logic_vector(31 downto 0);\r
+ jcarr25ID : std_logic_vector(31 downto 0);\r
+ jcarr26ID : std_logic_vector(31 downto 0);\r
+ jcarr27ID : std_logic_vector(31 downto 0);\r
+ jcarr28ID : std_logic_vector(31 downto 0);\r
+ jcarr29ID : std_logic_vector(31 downto 0);\r
+ jcarr30ID : std_logic_vector(31 downto 0);\r
+ jcarr31ID : std_logic_vector(31 downto 0);\r
+ jcarr32ID : std_logic_vector(31 downto 0);\r
+ jcarr33ID : std_logic_vector(31 downto 0);\r
+ jcarr34ID : std_logic_vector(31 downto 0);\r
+ jcarr35ID : std_logic_vector(31 downto 0);\r
+ jcarr36ID : std_logic_vector(31 downto 0);\r
+ jcarr37ID : std_logic_vector(31 downto 0);\r
+ jcarr38ID : std_logic_vector(31 downto 0);\r
+ jcarr39ID : std_logic_vector(31 downto 0);\r
+ jcarr40ID : std_logic_vector(31 downto 0);\r
+ jcarr41ID : std_logic_vector(31 downto 0);\r
+ jcarr42ID : std_logic_vector(31 downto 0)\r
+\r
+ );\r
+ port (\r
+ \r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ --\r
+ adr_i : in std_logic_vector(7 downto 2);\r
+ cbe_i : in std_logic_vector(3 downto 0);\r
+ dat_i : in std_logic_vector(31 downto 0);\r
+ dat_o : out std_logic_vector(31 downto 0);\r
+ wrcfg_i : in std_logic;\r
+ rdcfg_i : in std_logic;\r
+ perr_i : in std_logic;\r
+ serr_i : in std_logic;\r
+ tabort_i : in std_logic;\r
+ bar0_o : out std_logic_vector(31 downto 25);\r
+ perrEN_o : out std_logic;\r
+ serrEN_o : out std_logic;\r
+ memEN_o : out std_logic\r
+ \r
+ );\r
+ end component;\r
+\r
+\r
+ component pcipargen\r
+ port (\r
+\r
+ clk_i : in std_logic;\r
+ pcidatout_i : in std_logic_vector(31 downto 0);\r
+ cbe_i : in std_logic_vector(3 downto 0);\r
+ parOE_i : in std_logic;\r
+ par_o : out std_logic\r
+ \r
+ ); \r
+ end component;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| CONSTANTS |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--| SIGNALS |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+ signal bar0 : std_logic_vector(31 downto 25);\r
+ signal memEN : std_logic;\r
+ signal pciadrLD : std_logic;\r
+ signal adrcfg : std_logic;\r
+ signal adrmem : std_logic;\r
+ signal adr : std_logic_vector(24 downto 1);\r
+ signal cmd : std_logic_vector(3 downto 0);\r
+ signal pcidOE : std_logic;\r
+ signal parOE : std_logic; \r
+ signal wbdatLD : std_logic;\r
+ signal wbrgdMX : std_logic;\r
+ signal wbd16MX : std_logic;\r
+ signal wrcfg : std_logic;\r
+ signal rdcfg : std_logic;\r
+ signal pcidatread : std_logic_vector(31 downto 0);\r
+ signal pcidatwrite : std_logic_vector(31 downto 0);\r
+ signal pcidatout : std_logic_vector(31 downto 0); \r
+ signal parerr : std_logic;\r
+ signal syserr : std_logic;\r
+ signal tabort : std_logic;\r
+ signal perrEN : std_logic;\r
+ signal serrEN : std_logic;\r
+ \r
+begin\r
+\r
+\r
+ --+-------------------------------------------------------------------------+\r
+ --| Component instances |\r
+ --+-------------------------------------------------------------------------+\r
+\r
+ --+-----------------------------------------+\r
+ --| PCI decoder |\r
+ --+-----------------------------------------+\r
+\r
+ u1: component pcidec_new\r
+ port map (\r
+\r
+ clk_i => clk33,\r
+ nrst_i => nrst,\r
+ --\r
+ ad_i => ad,\r
+ cbe_i => cbe,\r
+ idsel_i => idsel,\r
+ bar0_i => bar0,\r
+ memEN_i => memEN,\r
+ pciadrLD_i => pciadrLD, \r
+ adrcfg_o => adrcfg,\r
+ adrmem_o => adrmem,\r
+ adr_o => adr,\r
+ cmd_o => cmd\r
+ \r
+ );\r
+\r
+\r
+ --+-----------------------------------------+\r
+ --| PCI-WB Sequencer |\r
+ --+-----------------------------------------+\r
+\r
+ u2: component pciwbsequ \r
+ port map (\r
+\r
+ -- General \r
+ clk_i => clk33, \r
+ nrst_i => nrst,\r
+ -- pci \r
+ cmd_i => cmd,\r
+ cbe_i => cbe,\r
+ frame_i => frame,\r
+ irdy_i => irdy, \r
+ devsel_o => devsel,\r
+ trdy_o => trdy, \r
+ -- control\r
+ adrcfg_i => adrcfg,\r
+ adrmem_i => adrmem,\r
+ pciadrLD_o => pciadrLD,\r
+ pcidOE_o => pcidOE,\r
+ parOE_o => parOE, \r
+ wbdatLD_o => wbdatLD,\r
+ wbrgdMX_o => wbrgdMX,\r
+ wbd16MX_o => wbd16MX,\r
+ wrcfg_o => wrcfg,\r
+ rdcfg_o => rdcfg,\r
+ -- whisbone\r
+ wb_sel_o => wb_sel_o,\r
+ wb_we_o => wb_we_o,\r
+ wb_stb_o => wb_stb_o,\r
+ wb_cyc_o => wb_cyc_o,\r
+ wb_ack_i => wb_ack_i,\r
+ wb_err_i => wb_err_i,\r
+ -- debug signals\r
+ debug_init => debug_init, \r
+ debug_access => debug_access\r
+ );\r
+ \r
+\r
+ --+-----------------------------------------+\r
+ --| PCI-wb datamultiplexer |\r
+ --+-----------------------------------------+\r
+\r
+ u3: component pcidmux\r
+ port map (\r
+\r
+ clk_i => clk33,\r
+ nrst_i => nrst,\r
+ --\r
+ d_io => ad, \r
+ pcidatout_o => pcidatout, \r
+ pcidOE_i => pcidOE,\r
+ wbdatLD_i => wbdatLD,\r
+ wbrgdMX_i => wbrgdMX,\r
+ wbd16MX_i => wbd16MX,\r
+ wb_dat_i => wb_dat_i,\r
+ wb_dat_o => wb_dat_o,\r
+ rg_dat_i => pcidatread,\r
+ rg_dat_o => pcidatwrite\r
+ \r
+ );\r
+\r
+\r
+ --+-----------------------------------------+\r
+ --| PCI registers |\r
+ --+-----------------------------------------+\r
+\r
+ u4: component pciregs\r
+ generic map (\r
+\r
+ vendorID => vendorID,\r
+ deviceID => deviceID,\r
+ revisionID => revisionID,\r
+ subsystemID => subsystemID,\r
+ subsystemvID => subsystemvID,\r
+ jcarr1ID => jcarr1ID,\r
+ jcarr2ID => jcarr2ID,\r
+ jcarr3ID => jcarr3ID,\r
+ jcarr4ID => jcarr4ID,\r
+ jcarr5ID => jcarr5ID,\r
+ jcarr6ID => jcarr6ID,\r
+ jcarr7ID => jcarr7ID,\r
+ jcarr8ID => jcarr8ID,\r
+ jcarr9ID => jcarr9ID,\r
+ jcarr10ID => jcarr10ID,\r
+ jcarr11ID => jcarr11ID,\r
+ jcarr12ID => jcarr12ID,\r
+ jcarr13ID => jcarr13ID,\r
+ jcarr14ID => jcarr14ID,\r
+ jcarr15ID => jcarr15ID,\r
+ jcarr16ID => jcarr16ID,\r
+ jcarr17ID => jcarr17ID,\r
+ jcarr18ID => jcarr18ID,\r
+ jcarr19ID => jcarr19ID,\r
+ jcarr20ID => jcarr20ID,\r
+ jcarr21ID => jcarr21ID,\r
+ jcarr22ID => jcarr22ID,\r
+ jcarr23ID => jcarr23ID,\r
+ jcarr24ID => jcarr24ID,\r
+ jcarr25ID => jcarr25ID,\r
+ jcarr26ID => jcarr26ID,\r
+ jcarr27ID => jcarr27ID,\r
+ jcarr28ID => jcarr28ID,\r
+ jcarr29ID => jcarr29ID,\r
+ jcarr30ID => jcarr30ID,\r
+ jcarr31ID => jcarr31ID,\r
+ jcarr32ID => jcarr32ID,\r
+ jcarr33ID => jcarr33ID,\r
+ jcarr34ID => jcarr34ID,\r
+ jcarr35ID => jcarr35ID,\r
+ jcarr36ID => jcarr36ID,\r
+ jcarr37ID => jcarr37ID,\r
+ jcarr38ID => jcarr38ID,\r
+ jcarr39ID => jcarr39ID,\r
+ jcarr40ID => jcarr40ID,\r
+ jcarr41ID => jcarr41ID,\r
+ jcarr42ID => jcarr42ID\r
+\r
+ )\r
+ port map (\r
+\r
+ clk_i => clk33,\r
+ nrst_i => nrst,\r
+ --\r
+ adr_i => adr(7 downto 2),\r
+ cbe_i => cbe,\r
+ dat_i => pcidatwrite,\r
+ dat_o => pcidatread,\r
+ wrcfg_i => wrcfg,\r
+ rdcfg_i => rdcfg,\r
+ perr_i => parerr,\r
+ serr_i => syserr,\r
+ tabort_i => tabort,\r
+ bar0_o => bar0,\r
+ perrEN_o => perrEN,\r
+ serrEN_o => serrEN,\r
+ memEN_o => memEN\r
+ \r
+ );\r
+ \r
+ --+-----------------------------------------+\r
+ --| PCI Parity Gnerator |\r
+ --+-----------------------------------------+\r
+\r
+ u5: component pcipargen\r
+ port map (\r
+\r
+ clk_i => clk33,\r
+ pcidatout_i => pcidatout, \r
+ cbe_i => cbe,\r
+ parOE_i => parOE, \r
+ par_o => par\r
+ \r
+ );\r
+\r
+\r
+ --+-----------------------------------------+\r
+ --| Whisbone Address bus |\r
+ --+-----------------------------------------+\r
+ \r
+ wb_adr_o <= adr;\r
+\r
+\r
+ --+-----------------------------------------+\r
+ --| unimplemented |\r
+ --+-----------------------------------------+\r
+\r
+ parerr <= '0';\r
+ syserr <= '0';\r
+ tabort <= '0';\r
+\r
+\r
+ --+-----------------------------------------+\r
+ --| unused outputs |\r
+ --+-----------------------------------------+\r
+ -- #stop: Curret TARGET indicates to Master stop current transaction\r
+ -- #perr:\r
+ -- #serr:\r
+ \r
+ perr <= 'Z';\r
+ serr <= 'Z';\r
+ stop <= 'Z';\r
+ intb <= '0' when ( wb_int_i = '1' ) else 'Z';\r
+\r
+ \r
+end rtl;\r
+\r
+\r
projects / raggedstone / blobdiff