dhwk
authorsithglan <sithglan>
Sun, 11 Feb 2007 21:57:15 +0000 (21:57 +0000)
committersithglan <sithglan>
Sun, 11 Feb 2007 21:57:15 +0000 (21:57 +0000)
22 files changed:
dhwk_old/Makefile [new file with mode: 0644]
dhwk_old/dhwk.prj [new file with mode: 0644]
dhwk_old/dhwk.ucf [new file with mode: 0644]
dhwk_old/dhwk.ut [new file with mode: 0644]
dhwk_old/dhwk.xst [new file with mode: 0644]
dhwk_old/source/disp_dec.v [new file with mode: 0644]
dhwk_old/source/heartbeat.vhd [new file with mode: 0644]
dhwk_old/source/new_pci32tlite.vhd [new file with mode: 0644]
dhwk_old/source/new_pciregs.vhd [new file with mode: 0644]
dhwk_old/source/pcidec.v [new file with mode: 0644]
dhwk_old/source/pcidmux.v [new file with mode: 0644]
dhwk_old/source/pcipargen.v [new file with mode: 0644]
dhwk_old/source/pcipargen.vhd [new file with mode: 0644]
dhwk_old/source/pciwbsequ.v [new file with mode: 0644]
dhwk_old/source/pciwbsequ.vhd [new file with mode: 0644]
dhwk_old/source/pfs.v [new file with mode: 0644]
dhwk_old/source/pfs.vhd [new file with mode: 0644]
dhwk_old/source/sync.v [new file with mode: 0644]
dhwk_old/source/test.v [new file with mode: 0644]
dhwk_old/source/top_dhwk.vhd [new file with mode: 0644]
dhwk_old/source/vga_main.vhd [new file with mode: 0644]
dhwk_old/source/wb_7seg.v [new file with mode: 0644]

diff --git a/dhwk_old/Makefile b/dhwk_old/Makefile
new file mode 100644 (file)
index 0000000..b3cd515
--- /dev/null
@@ -0,0 +1,3 @@
+PROJECT := dhwk
+
+include ../common/Makefile.common
diff --git a/dhwk_old/dhwk.prj b/dhwk_old/dhwk.prj
new file mode 100644 (file)
index 0000000..148efef
--- /dev/null
@@ -0,0 +1,14 @@
+verilog work "source/sync.v"
+verilog work "source/pcidec.v"
+verilog work "source/pcidmux.v"
+
+verilog work "source/pciwbsequ.v"
+verilog work "source/pcipargen.v"
+
+vhdl work "source/pciwbsequ.vhd"
+vhdl work "source/pfs.vhd"
+vhdl work "source/new_pciregs.vhd"
+vhdl work "source/pcipargen.vhd"
+vhdl work "source/new_pci32tlite.vhd"
+vhdl work "source/top_dhwk.vhd"
+vhdl work "source/heartbeat.vhd"
diff --git a/dhwk_old/dhwk.ucf b/dhwk_old/dhwk.ucf
new file mode 100644 (file)
index 0000000..9f9ac54
--- /dev/null
@@ -0,0 +1,52 @@
+NET "LED2"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
+NET "LED3"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
+NET "PCI_AD<0>"  LOC = "A5" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<10>"  LOC = "E9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<11>"  LOC = "F11" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<12>"  LOC = "E10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<13>"  LOC = "A8" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<14>"  LOC = "B9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<15>"  LOC = "B10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<16>"  LOC = "F17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<17>"  LOC = "F16" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<18>"  LOC = "A14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<19>"  LOC = "B14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<1>"  LOC = "B5" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<20>"  LOC = "B15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<21>"  LOC = "A15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<22>"  LOC = "F12" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<23>"  LOC = "F13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<24>"  LOC = "D15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<25>"  LOC = "E15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<26>"  LOC = "D17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<27>"  LOC = "C17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<28>"  LOC = "B17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<29>"  LOC = "E17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<2>"  LOC = "E6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<30>"  LOC = "A18" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<31>"  LOC = "B18" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<3>"  LOC = "D6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<4>"  LOC = "C6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<5>"  LOC = "B6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<6>"  LOC = "D7" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<7>"  LOC = "E7" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<8>"  LOC = "B8" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<9>"  LOC = "F10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<0>"  LOC = "F9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<1>"  LOC = "C10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<2>"  LOC = "D13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<3>"  LOC = "E13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CLK"  LOC = "A11" | IOSTANDARD = PCI33_3 ;
+NET "PCI_IDSEL"  LOC = "D14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nDEVSEL"  LOC = "E12" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nFRAME"  LOC = "C13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nINT"  LOC = "B19" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nIRDY"  LOC = "A13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nPERR"  LOC = "D12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nRES"  LOC = "A19" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nSERR"  LOC = "B12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nSTOP"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "LED5"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
+NET "LED4"  LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
diff --git a/dhwk_old/dhwk.ut b/dhwk_old/dhwk.ut
new file mode 100644 (file)
index 0000000..1a6b102
--- /dev/null
@@ -0,0 +1,27 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullUp
+-g UserID:0xFFFFFFFF
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/dhwk_old/dhwk.xst b/dhwk_old/dhwk.xst
new file mode 100644 (file)
index 0000000..9a47866
--- /dev/null
@@ -0,0 +1,51 @@
+set -xsthdpdir ./xst
+run
+-ifn dhwk.prj
+-ifmt mixed
+-ofn dhwk
+-ofmt NGC
+-p xc3s1500-fg456-4
+-top dhwk
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso dhwk.lso
+-keep_hierarchy NO
+-glob_opt AllClockNets
+-rtlview Yes
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-mux_extract YES
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-resource_sharing YES
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-equivalent_register_removal YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-slice_utilization_ratio_maxmargin 5
diff --git a/dhwk_old/source/disp_dec.v b/dhwk_old/source/disp_dec.v
new file mode 100644 (file)
index 0000000..d674d72
--- /dev/null
@@ -0,0 +1,29 @@
+module disp_dec(disp_dec_in, disp_dec_out);\r
+       input [3:0] disp_dec_in;\r
+       output reg [6:0] disp_dec_out;\r
+\r
+       always @(disp_dec_in)\r
+       begin\r
+               case (disp_dec_in)\r
+                       4'b0000: disp_dec_out <= 7'b1000000;\r
+                       4'b0001: disp_dec_out <= 7'b1111001;\r
+                       4'b0010: disp_dec_out <= 7'b0100100;\r
+                       4'b0011: disp_dec_out <= 7'b0110000;\r
+\r
+                       4'b0100: disp_dec_out <= 7'b0011001;\r
+                       4'b0101: disp_dec_out <= 7'b0010010;\r
+                       4'b0110: disp_dec_out <= 7'b0000010;\r
+                       4'b0111: disp_dec_out <= 7'b1111000;\r
+\r
+                       4'b1000: disp_dec_out <= 7'b0000000;\r
+                       4'b1001: disp_dec_out <= 7'b0010000;\r
+                       4'b1010: disp_dec_out <= 7'b0001000;\r
+                       4'b1011: disp_dec_out <= 7'b0000011;\r
+\r
+                       4'b1100: disp_dec_out <= 7'b1000110;\r
+                       4'b1101: disp_dec_out <= 7'b0100001;\r
+                       4'b1110: disp_dec_out <= 7'b0000110;\r
+                       4'b1111: disp_dec_out <= 7'b0001110;\r
+               endcase\r
+       end\r
+endmodule\r
diff --git a/dhwk_old/source/heartbeat.vhd b/dhwk_old/source/heartbeat.vhd
new file mode 100644 (file)
index 0000000..e079bbb
--- /dev/null
@@ -0,0 +1,46 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity heartbeat is
+generic (
+       divider : std_logic_vector(31 downto 0) := X"01F78A40"
+);
+
+port (
+       clk_i : in std_logic;
+       nrst_i : in std_logic;
+       led2_o : out std_logic;
+       led3_o : out std_logic;
+       led4_o : out std_logic;
+       led5_o : out std_logic
+);   
+
+end heartbeat;
+
+architecture rtl of heartbeat is
+begin
+
+process(clk_i, nrst_i)
+variable counter : std_logic_vector(31 downto 0);
+variable state : std_logic := '0';
+begin
+
+if (clk_i'event AND clk_i = '1') then
+       if nrst_i = '0' then
+               counter := (others => '0');
+        else
+               led5_o <= state;
+               led2_o <= state;
+               led4_o <= not state;
+               led3_o <= not state;
+               counter := counter + 1;
+               if counter = divider then
+                       state := not state;
+                       counter := (others => '0');
+               end if;
+       end if;
+end if;
+end process;
+end architecture;
diff --git a/dhwk_old/source/new_pci32tlite.vhd b/dhwk_old/source/new_pci32tlite.vhd
new file mode 100644 (file)
index 0000000..e4c7fab
--- /dev/null
@@ -0,0 +1,590 @@
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  File:                     pci32tlite.vhd                                                                          |\r
+--|                                                                                                                                                                                                    |\r
+--|  Components:       pcidec_new.vhd                                                                                                                                          |\r
+--|                        pciwbsequ.vhd                                                                                                                       |\r
+--|                        pcidmux.vhd                                                                                                                                 |\r
+--|                        pciregs.vhd                                                                                                                                 |\r
+--|                        pcipargen.vhd                                                                                                                               |\r
+--|                        -- Libs --                                                                                                                                  |\r
+--|                        ona.vhd                                                                                                                                             |\r
+--|                                                                                                                                                                                                    |\r
+--|     Description:   TARGET PCI :                                                                                                    |\r
+--|                                                                                                                                                                                            |\r
+--|                                    * PCI Target 32 Bits                                                                                                                    |\r
+--|                                    * BAR0 32MByte address space                                                                                                    |\r
+--|                                    * Whisbone compatible: D16, 32MB address space                                  |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  Revision history :                                                                                                                                                                |\r
+--|  Date                Version       Author  Description                                                                                                             |\r
+--|  2005-05-13   R00A00       PAU             First alfa revision (eng)                                                                               |\r
+--|     2006-01-05   R00B00    MS      inverted reset nres                                                                                     |\r
+--|                                 and added debug signals debug_init and debug_access             |                                                                                                                                                                                          |\r
+--|                                                                                                                                                                                                    |\r
+--|  To do:                                                                                                                                                                                    |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------+\r
+--|                                                                                                                            |\r
+--|  Copyright (C) 2005 Peio Azkarate, peio@opencores.org              | \r
+--|                                                                                                                            |\r
+--|  This source file may be used and distributed without              |\r
+--|  restriction provided that this copyright statement is not         |\r
+--|  removed from the file and that any derivative work contains       |\r
+--|  the original copyright notice and the associated disclaimer.      |\r
+--|                                                                    |\r
+--|  This source file is free software; you can redistribute it     |\r
+--|  and/or modify it under the terms of the GNU Lesser General     |\r
+--|  Public License as published by the Free Software Foundation;   |\r
+--|  either version 2.1 of the License, or (at your option) any     |\r
+--|  later version.                                                 |\r
+--|                                                                                                                            |\r
+--|  This source is distributed in the hope that it will be         |\r
+--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |\r
+--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |\r
+--|  PURPOSE.  See the GNU Lesser General Public License for more   |\r
+--|  details.                                                       |\r
+--|                                                                                                                            |\r
+--|  You should have received a copy of the GNU Lesser General      |\r
+--|  Public License along with this source; if not, download it     |\r
+--|  from http://www.opencores.org/lgpl.shtml                       |\r
+--|                                                                                                                            |\r
+--+-----------------------------------------------------------------+ \r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    LIBRARIES                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    ENTITY                                                                          |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity pci32tlite is\r
+generic (\r
+\r
+       vendorID                : std_logic_vector(15 downto 0) := x"10EE";\r
+       deviceID                : std_logic_vector(15 downto 0) := x"0100";\r
+       revisionID              : std_logic_vector(7 downto 0)  := x"37";\r
+       subsystemID     : std_logic_vector(15 downto 0) := x"1558";\r
+       subsystemvID    : std_logic_vector(15 downto 0) := x"0480";\r
+               jcarr1ID                : std_logic_vector(31 downto 0) := x"12345671";\r
+               jcarr2ID                : std_logic_vector(31 downto 0) := x"12345672";\r
+               jcarr3ID                : std_logic_vector(31 downto 0) := x"12345673";\r
+               jcarr4ID                : std_logic_vector(31 downto 0) := x"12345674";\r
+               jcarr5ID                : std_logic_vector(31 downto 0) := x"12345675";\r
+               jcarr6ID                : std_logic_vector(31 downto 0) := x"12345676";\r
+               jcarr7ID                : std_logic_vector(31 downto 0) := x"12345677";\r
+               jcarr8ID                : std_logic_vector(31 downto 0) := x"12345678";\r
+               jcarr9ID                : std_logic_vector(31 downto 0) := x"12345679";\r
+               jcarr10ID               : std_logic_vector(31 downto 0) := x"12345680";\r
+               jcarr11ID               : std_logic_vector(31 downto 0) := x"12345681";\r
+               jcarr12ID               : std_logic_vector(31 downto 0) := x"12345682";\r
+               jcarr13ID               : std_logic_vector(31 downto 0) := x"12345683";\r
+               jcarr14ID               : std_logic_vector(31 downto 0) := x"12345684";\r
+               jcarr15ID               : std_logic_vector(31 downto 0) := x"12345685";\r
+               jcarr16ID               : std_logic_vector(31 downto 0) := x"12345686";\r
+               jcarr17ID               : std_logic_vector(31 downto 0) := x"12345687";\r
+               jcarr18ID               : std_logic_vector(31 downto 0) := x"12345688";\r
+               jcarr19ID               : std_logic_vector(31 downto 0) := x"12345689";\r
+               jcarr20ID               : std_logic_vector(31 downto 0) := x"12345690";\r
+               jcarr21ID               : std_logic_vector(31 downto 0) := x"12345691";\r
+               jcarr22ID               : std_logic_vector(31 downto 0) := x"12345692";\r
+               jcarr23ID               : std_logic_vector(31 downto 0) := x"12345693";\r
+               jcarr24ID               : std_logic_vector(31 downto 0) := x"12345694";\r
+               jcarr25ID               : std_logic_vector(31 downto 0) := x"12345695";\r
+               jcarr26ID               : std_logic_vector(31 downto 0) := x"12345696";\r
+               jcarr27ID               : std_logic_vector(31 downto 0) := x"12345697";\r
+               jcarr28ID               : std_logic_vector(31 downto 0) := x"12345698";\r
+               jcarr29ID               : std_logic_vector(31 downto 0) := x"12345699";\r
+               jcarr30ID               : std_logic_vector(31 downto 0) := x"12345700";\r
+               jcarr31ID               : std_logic_vector(31 downto 0) := x"12345701";\r
+               jcarr32ID               : std_logic_vector(31 downto 0) := x"12345702";\r
+               jcarr33ID               : std_logic_vector(31 downto 0) := x"12345703";\r
+               jcarr34ID               : std_logic_vector(31 downto 0) := x"12345704";\r
+               jcarr35ID               : std_logic_vector(31 downto 0) := x"12345705";\r
+               jcarr36ID               : std_logic_vector(31 downto 0) := x"12345706";\r
+               jcarr37ID               : std_logic_vector(31 downto 0) := x"12345707";\r
+               jcarr38ID               : std_logic_vector(31 downto 0) := x"12345708";\r
+               jcarr39ID               : std_logic_vector(31 downto 0) := x"12345709";\r
+               jcarr40ID               : std_logic_vector(31 downto 0) := x"12345710";\r
+               jcarr41ID               : std_logic_vector(31 downto 0) := x"12345711";\r
+               jcarr42ID               : std_logic_vector(31 downto 0) := x"12345712"\r
+\r
+);\r
+port (\r
+\r
+    -- General \r
+    clk33       : in std_logic;\r
+    nrst           : in std_logic;\r
+    \r
+    -- PCI target 32bits\r
+    ad          : inout std_logic_vector(31 downto 0);\r
+    cbe         : in std_logic_vector(3 downto 0);\r
+    par         : out std_logic;  \r
+    frame       : in std_logic;\r
+    irdy        : in std_logic;\r
+    trdy        : out std_logic;\r
+    devsel      : out std_logic;\r
+    stop        : out std_logic;\r
+    idsel       : in std_logic;\r
+    perr        : out std_logic;\r
+    serr        : out std_logic;\r
+    intb        : out std_logic;\r
+      \r
+       -- Master whisbone\r
+    wb_adr_o     : out std_logic_vector(24 downto 1);     \r
+       wb_dat_i     : in std_logic_vector(15 downto 0);\r
+    wb_dat_o     : out std_logic_vector(15 downto 0);\r
+       wb_sel_o     : out std_logic_vector(1 downto 0);\r
+    wb_we_o      : out std_logic;\r
+       wb_stb_o     : inout std_logic;\r
+       wb_cyc_o     : out std_logic;\r
+       wb_ack_i     : in std_logic;\r
+       wb_err_i     : in std_logic;\r
+       wb_int_i     : in std_logic;\r
+\r
+       -- debug signals\r
+       debug_init       : out std_logic;\r
+       debug_access : out std_logic \r
+\r
+);\r
+end pci32tlite;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    ARCHITECTURE                                                            |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+architecture rtl of pci32tlite is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    COMPONENTS                                                                      |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+\r
+       component pcidec_new\r
+       port (\r
+       \r
+           clk_i               : in std_logic;\r
+               nrst_i          : in std_logic;\r
+               --\r
+               ad_i                    : in std_logic_vector(31 downto 0);\r
+               cbe_i                   : in std_logic_vector(3 downto 0);\r
+               idsel_i                 : in std_logic;\r
+               bar0_i          : in std_logic_vector(31 downto 25);\r
+               memEN_i                 : in std_logic;\r
+               pciadrLD_i              : in std_logic;\r
+               adrcfg_o                : out std_logic;\r
+               adrmem_o                : out std_logic;\r
+               adr_o                   : out std_logic_vector(24 downto 1);\r
+               cmd_o                   : out std_logic_vector(3 downto 0)\r
+               \r
+       );\r
+       end component;\r
+\r
+       \r
+       component pciwbsequ\r
+       port (\r
+       \r
+               -- General \r
+           clk_i               : in std_logic;\r
+               nrst_i          : in std_logic;\r
+               -- pci \r
+               cmd_i                   : in std_logic_vector(3 downto 0);\r
+               cbe_i                   : in std_logic_vector(3 downto 0);\r
+               frame_i                 : in std_logic;\r
+               irdy_i          : in std_logic;\r
+               devsel_o                : out std_logic;\r
+               trdy_o          : out std_logic;\r
+               -- control\r
+               adrcfg_i                : in std_logic;\r
+               adrmem_i                : in std_logic;\r
+               pciadrLD_o              : out std_logic;\r
+               pcidOE_o                : out std_logic;\r
+               parOE_o                 : out std_logic;                \r
+               wbdatLD_o       : out std_logic;\r
+               wbrgdMX_o               : out std_logic;\r
+               wbd16MX_o               : out std_logic;\r
+               wrcfg_o                 : out std_logic;\r
+               rdcfg_o                 : out std_logic;\r
+               -- whisbone\r
+               wb_sel_o                : out std_logic_vector(1 downto 0);\r
+               wb_we_o                 : out std_logic;\r
+               wb_stb_o                : inout std_logic;      \r
+               wb_cyc_o                : out std_logic;\r
+               wb_ack_i                : in std_logic;\r
+               wb_err_i                : in std_logic; \r
+               -- debug signals\r
+               debug_init              : out std_logic;\r
+               debug_access    : out std_logic\r
+       );\r
+       end component;\r
+\r
+\r
+       component pcidmux\r
+       port (\r
+       \r
+           clk_i               : in std_logic;\r
+               nrst_i          : in std_logic;\r
+               --\r
+               d_io                    : inout std_logic_vector(31 downto 0);\r
+               pcidatout_o             : out std_logic_vector(31 downto 0);\r
+               pcidOE_i                : in std_logic;\r
+               wbdatLD_i               : in std_logic;\r
+               wbrgdMX_i               : in std_logic;\r
+               wbd16MX_i               : in std_logic;\r
+               wb_dat_i                : in std_logic_vector(15 downto 0);\r
+               wb_dat_o                : out std_logic_vector(15 downto 0);\r
+               rg_dat_i                : in std_logic_vector(31 downto 0);\r
+               rg_dat_o                : out std_logic_vector(31 downto 0)\r
+                               \r
+       );\r
+       end component;\r
+\r
+\r
+       component pciregs\r
+       generic (\r
+\r
+               vendorID : std_logic_vector(15 downto 0);\r
+               deviceID : std_logic_vector(15 downto 0);\r
+               revisionID : std_logic_vector(7 downto 0);\r
+               subsystemID : std_logic_vector(15 downto 0);\r
+       subsystemvID : std_logic_vector(15 downto 0);\r
+               jcarr1ID        : std_logic_vector(31 downto 0);\r
+               jcarr2ID        : std_logic_vector(31 downto 0);\r
+               jcarr3ID        : std_logic_vector(31 downto 0);\r
+               jcarr4ID        : std_logic_vector(31 downto 0);\r
+               jcarr5ID        : std_logic_vector(31 downto 0);\r
+               jcarr6ID        : std_logic_vector(31 downto 0);\r
+               jcarr7ID        : std_logic_vector(31 downto 0);\r
+               jcarr8ID        : std_logic_vector(31 downto 0);\r
+               jcarr9ID        : std_logic_vector(31 downto 0);\r
+               jcarr10ID       : std_logic_vector(31 downto 0);\r
+               jcarr11ID       : std_logic_vector(31 downto 0);\r
+               jcarr12ID       : std_logic_vector(31 downto 0);\r
+               jcarr13ID       : std_logic_vector(31 downto 0);\r
+               jcarr14ID       : std_logic_vector(31 downto 0);\r
+               jcarr15ID       : std_logic_vector(31 downto 0);\r
+               jcarr16ID       : std_logic_vector(31 downto 0);\r
+               jcarr17ID       : std_logic_vector(31 downto 0);\r
+               jcarr18ID       : std_logic_vector(31 downto 0);\r
+               jcarr19ID       : std_logic_vector(31 downto 0);\r
+               jcarr20ID       : std_logic_vector(31 downto 0);\r
+               jcarr21ID       : std_logic_vector(31 downto 0);\r
+               jcarr22ID       : std_logic_vector(31 downto 0);\r
+               jcarr23ID       : std_logic_vector(31 downto 0);\r
+               jcarr24ID       : std_logic_vector(31 downto 0);\r
+               jcarr25ID       : std_logic_vector(31 downto 0);\r
+               jcarr26ID       : std_logic_vector(31 downto 0);\r
+               jcarr27ID       : std_logic_vector(31 downto 0);\r
+               jcarr28ID       : std_logic_vector(31 downto 0);\r
+               jcarr29ID       : std_logic_vector(31 downto 0);\r
+               jcarr30ID       : std_logic_vector(31 downto 0);\r
+               jcarr31ID       : std_logic_vector(31 downto 0);\r
+               jcarr32ID       : std_logic_vector(31 downto 0);\r
+               jcarr33ID       : std_logic_vector(31 downto 0);\r
+               jcarr34ID       : std_logic_vector(31 downto 0);\r
+               jcarr35ID       : std_logic_vector(31 downto 0);\r
+               jcarr36ID       : std_logic_vector(31 downto 0);\r
+               jcarr37ID       : std_logic_vector(31 downto 0);\r
+               jcarr38ID       : std_logic_vector(31 downto 0);\r
+               jcarr39ID       : std_logic_vector(31 downto 0);\r
+               jcarr40ID       : std_logic_vector(31 downto 0);\r
+               jcarr41ID       : std_logic_vector(31 downto 0);\r
+               jcarr42ID       : std_logic_vector(31 downto 0)\r
+\r
+       );\r
+       port (\r
+       \r
+           clk_i               : in std_logic;\r
+               nrst_i          : in std_logic;\r
+               --\r
+               adr_i                   : in std_logic_vector(7 downto 2);\r
+               cbe_i                   : in std_logic_vector(3 downto 0);\r
+               dat_i                   : in std_logic_vector(31 downto 0);\r
+               dat_o                   : out std_logic_vector(31 downto 0);\r
+               wrcfg_i         : in std_logic;\r
+               rdcfg_i         : in std_logic;\r
+               perr_i          : in std_logic;\r
+               serr_i          : in std_logic;\r
+               tabort_i        : in std_logic;\r
+               bar0_o                  : out std_logic_vector(31 downto 25);\r
+               perrEN_o                : out std_logic;\r
+               serrEN_o                : out std_logic;\r
+               memEN_o                 : out std_logic\r
+                               \r
+       );\r
+       end component;\r
+\r
+\r
+       component pcipargen\r
+       port (\r
+\r
+               clk_i                   : in std_logic;\r
+               pcidatout_i             : in std_logic_vector(31 downto 0);\r
+               cbe_i                   : in std_logic_vector(3 downto 0);\r
+               parOE_i                 : in std_logic;\r
+               par_o                   : out std_logic\r
+       \r
+       );   \r
+       end component;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    CONSTANTS                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    SIGNALS                                                                         |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+       signal bar0                     : std_logic_vector(31 downto 25);\r
+       signal memEN            : std_logic;\r
+       signal pciadrLD         : std_logic;\r
+       signal adrcfg           : std_logic;\r
+       signal adrmem           : std_logic;\r
+       signal adr                      : std_logic_vector(24 downto 1);\r
+       signal cmd                      : std_logic_vector(3 downto 0);\r
+       signal pcidOE           : std_logic;\r
+       signal parOE            : std_logic;    \r
+       signal wbdatLD          : std_logic;\r
+       signal wbrgdMX          : std_logic;\r
+       signal wbd16MX          : std_logic;\r
+       signal wrcfg            : std_logic;\r
+       signal rdcfg            : std_logic;\r
+       signal pcidatread       : std_logic_vector(31 downto 0);\r
+       signal pcidatwrite      : std_logic_vector(31 downto 0);\r
+       signal pcidatout        : std_logic_vector(31 downto 0);        \r
+       signal parerr           : std_logic;\r
+       signal syserr           : std_logic;\r
+       signal tabort           : std_logic;\r
+       signal perrEN           : std_logic;\r
+       signal serrEN           : std_logic;\r
+                       \r
+begin\r
+\r
+\r
+    --+-------------------------------------------------------------------------+\r
+    --|  Component instances                                                                                                   |\r
+    --+-------------------------------------------------------------------------+\r
+\r
+       --+-----------------------------------------+\r
+       --|  PCI decoder                                                        |\r
+       --+-----------------------------------------+\r
+\r
+       u1: component pcidec_new\r
+       port map (\r
+\r
+           clk_i       => clk33,\r
+               nrst_i          => nrst,\r
+               --\r
+               ad_i            => ad,\r
+               cbe_i           => cbe,\r
+               idsel_i         => idsel,\r
+               bar0_i      => bar0,\r
+               memEN_i         => memEN,\r
+               pciadrLD_i      => pciadrLD,    \r
+               adrcfg_o        => adrcfg,\r
+               adrmem_o        => adrmem,\r
+               adr_o           => adr,\r
+               cmd_o           => cmd\r
+               \r
+       );\r
+\r
+\r
+       --+-----------------------------------------+\r
+       --|  PCI-WB Sequencer                                           |\r
+       --+-----------------------------------------+\r
+\r
+       u2: component pciwbsequ \r
+       port map (\r
+\r
+               -- General \r
+           clk_i               => clk33,       \r
+               nrst_i      => nrst,\r
+               -- pci \r
+               cmd_i                   => cmd,\r
+               cbe_i                   => cbe,\r
+               frame_i                 => frame,\r
+               irdy_i          => irdy,        \r
+               devsel_o                => devsel,\r
+               trdy_o          => trdy,        \r
+               -- control\r
+               adrcfg_i                => adrcfg,\r
+               adrmem_i                => adrmem,\r
+               pciadrLD_o              => pciadrLD,\r
+               pcidOE_o                => pcidOE,\r
+               parOE_o                 => parOE,    \r
+               wbdatLD_o       => wbdatLD,\r
+               wbrgdMX_o               => wbrgdMX,\r
+               wbd16MX_o               => wbd16MX,\r
+               wrcfg_o                 => wrcfg,\r
+               rdcfg_o                 => rdcfg,\r
+               -- whisbone\r
+               wb_sel_o                => wb_sel_o,\r
+               wb_we_o                 => wb_we_o,\r
+               wb_stb_o                => wb_stb_o,\r
+               wb_cyc_o                => wb_cyc_o,\r
+               wb_ack_i                => wb_ack_i,\r
+               wb_err_i                => wb_err_i,\r
+               -- debug signals\r
+               debug_init              => debug_init, \r
+               debug_access    => debug_access\r
+       );\r
+   \r
+\r
+       --+-----------------------------------------+\r
+       --|  PCI-wb datamultiplexer                                     |\r
+       --+-----------------------------------------+\r
+\r
+       u3: component pcidmux\r
+       port map (\r
+\r
+           clk_i       => clk33,\r
+               nrst_i          => nrst,\r
+               --\r
+               d_io            => ad,  \r
+               pcidatout_o     => pcidatout,   \r
+               pcidOE_i        => pcidOE,\r
+               wbdatLD_i       => wbdatLD,\r
+               wbrgdMX_i       => wbrgdMX,\r
+               wbd16MX_i       => wbd16MX,\r
+               wb_dat_i        => wb_dat_i,\r
+               wb_dat_o        => wb_dat_o,\r
+               rg_dat_i        => pcidatread,\r
+               rg_dat_o        => pcidatwrite\r
+                       \r
+       );\r
+\r
+\r
+       --+-----------------------------------------+\r
+       --|  PCI registers                                                      |\r
+       --+-----------------------------------------+\r
+\r
+       u4: component pciregs\r
+       generic map (\r
+\r
+               vendorID                => vendorID,\r
+               deviceID                => deviceID,\r
+               revisionID              => revisionID,\r
+               subsystemID     => subsystemID,\r
+       subsystemvID    => subsystemvID,\r
+               jcarr1ID        => jcarr1ID,\r
+               jcarr2ID        => jcarr2ID,\r
+               jcarr3ID        => jcarr3ID,\r
+               jcarr4ID        => jcarr4ID,\r
+               jcarr5ID        => jcarr5ID,\r
+               jcarr6ID        => jcarr6ID,\r
+               jcarr7ID        => jcarr7ID,\r
+               jcarr8ID        => jcarr8ID,\r
+               jcarr9ID        => jcarr9ID,\r
+               jcarr10ID       => jcarr10ID,\r
+               jcarr11ID       => jcarr11ID,\r
+               jcarr12ID       => jcarr12ID,\r
+               jcarr13ID       => jcarr13ID,\r
+               jcarr14ID       => jcarr14ID,\r
+               jcarr15ID       => jcarr15ID,\r
+               jcarr16ID       => jcarr16ID,\r
+               jcarr17ID       => jcarr17ID,\r
+               jcarr18ID       => jcarr18ID,\r
+               jcarr19ID       => jcarr19ID,\r
+               jcarr20ID       => jcarr20ID,\r
+               jcarr21ID       => jcarr21ID,\r
+               jcarr22ID       => jcarr22ID,\r
+               jcarr23ID       => jcarr23ID,\r
+               jcarr24ID       => jcarr24ID,\r
+               jcarr25ID       => jcarr25ID,\r
+               jcarr26ID       => jcarr26ID,\r
+               jcarr27ID       => jcarr27ID,\r
+               jcarr28ID       => jcarr28ID,\r
+               jcarr29ID       => jcarr29ID,\r
+               jcarr30ID       => jcarr30ID,\r
+               jcarr31ID       => jcarr31ID,\r
+               jcarr32ID       => jcarr32ID,\r
+               jcarr33ID       => jcarr33ID,\r
+               jcarr34ID       => jcarr34ID,\r
+               jcarr35ID       => jcarr35ID,\r
+               jcarr36ID       => jcarr36ID,\r
+               jcarr37ID       => jcarr37ID,\r
+               jcarr38ID       => jcarr38ID,\r
+               jcarr39ID       => jcarr39ID,\r
+               jcarr40ID       => jcarr40ID,\r
+               jcarr41ID       => jcarr41ID,\r
+               jcarr42ID       => jcarr42ID\r
+\r
+       )\r
+       port map (\r
+\r
+           clk_i       => clk33,\r
+               nrst_i          => nrst,\r
+               --\r
+               adr_i           => adr(7 downto 2),\r
+               cbe_i           => cbe,\r
+               dat_i           => pcidatwrite,\r
+               dat_o           => pcidatread,\r
+               wrcfg_i     => wrcfg,\r
+               rdcfg_i     => rdcfg,\r
+               perr_i      => parerr,\r
+               serr_i      => syserr,\r
+               tabort_i    => tabort,\r
+               bar0_o          => bar0,\r
+               perrEN_o        => perrEN,\r
+               serrEN_o        => serrEN,\r
+               memEN_o         => memEN\r
+                                       \r
+       );\r
+       \r
+       --+-----------------------------------------+\r
+       --|  PCI Parity Gnerator                                        |\r
+       --+-----------------------------------------+\r
+\r
+       u5: component pcipargen\r
+       port map (\r
+\r
+           clk_i       => clk33,\r
+               pcidatout_i     => pcidatout,   \r
+               cbe_i           => cbe,\r
+               parOE_i         => parOE,       \r
+               par_o           => par\r
+                                       \r
+       );\r
+\r
+\r
+       --+-----------------------------------------+\r
+       --|  Whisbone Address bus                                       |\r
+       --+-----------------------------------------+\r
+       \r
+       wb_adr_o <= adr;\r
+\r
+\r
+       --+-----------------------------------------+\r
+       --|  unimplemented                                                      |\r
+       --+-----------------------------------------+\r
+\r
+       parerr  <= '0';\r
+       syserr  <= '0';\r
+       tabort  <= '0';\r
+\r
+\r
+       --+-----------------------------------------+\r
+       --|  unused outputs                                                     |\r
+       --+-----------------------------------------+\r
+       -- #stop: Curret TARGET indicates to Master stop current transaction\r
+       -- #perr:\r
+       -- #serr:\r
+       \r
+       perr    <= 'Z';\r
+       serr    <= 'Z';\r
+       stop    <= 'Z';\r
+       intb    <= '0' when ( wb_int_i = '1' ) else 'Z';\r
+\r
+               \r
+end rtl;\r
+\r
+\r
diff --git a/dhwk_old/source/new_pciregs.vhd b/dhwk_old/source/new_pciregs.vhd
new file mode 100644 (file)
index 0000000..4adb7ac
--- /dev/null
@@ -0,0 +1,675 @@
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  File:                     pciregs.vhd                                                                             |\r
+--|                                                                                                                                                                                                    |\r
+--|  Project:          pci32tlite_oc                                                                                                                                   |\r
+--|                                                                                                                                                                                                    |\r
+--|  Description:      Registros PCI                                                                                                                                   |\r
+--|                                    BAR0 is used externally by decoder.                                                                                             |\r
+--|                                                                                                                                                                                                    |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|    |       PCI CONFIGURATION SPACE REGISTERS                                                                       |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                                    |\r
+--| +-------------------------------------------------------------------+                                                      |\r
+--| |   REGISTER       |       adr(7..2)       |       offset  | Byte Enable   | Size  |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  VENDORID                |  000000 (r)   |     00        |          0/1          |       2       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  DERVICEID       |  000000 (r)   |         02    |          2/3          |   2   |                                                       |\r
+--| +-------------------------------------------------------------------+                                                      |\r
+--| |  CMD                     |  000001 (r/w) |         04    |          0/1          |       2       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  ST                      |  000001 (r/w*)|         06    |          2/3          |   2   |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  REVISIONID      |  000010 (r)   |         08    |           0           |       1       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  CLASSCODE       |  000010 (r)   |         09    |         1/2/3         |   3   |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  HEADERTYPE      |  000011 (r)   |         0E    |           2           |       1       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  BAR0                    |  000100 (r/w) |         10    |        0/1/2/3        |       4       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  SUBSYSTEMID     |  001011 (r)   |     2C        |          0/1          |       2       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  SUBSYSTEMVID    |  001011 (r)   |         2E    |          0/1          |   2   |                                                       |\r
+--| +-------------------------------------------------------------------+                                                      |\r
+--| |  INTLINE         |  001111 (r/w) |         3C    |           0           |       1       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--| |  INTPIN          |  001111 (r)   |         3D    |           1           |       1       |                                                       |\r
+--| +-------------------------------------------------------------------+                                              |\r
+--|  (w*) Reseteable                                                                                                                                                           |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | VENDORID (r) Vendor ID register                               |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Identifies manufacturer of device.                                                                    |                                               |\r
+--| | VENDORIDr : vendorID (generic)                                                                           |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | DEVICEID (r) Device ID register                       |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Identifies the device.                                                                                                |                                               |\r
+--| | DEVICEIDr : deviceID (generic)                                                                           |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | CMD (r/w) CoMmanD register                            |                                                                                               |\r
+--|    +-----------------------------------------------+----------------------------+                                  |\r
+--|    |    0    |    0   |   0    |    0   |   0    |    0    |     0     | SERRENb| (15-8)                   |\r
+--|    +----------------------------------------------------------------------------+                                  |\r
+--|    |    0    | PERRENb|   0        |        0       |       0        |    0    |MEMSPACEENb|   0    |  (7-0)                       |\r
+--|    +----------------------------------------------------------------------------+                                  |\r
+--|    | SERRENb : System ERRor ENable (1 = Enabled)                                                   |                                               |\r
+--|    | PERRENb : Parity ERRor ENable (1 = Enabled)                                                   |                                               |\r
+--|    | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled)                                              |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | ST (r/w*) STatus register                                             |                                                                                               |\r
+--|    +-----------------------------------------------+-------------------------+                                             |\r
+--|    | PERRDTb | SERRSIb|   --   |   --   |TABORTSIb| DEVSELTIMb(1..0)|   --   | (15-8)                              |\r
+--|    +-------------------------------------------------------------------------+                                             |\r
+--|    |    --   |   --   |   --       |       --       |       --        |   --   |   --   |   --   |  (7-0)                          |\r
+--|    +-------------------------------------------------------------------------+                                             |\r
+--|    | PERRDTb : Parity ERRor DeTected                                                                               |                                               |\r
+--|    | SERRSIb : System ERRor SIgnaled                                                                               |                                               |\r
+--|    | TABORTSIb : Target ABORT SIgnaled                                                                             |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | REVISIONID (r) Revision ID register                   |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Identifies a device revision.                                                                                 |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | CLASSCODE (r) CLASS CODE register                             |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Identifies the generic funtion of the device.                                                 |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | HEADERTYPE (r) Header Type register                   |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Identifies the layout of the second part of the predefined header.    |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | BAR0 (r/w) Base AddRess 0 register                    |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    |                  BAR032MBb(6..0)                             |   --   | (31-24)                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|    | BAR032MBb : Base Address 32MBytes decode space (7 bits)                               |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Identifies vendor of add-in board or subsystem.                                               |                                               |\r
+--| | SUBSYSTEMVIDr : subsystemvID (generic)                                                           |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | SUBSYSTEMID (r) SUBSYSTEM ID register                 |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Vendor specific.                                                                                                              |                                               |\r
+--| | SUBSYTEMIDr : subsytemID (generic)                                                                       |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | INTLINE (r/w) INTerrupt LINE register                 |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    |                          INTLINEr(7..0)                               | (7..0)                                |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|    | Interrupt Line routing information                                                            |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--|    +-----------------------------------------------+                                                                                               |\r
+--|    | INTPIN (r) INTerrupt PIN register                             |                                                                                               |\r
+--|    +-----------------------------------------------+-----------------------+                                               |\r
+--|    | Tells which interrupt pin the device uses: 01=INTA                                    |                                               |\r
+--|    +-----------------------------------------------------------------------+                                               |\r
+--|                                                                                                                                                                                            |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  Revision history :                                                                                                                                                                |\r
+--|  Date                Version       Author  Description                                                                                                             |\r
+--|  2005-05-13   R00A00       PAU             First alfa revision (eng)                                                                               |\r
+--|                                                                                                                                                                                                    |\r
+--|  To do:                                                                                                                                                                            |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------+\r
+--|                                                                                                                            |\r
+--|  Copyright (C) 2005 Peio Azkarate, peio@opencores.org              | \r
+--|                                                                                                                            |\r
+--|  This source file may be used and distributed without              |\r
+--|  restriction provided that this copyright statement is not         |\r
+--|  removed from the file and that any derivative work contains       |\r
+--|  the original copyright notice and the associated disclaimer.      |\r
+--|                                                                    |\r
+--|  This source file is free software; you can redistribute it     |\r
+--|  and/or modify it under the terms of the GNU Lesser General     |\r
+--|  Public License as published by the Free Software Foundation;   |\r
+--|  either version 2.1 of the License, or (at your option) any     |\r
+--|  later version.                                                 |\r
+--|                                                                                                                            |\r
+--|  This source is distributed in the hope that it will be         |\r
+--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |\r
+--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |\r
+--|  PURPOSE.  See the GNU Lesser General Public License for more   |\r
+--|  details.                                                       |\r
+--|                                                                                                                            |\r
+--|  You should have received a copy of the GNU Lesser General      |\r
+--|  Public License along with this source; if not, download it     |\r
+--|  from http://www.opencores.org/lgpl.shtml                       |\r
+--|                                                                                                                            |\r
+--+-----------------------------------------------------------------+ \r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    LIBRARIES                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    ENTITY                                                                          |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity pciregs is\r
+generic (\r
+\r
+       vendorID                : std_logic_vector(15 downto 0);\r
+       deviceID                : std_logic_vector(15 downto 0);\r
+       revisionID              : std_logic_vector(7 downto 0);\r
+       subsystemID     : std_logic_vector(15 downto 0);\r
+    subsystemvID       : std_logic_vector(15 downto 0);\r
+               jcarr1ID                : std_logic_vector(31 downto 0);\r
+               jcarr2ID                : std_logic_vector(31 downto 0);\r
+               jcarr3ID                : std_logic_vector(31 downto 0);\r
+               jcarr4ID                : std_logic_vector(31 downto 0);\r
+               jcarr5ID                : std_logic_vector(31 downto 0);\r
+               jcarr6ID                : std_logic_vector(31 downto 0);\r
+               jcarr7ID                : std_logic_vector(31 downto 0);\r
+               jcarr8ID                : std_logic_vector(31 downto 0);\r
+               jcarr9ID                : std_logic_vector(31 downto 0);\r
+               jcarr10ID               : std_logic_vector(31 downto 0);\r
+               jcarr11ID               : std_logic_vector(31 downto 0);\r
+               jcarr12ID               : std_logic_vector(31 downto 0);\r
+               jcarr13ID               : std_logic_vector(31 downto 0);\r
+               jcarr14ID               : std_logic_vector(31 downto 0);\r
+               jcarr15ID               : std_logic_vector(31 downto 0);\r
+               jcarr16ID               : std_logic_vector(31 downto 0);\r
+               jcarr17ID               : std_logic_vector(31 downto 0);\r
+               jcarr18ID               : std_logic_vector(31 downto 0);\r
+               jcarr19ID               : std_logic_vector(31 downto 0);\r
+               jcarr20ID               : std_logic_vector(31 downto 0);\r
+               jcarr21ID               : std_logic_vector(31 downto 0);\r
+               jcarr22ID               : std_logic_vector(31 downto 0);\r
+               jcarr23ID               : std_logic_vector(31 downto 0);\r
+               jcarr24ID               : std_logic_vector(31 downto 0);\r
+               jcarr25ID               : std_logic_vector(31 downto 0);\r
+               jcarr26ID               : std_logic_vector(31 downto 0);\r
+               jcarr27ID               : std_logic_vector(31 downto 0);\r
+               jcarr28ID               : std_logic_vector(31 downto 0);\r
+               jcarr29ID               : std_logic_vector(31 downto 0);\r
+               jcarr30ID               : std_logic_vector(31 downto 0);\r
+               jcarr31ID               : std_logic_vector(31 downto 0);\r
+               jcarr32ID               : std_logic_vector(31 downto 0);\r
+               jcarr33ID               : std_logic_vector(31 downto 0);\r
+               jcarr34ID               : std_logic_vector(31 downto 0);\r
+               jcarr35ID               : std_logic_vector(31 downto 0);\r
+               jcarr36ID               : std_logic_vector(31 downto 0);\r
+               jcarr37ID               : std_logic_vector(31 downto 0);\r
+               jcarr38ID               : std_logic_vector(31 downto 0);\r
+               jcarr39ID               : std_logic_vector(31 downto 0);\r
+               jcarr40ID               : std_logic_vector(31 downto 0);\r
+               jcarr41ID               : std_logic_vector(31 downto 0);\r
+               jcarr42ID               : std_logic_vector(31 downto 0)\r
+\r
+);\r
+port (\r
+\r
+       -- General \r
+    clk_i              : in std_logic;\r
+       nrst_i          : in std_logic;\r
+       --  \r
+       adr_i                   : in std_logic_vector(5 downto 0);\r
+       cbe_i                   : in std_logic_vector(3 downto 0);\r
+       dat_i                   : in std_logic_vector(31 downto 0);\r
+       dat_o                   : out std_logic_vector(31 downto 0);\r
+       --\r
+       wrcfg_i                 : in std_logic;\r
+       rdcfg_i                 : in std_logic;\r
+       perr_i                  : in std_logic;\r
+       serr_i                  : in std_logic;\r
+       tabort_i                : in std_logic;\r
+       --\r
+       bar0_o                  : out std_logic_vector(31 downto 25);\r
+       perrEN_o                : out std_logic;\r
+       serrEN_o                : out std_logic;\r
+       memEN_o                 : out std_logic\r
+               \r
+);   \r
+end pciregs;\r
+\r
+\r
+architecture rtl of pciregs is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    COMPONENTS                                                                      |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    CONSTANTS                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+       constant CLASSCODEr             : std_logic_vector(23 downto 0) := X"028000";   -- Bridge-OtherBridgeDevice\r
+       constant REVISIONIDr    : std_logic_vector(7 downto 0)  := revisionID;  -- PR00=80,PR1=81...\r
+       constant HEADERTYPEr    : std_logic_vector(7 downto 0)  := X"00";               \r
+       constant DEVSELTIMb             : std_logic_vector(1 downto 0)  := b"01";               -- DEVSEL TIMing (bits) medium speed\r
+       constant VENDORIDr              : std_logic_vector(15 downto 0) := vendorID;    \r
+       constant DEVICEIDr              : std_logic_vector(15 downto 0) := deviceID;    \r
+       constant SUBSYSTEMIDr   : std_logic_vector(15 downto 0) := subsystemID; \r
+       constant SUBSYSTEMVIDr  : std_logic_vector(15 downto 0) := subsystemvID;        \r
+       constant JCARR1IDr      : std_logic_vector(31 downto 0) := jcarr1ID;\r
+       constant JCARR2IDr      : std_logic_vector(31 downto 0) := jcarr2ID;\r
+       constant JCARR3IDr      : std_logic_vector(31 downto 0) := jcarr3ID;\r
+       constant JCARR4IDr      : std_logic_vector(31 downto 0) := jcarr4ID;\r
+       constant JCARR5IDr      : std_logic_vector(31 downto 0) := jcarr5ID;\r
+       constant JCARR6IDr      : std_logic_vector(31 downto 0) := jcarr6ID;\r
+       constant JCARR7IDr      : std_logic_vector(31 downto 0) := jcarr7ID;\r
+       constant JCARR8IDr      : std_logic_vector(31 downto 0) := jcarr8ID;\r
+       constant JCARR9IDr      : std_logic_vector(31 downto 0) := jcarr9ID;\r
+       constant JCARR10IDr     : std_logic_vector(31 downto 0) := jcarr10ID;\r
+       constant JCARR11IDr     : std_logic_vector(31 downto 0) := jcarr11ID;\r
+       constant JCARR12IDr     : std_logic_vector(31 downto 0) := jcarr12ID;\r
+       constant JCARR13IDr     : std_logic_vector(31 downto 0) := jcarr13ID;\r
+       constant JCARR14IDr     : std_logic_vector(31 downto 0) := jcarr14ID;\r
+       constant JCARR15IDr     : std_logic_vector(31 downto 0) := jcarr15ID;\r
+       constant JCARR16IDr     : std_logic_vector(31 downto 0) := jcarr16ID;\r
+       constant JCARR17IDr     : std_logic_vector(31 downto 0) := jcarr17ID;\r
+       constant JCARR18IDr     : std_logic_vector(31 downto 0) := jcarr18ID;\r
+       constant JCARR19IDr     : std_logic_vector(31 downto 0) := jcarr19ID;\r
+       constant JCARR20IDr     : std_logic_vector(31 downto 0) := jcarr20ID;\r
+       constant JCARR21IDr     : std_logic_vector(31 downto 0) := jcarr21ID;\r
+       constant JCARR22IDr     : std_logic_vector(31 downto 0) := jcarr22ID;\r
+       constant JCARR23IDr     : std_logic_vector(31 downto 0) := jcarr23ID;\r
+       constant JCARR24IDr     : std_logic_vector(31 downto 0) := jcarr24ID;\r
+       constant JCARR25IDr     : std_logic_vector(31 downto 0) := jcarr25ID;\r
+       constant JCARR26IDr     : std_logic_vector(31 downto 0) := jcarr26ID;\r
+       constant JCARR27IDr     : std_logic_vector(31 downto 0) := jcarr27ID;\r
+       constant JCARR28IDr     : std_logic_vector(31 downto 0) := jcarr28ID;\r
+       constant JCARR29IDr     : std_logic_vector(31 downto 0) := jcarr29ID;\r
+       constant JCARR30IDr     : std_logic_vector(31 downto 0) := jcarr30ID;\r
+       constant JCARR31IDr     : std_logic_vector(31 downto 0) := jcarr31ID;\r
+       constant JCARR32IDr     : std_logic_vector(31 downto 0) := jcarr32ID;\r
+       constant JCARR33IDr     : std_logic_vector(31 downto 0) := jcarr33ID;\r
+       constant JCARR34IDr     : std_logic_vector(31 downto 0) := jcarr34ID;\r
+       constant JCARR35IDr     : std_logic_vector(31 downto 0) := jcarr35ID;\r
+       constant JCARR36IDr     : std_logic_vector(31 downto 0) := jcarr36ID;\r
+       constant JCARR37IDr     : std_logic_vector(31 downto 0) := jcarr37ID;\r
+       constant JCARR38IDr     : std_logic_vector(31 downto 0) := jcarr38ID;\r
+       constant JCARR39IDr     : std_logic_vector(31 downto 0) := jcarr39ID;\r
+       constant JCARR40IDr     : std_logic_vector(31 downto 0) := jcarr40ID;\r
+       constant JCARR41IDr     : std_logic_vector(31 downto 0) := jcarr41ID;\r
+       constant JCARR42IDr     : std_logic_vector(31 downto 0) := jcarr42ID;\r
+       constant INTPINr                : std_logic_vector(7 downto 0)  := X"01";               -- INTA#\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    SIGNALS                                                                         |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+       signal dataout          : std_logic_vector(31 downto 0);\r
+       signal tabortPFS        : std_logic;\r
+       signal serrPFS          : std_logic;\r
+       signal perrPFS          : std_logic;\r
+       signal adrSTCMD         : std_logic;\r
+       signal adrBAR0          : std_logic;\r
+       signal adrINT           : std_logic;\r
+       signal we0CMD           : std_logic;\r
+       signal we1CMD           : std_logic;\r
+       signal we3ST            : std_logic;\r
+       signal we3BAR0          : std_logic;\r
+       signal we0INT           : std_logic;\r
+       signal we1INT           : std_logic;\r
+       signal st11SEN          : std_logic;\r
+       signal st11REN          : std_logic;\r
+       signal st14SEN          : std_logic;\r
+       signal st14REN          : std_logic;\r
+       signal st15SEN          : std_logic;\r
+       signal st15REN          : std_logic;\r
+\r
+\r
+       --+---------------------------------------------------------+\r
+       --|  CONFIGURATION SPACE REGISTERS                                                      |\r
+       --+---------------------------------------------------------+\r
+\r
+       -- INTERRUPT LINE register \r
+       signal INTLINEr         : std_logic_vector(7 downto 0);\r
+       -- COMMAND register bits\r
+       signal MEMSPACEENb      : std_logic;                                            -- Memory SPACE ENable (bit)\r
+       signal PERRENb          : std_logic;                                            -- Parity ERRor ENable (bit)\r
+       signal SERRENb          : std_logic;                                            -- SERR ENable (bit)\r
+       -- STATUS register bits\r
+       --signal DEVSELTIMb     : std_logic_vector(1 downto 0);         -- DEVSEL TIMing (bits)\r
+       signal TABORTSIb        : std_logic;                                            -- TarGet ABORT SIgnaling (bit)\r
+       signal SERRSIb          : std_logic;                                            -- System ERRor SIgnaling (bit)\r
+       signal PERRDTb          : std_logic;                                            -- Parity ERRor DeTected (bit)\r
+       -- BAR0 register bits\r
+       signal BAR032MBb        : std_logic_vector(6 downto 0);         -- BAR0 32MBytes Space (bits)\r
+               \r
+\r
+component pfs\r
+port (\r
+   clk          : in std_logic;\r
+   a            : in std_logic;\r
+   y            : out std_logic\r
+);   \r
+\r
+end component;\r
+\r
+begin\r
+\r
+    --+-------------------------------------------------------------------------+\r
+    --|  Component instances                                                                                                   |\r
+    --+-------------------------------------------------------------------------+\r
+\r
+       u1:  pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS );\r
+       u2:  pfs port map ( clk => clk_i, a => serr_i, y => serrPFS );\r
+       u3:  pfs port map ( clk => clk_i, a => perr_i, y => perrPFS );\r
+        \r
+\r
+       --+-------------------------------------------------------------------------+\r
+       --|  Registers Address Decoder                                                                                          |\r
+    --+-------------------------------------------------------------------------+\r
+\r
+    adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0';\r
+    adrBAR0  <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0';\r
+    adrINT   <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0';\r
+\r
+\r
+       --+-------------------------------------------------------------------------+\r
+       --|                       WRITE ENABLE REGISTERS                                                        |\r
+    --+-------------------------------------------------------------------------+\r
+\r
+       --+-----------------------------------------+\r
+       --|  Write Enable Registers                                     |\r
+       --+-----------------------------------------+\r
+               \r
+    we0CMD  <= adrSTCMD and wrcfg_i and (not cbe_i(0));\r
+    we1CMD  <= adrSTCMD and wrcfg_i and (not cbe_i(1));\r
+    --we2ST    <= adrSTCMD and wrcfg_i and (not cbe_i(2));\r
+    we3ST   <= adrSTCMD and wrcfg_i and (not cbe_i(3));\r
+    --we2BAR0 <= adrBAR0  and wrcfg_i and (not cbe_i(2));\r
+    we3BAR0 <= adrBAR0  and wrcfg_i and (not cbe_i(3));\r
+       we0INT  <= adrINT   and wrcfg_i and (not cbe_i(0));\r
+    --we1INT   <= adrINT   and wrcfg_i and (not cbe_i(1));\r
+\r
+       --+-----------------------------------------+\r
+       --|  Set Enable & Reset Enable bits                     |\r
+       --+-----------------------------------------+\r
+       st11SEN <= tabortPFS; \r
+       st11REN <= we3ST and dat_i(27);\r
+       st14SEN <= serrPFS; \r
+       st14REN <= we3ST and dat_i(30);\r
+       st15SEN <= perrPFS; \r
+       st15REN <= we3ST and dat_i(31);\r
+\r
+\r
+       --+-------------------------------------------------------------------------+\r
+       --|                                                     WRITE REGISTERS                                                         |\r
+    --+-------------------------------------------------------------------------+\r
+\r
+       --+---------------------------------------------------------+\r
+       --|  COMMAND REGISTER Write                                                                     |\r
+       --+---------------------------------------------------------+\r
+\r
+    REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i )\r
+    begin\r
+\r
+        if( nrst_i = '0' ) then\r
+                       MEMSPACEENb <= '0';\r
+                       PERRENb         <= '0';\r
+                       SERRENb         <= '0';                 \r
+        elsif( rising_edge( clk_i ) ) then\r
+\r
+                       -- Byte 0\r
+            if( we0CMD = '1' ) then\r
+                               MEMSPACEENb <= dat_i(1);\r
+                               PERRENb         <= dat_i(6);                \r
+            end if;\r
+                       \r
+                       -- Byte 1\r
+            if( we1CMD = '1' ) then\r
+                               SERRENb         <= dat_i(8);                \r
+            end if;\r
+\r
+        end if;\r
+\r
+    end process REGCMDWR;\r
+\r
+\r
+       --+---------------------------------------------------------+\r
+       --|  STATUS REGISTER WRITE (Reset only)                                         |\r
+       --+---------------------------------------------------------+\r
+\r
+    REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN )\r
+    begin\r
+\r
+        if( nrst_i = '0' ) then\r
+                       TABORTSIb       <= '0';\r
+                       SERRSIb         <= '0';\r
+                       PERRDTb         <= '0';\r
+        elsif( rising_edge( clk_i ) ) then\r
+\r
+                       -- TarGet ABORT SIgnaling bit\r
+            if( st11SEN = '1' ) then\r
+                               TABORTSIb       <= '1';\r
+                       elsif ( st11REN = '1' ) then\r
+                               TABORTSIb       <= '0';                 \r
+            end if;\r
+\r
+                       -- System ERRor SIgnaling bit\r
+            if( st14SEN = '1' ) then\r
+                               SERRSIb <= '1';\r
+                       elsif ( st14REN = '1' ) then\r
+                               SERRSIb <= '0';                 \r
+            end if;\r
+\r
+                       -- Parity ERRor DEtected bit\r
+            if( st15SEN = '1' ) then\r
+                               PERRDTb <= '1';\r
+                       elsif ( st15REN = '1' ) then\r
+                               PERRDTb <= '0';                 \r
+            end if;\r
+                       \r
+        end if;\r
+\r
+    end process REGSTWR;\r
+\r
+\r
+       --+---------------------------------------------------------+\r
+       --|  INTERRUPT REGISTER Write                                                           |\r
+       --+---------------------------------------------------------+\r
+\r
+    REGINTWR: process( clk_i, nrst_i, we0INT, dat_i )\r
+    begin\r
+\r
+        if( nrst_i = '0' ) then\r
+                       INTLINEr <= ( others => '0' );\r
+        elsif( rising_edge( clk_i ) ) then\r
+\r
+                       -- Byte 0\r
+            if( we0INT = '1' ) then\r
+                               INTLINEr <= dat_i(7 downto 0);\r
+            end if;\r
+                       \r
+\r
+        end if;\r
+\r
+    end process REGINTWR;\r
+\r
+\r
+       --+---------------------------------------------------------+\r
+       --|  BAR0 32MBytes address space (bits 31-25)                           |\r
+       --+---------------------------------------------------------+\r
+\r
+    REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i )\r
+    begin\r
+\r
+        if( nrst_i = '0' ) then\r
+                       BAR032MBb <= ( others => '1' );\r
+        elsif( rising_edge( clk_i ) ) then\r
+\r
+                       -- Byte 3\r
+            if( we3BAR0 = '1' ) then\r
+                               BAR032MBb <= dat_i(31 downto 25);\r
+            end if;\r
+                       \r
+        end if;\r
+\r
+    end process REGBAR0WR;\r
+\r
+\r
+       --+-------------------------------------------------------------------------+\r
+       --|  Registers MUX      (READ)                                                                                                  |\r
+    --+-------------------------------------------------------------------------+\r
+--+-------------------------------------------------------------------------------------------------+\r
+\r
+    RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, \r
+                                       INTLINEr, rdcfg_i )\r
+    begin\r
+\r
+               if ( rdcfg_i = '1' ) then\r
+               \r
+               case adr_i is\r
+\r
+               when b"000000" => \r
+                                       dataout <= DEVICEIDr & VENDORIDr;\r
+               when b"000001" => \r
+                                       dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" &\r
+                                                          b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0";\r
+                   when b"000010" => \r
+                                       dataout <= CLASSCODEr & REVISIONIDr;\r
+                   when b"000100" => \r
+                                       dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000";\r
+               when b"001011" => \r
+                                       dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr;\r
+                   when b"001111" => \r
+                                       dataout <= b"0000000000000000" & INTPINr & INTLINEr;\r
+                when b"010001" =>\r
+                                 dataout <= JCARR1IDr;\r
+                when b"010010" =>\r
+                                 dataout <= JCARR2IDr;\r
+                when b"010011" =>\r
+                                 dataout <= JCARR3IDr;\r
+                when b"010100" =>\r
+                                 dataout <= JCARR4IDr;\r
+                when b"010101" =>\r
+                                 dataout <= JCARR5IDr;\r
+                when b"010110" =>\r
+                                 dataout <= JCARR6IDr;\r
+                when b"010111" =>\r
+                                 dataout <= JCARR7IDr;\r
+                when b"011000" =>\r
+                                 dataout <= JCARR8IDr;\r
+                when b"011001" =>\r
+                                 dataout <= JCARR9IDr;\r
+                when b"011010" =>\r
+                                 dataout <= JCARR10IDr;\r
+                when b"011011" =>\r
+                                 dataout <= JCARR11IDr;\r
+                when b"011100" =>\r
+                                 dataout <= JCARR12IDr;\r
+                when b"011101" =>\r
+                                 dataout <= JCARR13IDr;\r
+                when b"011110" =>\r
+                                 dataout <= JCARR14IDr;\r
+                when b"011111" =>\r
+                                 dataout <= JCARR15IDr;\r
+                when b"100000" =>\r
+                                 dataout <= JCARR16IDr;\r
+                when b"100001" =>\r
+                                 dataout <= JCARR17IDr;\r
+                when b"100010" =>\r
+                                 dataout <= JCARR18IDr;\r
+                when b"100011" =>\r
+                                 dataout <= JCARR19IDr;\r
+                when b"100100" =>\r
+                                 dataout <= JCARR20IDr;\r
+                when b"100101" =>\r
+                                 dataout <= JCARR21IDr;\r
+                when b"100110" =>\r
+                                 dataout <= JCARR22IDr;\r
+                when b"100111" =>\r
+                                 dataout <= JCARR23IDr;\r
+                when b"101000" =>\r
+                                 dataout <= JCARR24IDr;\r
+                when b"101001" =>\r
+                                 dataout <= JCARR25IDr;\r
+                when b"101010" =>\r
+                                 dataout <= JCARR26IDr;\r
+                when b"101011" =>\r
+                                 dataout <= JCARR27IDr;\r
+                when b"101100" =>\r
+                                 dataout <= JCARR28IDr;\r
+                when b"101101" =>\r
+                                 dataout <= JCARR29IDr;\r
+                when b"101110" =>\r
+                                 dataout <= JCARR30IDr;\r
+                when b"101111" =>\r
+                                 dataout <= JCARR31IDr;\r
+                when b"110000" =>\r
+                                 dataout <= JCARR32IDr;\r
+                when b"110001" =>\r
+                                 dataout <= JCARR33IDr;\r
+                when b"110010" =>\r
+                                 dataout <= JCARR34IDr;\r
+                when b"110011" =>\r
+                                 dataout <= JCARR35IDr;\r
+                when b"110100" =>\r
+                                 dataout <= JCARR36IDr;\r
+                when b"110101" =>\r
+                                 dataout <= JCARR37IDr;\r
+                when b"110110" =>\r
+                                 dataout <= JCARR38IDr;\r
+                when b"110111" =>\r
+                                 dataout <= JCARR39IDr;\r
+                when b"111000" =>\r
+                                 dataout <= JCARR40IDr;\r
+                when b"111001" =>\r
+                                 dataout <= JCARR41IDr;\r
+                when b"111010" =>\r
+                                 dataout <= JCARR42IDr;\r
+                   when others    => \r
+                                       dataout <= ( others => '0' );\r
+\r
+               end case;\r
+       \r
+               else\r
+               \r
+                       dataout <= ( others => '0' );\r
+                       \r
+               end if;\r
+\r
+    end process RRMUX;\r
+\r
+       dat_o <= dataout;\r
+       \r
+       \r
+       --+-------------------------------------------------------------------------+\r
+       --|  BAR0 & COMMAND REGS bits outputs                                                                           |\r
+    --+-------------------------------------------------------------------------+\r
+       \r
+       bar0_o          <= BAR032MBb;\r
+       perrEN_o        <= PERRENb;\r
+       serrEN_o        <= SERRENb;                     \r
+       memEN_o         <= MEMSPACEENb;\r
+\r
+       \r
+end rtl;\r
diff --git a/dhwk_old/source/pcidec.v b/dhwk_old/source/pcidec.v
new file mode 100644 (file)
index 0000000..1b44acb
--- /dev/null
@@ -0,0 +1,67 @@
+//  Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r
+//  Copyright (C) 2006 Jeff Carr, jcarr@opencores.org\r
+//     Copyleft GPL v2\r
+\r
+module pcidec_new (clk_i, nrst_i, ad_i, cbe_i, idsel_i, bar0_i, memEN_i,\r
+       pciadrLD_i, adrcfg_o, adrmem_o, adr_o, cmd_o);\r
+\r
+       // General \r
+       input clk_i;\r
+       input nrst_i;\r
+       // pci \r
+       input [31:0] ad_i;\r
+       input [3:0] cbe_i;\r
+       input idsel_i;\r
+       // control\r
+       input [31:25] bar0_i;\r
+       input memEN_i;\r
+       input pciadrLD_i;\r
+       output adrcfg_o;\r
+       output adrmem_o;\r
+       output [24:1] adr_o;\r
+       output [3:0] cmd_o;\r
+\r
+       reg [31:0] adr;\r
+       reg [3:0] cmd;\r
+       reg idsel_s;\r
+       wire a1;\r
+\r
+       //+-------------------------------------------------------------------------+\r
+       //|  Load PCI Signals                                                                                                           |\r
+       //+-------------------------------------------------------------------------+\r
+\r
+       always @( negedge nrst_i or posedge clk_i )\r
+       begin\r
+               if( nrst_i == 0 )\r
+               begin\r
+                       adr <= 23'b1111_1111_1111_1111_1111_111;\r
+                       cmd <= 3'b111;\r
+                       idsel_s <= 1'b0;\r
+               end\r
+               else\r
+                       if ( pciadrLD_i == 1 )\r
+                       begin\r
+                               adr <= ad_i;\r
+                               cmd <= cbe_i;\r
+                               idsel_s <= idsel_i;\r
+                       end\r
+       end\r
+\r
+       assign adrmem_o = (\r
+               ( memEN_i == 1'b1 ) &&\r
+               ( adr [31:25] == bar0_i ) &&\r
+               ( adr [1:0] == 2'b00 ) &&\r
+               ( cmd [3:1] == 3'b011 )\r
+       ) ? 1'b1 : 1'b0;\r
+\r
+       assign adrcfg_o = (\r
+               ( idsel_s == 1'b1 ) &&\r
+               ( adr [1:0] == 2'b00 ) &&\r
+               ( cmd [3:1] == 3'b101 )\r
+       ) ? 1'b1 : 1'b0;\r
+\r
+       assign a1 = ~ ( cbe_i [3] && cbe_i [2] );\r
+       assign adr_o = {adr [24:2], a1};\r
+       assign cmd_o = cmd;\r
+\r
+endmodule\r
diff --git a/dhwk_old/source/pcidmux.v b/dhwk_old/source/pcidmux.v
new file mode 100644 (file)
index 0000000..bee8bd8
--- /dev/null
@@ -0,0 +1,55 @@
+// Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r
+// Copyright (C) 2006 Jeff Carr, jcarr@opencores.org\r
+//\r
+// I think what this does is handle 16 vs 32 bit pci accesses\r
+\r
+module pcidmux ( clk_i, nrst_i, d_io, pcidatout_o, pcidOE_i, wbdatLD_i, wbrgdMX_i,\r
+       wbd16MX_i, wb_dat_i, wb_dat_o, rg_dat_i, rg_dat_o);\r
+\r
+       input clk_i;\r
+       input nrst_i;\r
+\r
+       // d_io                 : inout std_logic_vector(31 downto 0);\r
+       inout [31:0] d_io;\r
+       output [31:0] pcidatout_o;\r
+\r
+       input pcidOE_i;\r
+       input wbdatLD_i;\r
+       input wbrgdMX_i;\r
+       input wbd16MX_i;\r
+\r
+       input [15:0] wb_dat_i;\r
+       output [15:0] wb_dat_o;\r
+       input [31:0] rg_dat_i;\r
+       output [31:0] rg_dat_o;\r
+\r
+       wire [31:0] pcidatin;\r
+       wire [31:0] pcidatout;\r
+\r
+       reg [15:0] wb_dat_is;\r
+\r
+       // always @(negedge nrst_i or posedge clk_i or posedge wbdatLD_i or posedge wb_dat_i)\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+               if ( nrst_i == 0 )\r
+                       wb_dat_is <= 16'b1111_1111_1111_1111;\r
+               else\r
+                       if ( wbdatLD_i == 1 )\r
+                               wb_dat_is <= wb_dat_i;\r
+       end\r
+\r
+       assign pcidatin = d_io;\r
+       assign d_io = (pcidOE_i == 1'b1 ) ? pcidatout : 32'bZ;\r
+\r
+       assign pcidatout [31:24] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0]  : rg_dat_i [31:24];\r
+       assign pcidatout [23:16] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [23:16];\r
+       assign pcidatout [15:8]  = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0]  : rg_dat_i [15:8];\r
+       assign pcidatout [7:0]   = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [7:0];\r
+\r
+       assign pcidatout_o = pcidatout;\r
+       assign rg_dat_o = pcidatin;\r
+\r
+       assign wb_dat_o [15:8] = (wbd16MX_i == 1'b1) ? pcidatin [23:16] : pcidatin [7:0];\r
+       assign wb_dat_o [7:0]  = (wbd16MX_i == 1'b1) ? pcidatin [31:24] : pcidatin [15:8];\r
+\r
+endmodule \r
diff --git a/dhwk_old/source/pcipargen.v b/dhwk_old/source/pcipargen.v
new file mode 100644 (file)
index 0000000..86eca4e
--- /dev/null
@@ -0,0 +1,80 @@
+//\r
+//                  PCI Parity Generator.\r
+//\r
+// PCI Target generates PAR in the data phase of a read cycle. \r
+// The 1's sum on AD, CBE and PAR is even.\r
+//\r
+//   Date                Version       Author  Description\r
+//   2005-05-13   R00A00       PAU             First alfa revision     (eng)\r
+//\r
+//  Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r
+//\r
+//   This source file is free software; you can redistribute it     |\r
+//   and/or modify it under the terms of the GNU Lesser General     |\r
+//   Public License as published by the Free Software Foundation;   |\r
+//   either version 2.1 of the License, or (at your option) any     |\r
+//   later version.                                                 |\r
+\r
+\r
+module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o);\r
+\r
+       input clk_i;\r
+       input [31:0] pcidatout_i;\r
+       input [3:0] cbe_i;\r
+       input parOE_i;\r
+       output par_o;\r
+\r
+\r
+       wire [31:0] d;\r
+       wire pardat;\r
+       wire parcbe;\r
+       wire par;\r
+       wire par_s;\r
+\r
+       assign d = pcidatout_i;\r
+\r
+       assign pardat = d[0]  ^ d[1]  ^ d[2]  ^ d[3]  ^ d[4]  ^ d[5]  ^ d[6]  ^ d[7]  ^ \r
+                          d[8]  ^ d[9]  ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ \r
+                          d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ \r
+                          d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];\r
+                                               \r
+       assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3]; \r
+\r
+       assign par = pardat ^ parcbe;\r
+\r
+    // PAR\r
+       assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ;\r
+\r
+endmodule\r
+/*\r
+component sync\r
+port (\r
+    clk             : in std_logic;\r
+    d           : in std_logic;\r
+    q               : out std_logic\r
+);\r
+end component;\r
+\r
+component sync2\r
+port (\r
+    clk             : in std_logic;\r
+    d           : in std_logic;\r
+    q               : out std_logic\r
+);\r
+end component;\r
+\r
+begin\r
+\r
+\r
+\r
+    u1: sync2 port map (\r
+               clk => clk_i,\r
+               d => par,\r
+               q => par_s\r
+       );\r
+       \r
+\r
+\r
+\r
+end rtl;\r
+*/\r
diff --git a/dhwk_old/source/pcipargen.vhd b/dhwk_old/source/pcipargen.vhd
new file mode 100644 (file)
index 0000000..a1dfc16
--- /dev/null
@@ -0,0 +1,144 @@
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  File:             pcipargen.vhd                                                                                   |\r
+--|                                                                                                                                                                                                    |\r
+--|  Project:          pci32tlite_oc                                                                                                                                   |\r
+--|                                                                                                                                                                                                    |\r
+--|  Description:      PCI Parity Generator.                                                                                                                   |\r
+--|                                    PCI Target generates PAR in the data phase of a read cycle. The 1's sum on AD,  |\r
+--|                                    CBE and PAR is even.                                                                                    |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  Revision history :                                                                                                                                                                |\r
+--|  Date                Version       Author  Description                                                                                                             |\r
+--|  2005-05-13   R00A00       PAU             First alfa revision     (eng)                                                                           |\r
+--|                                                                                                                                                                                                    |\r
+--|  To do:                                                                                                                                                                                    |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------+\r
+--|                                                                                                                            |\r
+--|  Copyright (C) 2005 Peio Azkarate, peio@opencores.org              | \r
+--|                                                                                                                            |\r
+--|  This source file may be used and distributed without              |\r
+--|  restriction provided that this copyright statement is not         |\r
+--|  removed from the file and that any derivative work contains       |\r
+--|  the original copyright notice and the associated disclaimer.      |\r
+--|                                                                    |\r
+--|  This source file is free software; you can redistribute it     |\r
+--|  and/or modify it under the terms of the GNU Lesser General     |\r
+--|  Public License as published by the Free Software Foundation;   |\r
+--|  either version 2.1 of the License, or (at your option) any     |\r
+--|  later version.                                                 |\r
+--|                                                                                                                            |\r
+--|  This source is distributed in the hope that it will be         |\r
+--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |\r
+--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |\r
+--|  PURPOSE.  See the GNU Lesser General Public License for more   |\r
+--|  details.                                                       |\r
+--|                                                                                                                            |\r
+--|  You should have received a copy of the GNU Lesser General      |\r
+--|  Public License along with this source; if not, download it     |\r
+--|  from http://www.opencores.org/lgpl.shtml                       |\r
+--|                                                                                                                            |\r
+--+-----------------------------------------------------------------+ \r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    LIBRARIES                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    ENTITY                                                                          |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity pcipargen is\r
+port (\r
+\r
+       clk_i                   : in std_logic;\r
+       pcidatout_i             : in std_logic_vector(31 downto 0);\r
+       cbe_i                   : in std_logic_vector(3 downto 0);\r
+       parOE_i                 : in std_logic;\r
+       par_o                   : out std_logic\r
+       \r
+);   \r
+end pcipargen;\r
+\r
+\r
+architecture rtl of pcipargen is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    COMPONENTS                                                                      |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    CONSTANTS                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    SIGNALS                                                                         |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+       signal d                        : std_logic_vector(31 downto 0);\r
+       signal pardat           : std_logic;\r
+       signal parcbe           : std_logic;\r
+       signal par                      : std_logic;\r
+       signal par_s            : std_logic;\r
+\r
+component sync\r
+port (\r
+    clk             : in std_logic;\r
+    d           : in std_logic;\r
+    q               : out std_logic\r
+);\r
+end component;\r
+\r
+component sync2\r
+port (\r
+    clk             : in std_logic;\r
+    d           : in std_logic;\r
+    q               : out std_logic\r
+);\r
+end component;\r
+\r
+begin\r
+\r
+\r
+       d <= pcidatout_i;\r
+\r
+       \r
+    --+-------------------------------------------------------------------------+\r
+       --|  building parity                                                                                                            |\r
+    --+-------------------------------------------------------------------------+\r
+       \r
+       pardat  <= d(0)  xor d(1)  xor d(2)  xor d(3)  xor d(4)  xor d(5)  xor d(6)  xor d(7)  xor \r
+                          d(8)  xor d(9)  xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor \r
+                          d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor \r
+                          d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);\r
+                                               \r
+       parcbe  <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3); \r
+       \r
+       par <= pardat xor parcbe;\r
+\r
+    -- u1: sync port map ( clk => clk_i, d => par, q => par_s );\r
+       \r
+    u1: sync2 port map (\r
+               clk => clk_i,\r
+               d => par,\r
+               q => par_s\r
+       );\r
+       \r
+\r
+    --+-------------------------------------------------------------------------+\r
+    --|  PAR                                                                                                                                   |\r
+    --+-------------------------------------------------------------------------+\r
+\r
+       par_o <= par_s when ( parOE_i = '1' ) else 'Z';\r
+\r
+\r
+end rtl;\r
diff --git a/dhwk_old/source/pciwbsequ.v b/dhwk_old/source/pciwbsequ.v
new file mode 100644 (file)
index 0000000..2b09f7f
--- /dev/null
@@ -0,0 +1,295 @@
+// Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r
+//\r
+//   This source file is free software; you can redistribute it\r
+//   and/or modify it under the terms of the GNU Lesser General\r
+//   Public License as published by the Free Software Foundation;\r
+//   either version 2.1 of the License, or (at your option) any\r
+//   later version.\r
+//\r
+\r
+(* signal_encoding = "user" *)\r
+(* safe_implementation = "yes" *)\r
+\r
+module pciwbsequ_new ( clk_i, nrst_i, cmd_i, cbe_i, frame_i, irdy_i, devsel_o, \r
+       trdy_o, adrcfg_i, adrmem_i, pciadrLD_o, pcidOE_o, parOE_o, wbdatLD_o, \r
+       wbrgdMX_o, wbd16MX_o, wrcfg_o, rdcfg_o, wb_sel_o, wb_we_o, wb_stb_o, \r
+       wb_cyc_o, wb_ack_i, wb_err_i, debug_init, debug_access );\r
+\r
+       // General \r
+       input clk_i;\r
+       input nrst_i;\r
+       // pci \r
+       // adr_i\r
+       input [3:0] cmd_i;\r
+       input [3:0] cbe_i;\r
+       input frame_i;\r
+       input irdy_i;\r
+       output devsel_o;\r
+       output trdy_o;\r
+       // control\r
+       input adrcfg_i;\r
+       input adrmem_i;\r
+       output pciadrLD_o;\r
+       output pcidOE_o;\r
+       output reg parOE_o;\r
+       output wbdatLD_o;\r
+       output wbrgdMX_o;\r
+       output wbd16MX_o;\r
+       output wrcfg_o;\r
+       output rdcfg_o;\r
+       // whisbone\r
+       output [1:0] wb_sel_o;\r
+       output wb_we_o;\r
+       inout wb_stb_o;\r
+       output wb_cyc_o;\r
+       input wb_ack_i;\r
+       input wb_err_i;\r
+       // debug signals\r
+       output reg debug_init;\r
+       output reg debug_access;\r
+\r
+       //type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR );        \r
+       //wire pst_pci          : PciFSM;\r
+       //wire nxt_pci          : PciFSM;\r
+\r
+       //      typedef enum reg [2:0] {\r
+       //              RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW\r
+       //      } color_t;\r
+       //\r
+       //      color_t   my_color = GREEN;\r
+\r
+       // parameter PCIIDLE    = 2'b00;\r
+       // parameter B_BUSY     = 2'b01;\r
+       // parameter S_DATA1    = 2'b10;\r
+       // parameter S_DATA2    = 2'b11;\r
+       // parameter TURN_AR    = 3'b100;\r
+\r
+       reg [2:0] pst_pci;\r
+       reg [2:0] nxt_pci;\r
+\r
+       parameter [2:0] \r
+               PCIIDLE    = 3'b000,\r
+               B_BUSY     = 3'b001,\r
+               S_DATA1    = 3'b010,\r
+               S_DATA2    = 3'b011,\r
+               TURN_AR    = 3'b100;\r
+\r
+\r
+       initial begin\r
+               pst_pci = 3'b000;\r
+       end\r
+\r
+       initial begin\r
+               nxt_pci = 3'b000;\r
+       end\r
+       \r
+       wire sdata1;\r
+       wire sdata2;\r
+       wire idleNX;\r
+       wire sdata1NX;\r
+       wire sdata2NX;\r
+       wire turnarNX;\r
+       wire idle;\r
+       reg  devselNX_n;\r
+       reg  trdyNX_n;\r
+       reg  devsel;\r
+       reg  trdy;\r
+       wire adrpci;\r
+       wire acking;\r
+       wire rdcfg;\r
+       reg  targOE;\r
+       reg  pcidOE;\r
+\r
+       // always @(nrst_i or clk_i or nxt_pci)\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+       if( nrst_i == 0 )\r
+                       pst_pci <= PCIIDLE;\r
+               else \r
+                       pst_pci <= nxt_pci; \r
+       end\r
+\r
+       // always @(negedge nrst_i or posedge clk_i)\r
+       always @( pst_pci or frame_i or irdy_i or adrcfg_i or adrpci or acking )\r
+       begin\r
+               devselNX_n      <= 1'b1;\r
+               trdyNX_n        <= 1'b1;        \r
+               case (pst_pci)\r
+            PCIIDLE : \r
+                       begin\r
+                               if ( frame_i == 0 )\r
+                                       nxt_pci <= B_BUSY;      \r
+                               else\r
+                                       nxt_pci <= PCIIDLE;\r
+                       end\r
+               B_BUSY:\r
+                               if ( adrpci == 0 )\r
+                                       nxt_pci <= TURN_AR;\r
+                               else\r
+                                       begin\r
+                                       nxt_pci <= S_DATA1;\r
+                                       devselNX_n <= 0; \r
+                                       end\r
+                       S_DATA1:\r
+                               if ( acking == 1 )\r
+                                       begin\r
+                                       nxt_pci         <= S_DATA2;\r
+                                       devselNX_n      <= 0;                                   \r
+                                       trdyNX_n        <= 0;   \r
+                                       end\r
+                               else\r
+                                       begin\r
+                                       nxt_pci <= S_DATA1;\r
+                                       devselNX_n <= 0;                                        \r
+                                       end\r
+                       S_DATA2:\r
+                       if ( frame_i == 1 && irdy_i == 0 )\r
+                                       nxt_pci <= TURN_AR;\r
+                               else\r
+                                       begin\r
+                                       nxt_pci <= S_DATA2;\r
+                                       devselNX_n <= 0;\r
+                                       trdyNX_n <= 0;\r
+                                       end\r
+                       TURN_AR:\r
+                               if ( frame_i == 1 )\r
+                                       nxt_pci <= PCIIDLE;\r
+                               else\r
+                                       nxt_pci <= TURN_AR;\r
+           endcase\r
+       end\r
+\r
+       // FSM control signals\r
+       assign adrpci = adrmem_i;\r
+       \r
+       assign acking = (\r
+               ( wb_ack_i == 1 || wb_err_i == 1 ) || \r
+               ( adrcfg_i == 1 &&   irdy_i == 0)\r
+       ) ? 1'b1 : 1'b0; \r
+\r
+       // FSM derived Control signals\r
+       assign idle             = ( pst_pci <= PCIIDLE ) ? 1'b1 : 1'b0;\r
+       assign sdata1           = ( pst_pci <= S_DATA1 ) ? 1'b1 : 1'b0;\r
+       assign sdata2           = ( pst_pci <= S_DATA2 ) ? 1'b1 : 1'b0;\r
+       assign idleNX           = ( nxt_pci <= PCIIDLE ) ? 1'b1 : 1'b0;\r
+       assign sdata1NX         = ( nxt_pci <= S_DATA1 ) ? 1'b1 : 1'b0;\r
+       assign sdata2NX         = ( nxt_pci <= S_DATA2 ) ? 1'b1 : 1'b0;\r
+       assign turnarNX         = ( nxt_pci <= TURN_AR ) ? 1'b1 : 1'b0;\r
+\r
+       // PCI Data Output Enable\r
+       // always @( nrst_i or clk_i or cmd_i [0] or sdata1NX or turnarNX )\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+       if ( nrst_i == 0 )\r
+                       pcidOE <= 0;\r
+               else\r
+                       if ( sdata1NX == 1 && cmd_i [0] == 0 )\r
+                               pcidOE <= 1;\r
+                       else \r
+                               if ( turnarNX == 1 )\r
+                                       pcidOE <= 0;\r
+       end\r
+\r
+       assign pcidOE_o = pcidOE;\r
+\r
+       // PAR Output Enable\r
+       // PCI Read data phase\r
+       // PAR is valid 1 cicle after data is valid\r
+       // always @( nrst_i or clk_i or cmd_i [0] or sdata2NX or turnarNX )\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+       if ( nrst_i == 0 )\r
+                       parOE_o <= 0;\r
+               else\r
+                       if ( ( sdata2NX == 1 || turnarNX == 1 ) && cmd_i [0] == 0 )\r
+                               parOE_o <= 1;\r
+                       else\r
+                               parOE_o <= 0;\r
+       end\r
+\r
+       // Target s/t/s signals OE control\r
+       // targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0';\r
+       // always @( nrst_i or clk_i or sdata1NX or idleNX )\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+       if ( nrst_i == 0 )\r
+                       targOE <= 0;\r
+               else\r
+                       if ( sdata1NX == 1 )\r
+                               targOE <= 1;\r
+                       else \r
+                               if ( idleNX == 1 )\r
+                                       targOE <= 0;\r
+       end\r
+               \r
+    // WHISBONE outs\r
+       assign wb_cyc_o = (adrmem_i == 1 && sdata1 == 1) ? 1'b1 : 1'b0;\r
+    assign wb_stb_o = (adrmem_i == 1 && sdata1 == 1 && irdy_i == 0 ) ? 1'b1 : 1'b0;\r
+\r
+       // PCI(Little endian) to WB(Big endian)\r
+       assign wb_sel_o [1] = (! cbe_i [0]) || (! cbe_i [2]);\r
+       assign wb_sel_o [0] = (! cbe_i [1]) || (! cbe_i [3]);   \r
+\r
+       assign wb_we_o = cmd_i [0];\r
+\r
+       // Syncronized PCI outs\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+               if( nrst_i == 0 )\r
+                       begin\r
+                       devsel  <= 1;\r
+                       trdy    <= 1;\r
+                       end\r
+               else\r
+                       begin\r
+                       devsel <= devselNX_n;\r
+                       trdy   <= trdyNX_n;\r
+                       end\r
+       end\r
+\r
+       assign devsel_o = ( targOE == 1 ) ? devsel : 1'bZ;\r
+       assign trdy_o   = ( targOE == 1 ) ? trdy   : 1'bZ;\r
+\r
+       // rd/wr Configuration Space Registers\r
+       assign wrcfg_o = (\r
+               adrcfg_i == 1 &&\r
+               cmd_i [0] == 1 &&\r
+               sdata2 == 1\r
+       ) ? 1'b1 : 1'b0;\r
+\r
+       assign rdcfg = (\r
+               adrcfg_i == 1 &&\r
+               cmd_i [0] == 0 &&\r
+               (sdata1 == 1 || sdata2 == 1)\r
+       ) ? 1'b1 : 1'b0;\r
+\r
+       assign rdcfg_o = rdcfg;\r
+\r
+       // LoaD enable signals\r
+       assign pciadrLD_o = ! frame_i;\r
+       assign wbdatLD_o  = wb_ack_i;\r
+\r
+       // Mux control signals\r
+       assign wbrgdMX_o = ! rdcfg;\r
+       assign wbd16MX_o = (cbe_i [3] == 0 || cbe_i [2] == 0) ? 1'b1 : 1'b0;\r
+       \r
+       // debug outs \r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+               if ( nrst_i == 0 )\r
+                       debug_init <= 0;\r
+               else\r
+                       if (devsel == 0)\r
+                               debug_init <= 1;\r
+       end\r
+\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+               if ( nrst_i == 0 )\r
+                       debug_access <= 0;\r
+               else\r
+                       if (wb_stb_o == 1)\r
+                               debug_access <= 1;\r
+       end\r
+\r
+endmodule\r
diff --git a/dhwk_old/source/pciwbsequ.vhd b/dhwk_old/source/pciwbsequ.vhd
new file mode 100644 (file)
index 0000000..61744cf
--- /dev/null
@@ -0,0 +1,382 @@
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  File:                     pciwbsequ.vhd                                                                           |\r
+--|                                                                                                                                                                                                    |\r
+--|  Project:          pci32tlite_oc                                                                                                                                   |\r
+--|                                                                                                                                                                                                    |\r
+--|  Description:      FSM controlling PCI to Whisbone sequence.                                                                               |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  Revision history :                                                                                                                                                                |\r
+--|  Date                Version       Author  Description                                                                                                             |\r
+--|  2005-05-13   R00A00    PAU                First alfa revision     (eng)                                                                           |\r
+--|  2006-01-09             MS      added debug signals debug_init, debug_access                                       |                                                                                                                                                       |\r
+--|                                                                                                                                                                                                    |\r
+--|  To do:                                                                                                                                                                                    |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------+\r
+--|                                                                                                                            |\r
+--|  Copyright (C) 2005 Peio Azkarate, peio@opencores.org              | \r
+--|                                                                                                                            |\r
+--|  This source file may be used and distributed without              |\r
+--|  restriction provided that this copyright statement is not         |\r
+--|  removed from the file and that any derivative work contains       |\r
+--|  the original copyright notice and the associated disclaimer.      |\r
+--|                                                                    |\r
+--|  This source file is free software; you can redistribute it     |\r
+--|  and/or modify it under the terms of the GNU Lesser General     |\r
+--|  Public License as published by the Free Software Foundation;   |\r
+--|  either version 2.1 of the License, or (at your option) any     |\r
+--|  later version.                                                 |\r
+--|                                                                                                                            |\r
+--|  This source is distributed in the hope that it will be         |\r
+--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |\r
+--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |\r
+--|  PURPOSE.  See the GNU Lesser General Public License for more   |\r
+--|  details.                                                       |\r
+--|                                                                                                                            |\r
+--|  You should have received a copy of the GNU Lesser General      |\r
+--|  Public License along with this source; if not, download it     |\r
+--|  from http://www.opencores.org/lgpl.shtml                       |\r
+--|                                                                                                                            |\r
+--+-----------------------------------------------------------------+ \r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    LIBRARIES                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    ENTITY                                                                          |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity pciwbsequ is\r
+port (\r
+\r
+       -- General \r
+    clk_i              : in std_logic;\r
+       nrst_i          : in std_logic;\r
+       -- pci \r
+       --adr_i\r
+       cmd_i                   : in std_logic_vector(3 downto 0);\r
+       cbe_i                   : in std_logic_vector(3 downto 0);\r
+       frame_i                 : in std_logic;\r
+       irdy_i          : in std_logic;\r
+       devsel_o                : out std_logic;\r
+       trdy_o          : out std_logic;\r
+       -- control\r
+       adrcfg_i                : in std_logic;\r
+       adrmem_i                : in std_logic;\r
+       pciadrLD_o              : out std_logic;\r
+       pcidOE_o                : out std_logic;\r
+       parOE_o                 : out std_logic;\r
+       wbdatLD_o       : out std_logic;\r
+       wbrgdMX_o       : out std_logic;\r
+       wbd16MX_o       : out std_logic;        \r
+       wrcfg_o                 : out std_logic;\r
+       rdcfg_o                 : out std_logic;\r
+       -- whisbone\r
+       wb_sel_o                : out std_logic_vector(1 downto 0);\r
+       wb_we_o                 : out std_logic;\r
+       wb_stb_o                : inout std_logic;      \r
+       wb_cyc_o                : out std_logic;\r
+       wb_ack_i                : in std_logic;\r
+       wb_err_i                : in std_logic; \r
+       -- debug signals\r
+       debug_init       : out std_logic;\r
+       debug_access : out std_logic \r
+);   \r
+end pciwbsequ;\r
+\r
+\r
+architecture rtl of pciwbsequ is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    COMPONENTS                                                                      |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    CONSTANTS                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    SIGNALS                                                                         |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+       type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR );  \r
+       signal pst_pci          : PciFSM;\r
+       signal nxt_pci          : PciFSM;\r
+\r
+       signal sdata1           : std_logic;\r
+       signal sdata2           : std_logic;\r
+       signal idleNX           : std_logic;\r
+       signal sdata1NX         : std_logic;\r
+       signal sdata2NX         : std_logic;\r
+       signal turnarNX         : std_logic;\r
+       signal idle                     : std_logic;\r
+       signal devselNX_n       : std_logic;\r
+       signal trdyNX_n         : std_logic;\r
+       signal devsel           : std_logic;\r
+       signal trdy                     : std_logic;\r
+       signal adrpci           : std_logic;\r
+       signal acking           : std_logic;\r
+       signal rdcfg            : std_logic;\r
+       signal targOE           : std_logic;\r
+       signal pcidOE           : std_logic;\r
+\r
+\r
+begin\r
+       \r
+    --+-------------------------------------------------------------------------+\r
+    --|  PCI-Whisbone Sequencer                                                                                                        |\r
+    --+-------------------------------------------------------------------------+\r
+       \r
+       \r
+    --+-------------------------------------------------------------+\r
+       --|  FSM PCI-Whisbone                                                                                   |\r
+    --+-------------------------------------------------------------+\r
+               \r
+       PCIFSM_CLOCKED: process( nrst_i, clk_i, nxt_pci )\r
+       begin\r
+       \r
+       if( nrst_i = '0' ) then\r
+                       pst_pci <= PCIIDLE;\r
+               elsif( rising_edge(clk_i) ) then\r
+                       pst_pci <= nxt_pci; \r
+        end if;\r
+    \r
+       end process PCIFSM_CLOCKED;\r
+\r
+\r
+       PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking )\r
+       begin\r
+               \r
+               devselNX_n      <= '1';\r
+               trdyNX_n        <= '1'; \r
+       case pst_pci is\r
+\r
+               when PCIIDLE =>\r
+                       if ( frame_i = '0' ) then       \r
+                                       nxt_pci <= B_BUSY;      \r
+                               else\r
+                                       nxt_pci <= PCIIDLE;\r
+                               end if;         \r
+                               \r
+            when B_BUSY =>\r
+                               if ( adrpci = '0' ) then\r
+                                       nxt_pci <= TURN_AR;\r
+                               else\r
+                                       nxt_pci <= S_DATA1;\r
+                                       devselNX_n <= '0'; \r
+                               end if;\r
+\r
+                   when S_DATA1 =>\r
+                       if ( acking = '1' ) then        \r
+                                       nxt_pci         <= S_DATA2;\r
+                                       devselNX_n      <= '0';                                         \r
+                                       trdyNX_n        <= '0'; \r
+                               else\r
+                                       nxt_pci <= S_DATA1;\r
+                                       devselNX_n <= '0';                                      \r
+                               end if;         \r
+                                                               \r
+                   when S_DATA2 => \r
+                       if ( frame_i = '1' and irdy_i = '0' ) then      \r
+                                       nxt_pci <= TURN_AR;\r
+                               else\r
+                                       nxt_pci <= S_DATA2;\r
+                                       devselNX_n <= '0';                                      \r
+                                       trdyNX_n <= '0';        \r
+                               end if;         \r
+                               \r
+                       when TURN_AR =>\r
+                               if ( frame_i = '1' ) then\r
+                                       nxt_pci <= PCIIDLE;\r
+                               else\r
+                                       nxt_pci <= TURN_AR;\r
+                               end if;\r
+                               \r
+           end case;\r
+        \r
+       end process PCIFSM_COMB;        \r
+\r
+\r
+    --+-------------------------------------------------------------+\r
+       --|  FSM control signals                                                                                |\r
+    --+-------------------------------------------------------------+\r
+\r
+       adrpci <= adrmem_i or adrcfg_i;\r
+       acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and  irdy_i = '0')\r
+                                 else '0'; \r
+\r
+\r
+    --+-------------------------------------------------------------+\r
+       --|  FSM derived Control signals                                                                |\r
+    --+-------------------------------------------------------------+\r
+       idle            <= '1' when ( pst_pci = PCIIDLE ) else '0';\r
+       sdata1          <= '1' when ( pst_pci = S_DATA1 ) else '0';\r
+       sdata2          <= '1' when ( pst_pci = S_DATA2 ) else '0';\r
+       idleNX          <= '1' when ( nxt_pci = PCIIDLE ) else '0';\r
+       sdata1NX        <= '1' when ( nxt_pci = S_DATA1 ) else '0';     \r
+       sdata2NX        <= '1' when ( nxt_pci = S_DATA2 ) else '0';\r
+       turnarNX        <= '1' when ( nxt_pci = TURN_AR ) else '0';\r
+       \r
+\r
+\r
+    --+-------------------------------------------------------------+\r
+       --|  PCI Data Output Enable                                                                             |\r
+    --+-------------------------------------------------------------+\r
+\r
+       PCIDOE_P: process( nrst_i, clk_i, cmd_i(0), sdata1NX, turnarNX )\r
+       begin\r
+\r
+       if ( nrst_i = '0' ) then \r
+                       pcidOE <= '0';\r
+               elsif ( rising_edge(clk_i) ) then \r
+\r
+                       if ( sdata1NX = '1' and cmd_i(0) = '0' ) then\r
+                               pcidOE <= '1';\r
+                       elsif ( turnarNX = '1' ) then\r
+                               pcidOE <= '0';\r
+                       end if;                 \r
+                       \r
+        end if;\r
+\r
+       end process PCIDOE_P;\r
+\r
+       pcidOE_o <= pcidOE;\r
+\r
+\r
+    --+-------------------------------------------------------------+\r
+       --|  PAR Output Enable                                                                                  |\r
+       --|  PCI Read data phase                                                                                |\r
+       --|  PAR is valid 1 cicle after data is valid                                   |\r
+    --+-------------------------------------------------------------+\r
+\r
+       PAROE_P: process( nrst_i, clk_i, cmd_i(0), sdata2NX, turnarNX )\r
+       begin\r
+\r
+       if ( nrst_i = '0' ) then \r
+                       parOE_o <= '0';\r
+               elsif ( rising_edge(clk_i) ) then \r
+\r
+                       if ( ( sdata2NX = '1' or turnarNX = '1' ) and cmd_i(0) = '0' ) then\r
+                               parOE_o <= '1';\r
+                       else\r
+                               parOE_o <= '0';\r
+                       end if;                 \r
+                       \r
+        end if;\r
+               \r
+       end process PAROE_P;\r
+\r
+       \r
+    --+-------------------------------------------------------------+\r
+       --|  Target s/t/s signals OE control                                                    |\r
+    --+-------------------------------------------------------------+\r
+\r
+--     targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0';\r
+       TARGOE_P: process( nrst_i, clk_i, sdata1NX, idleNX )\r
+       begin\r
+\r
+       if ( nrst_i = '0' ) then \r
+                       targOE <= '0';\r
+               elsif ( rising_edge(clk_i) ) then \r
+\r
+                       if ( sdata1NX = '1' ) then\r
+                               targOE <= '1';\r
+                       elsif ( idleNX = '1' ) then\r
+                               targOE <= '0';\r
+                       end if;                 \r
+                       \r
+        end if;\r
+\r
+       end process TARGOE_P;\r
+               \r
+\r
+    --+-------------------------------------------------------------------------+\r
+    --|  WHISBONE outs                                                                                                                 |\r
+    --+-------------------------------------------------------------------------+\r
+                               \r
+       wb_cyc_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' ) else '0';\r
+    wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0';\r
+\r
+       -- PCI(Little endian) to WB(Big endian)\r
+       wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2));\r
+       wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3));        \r
+       -- \r
+       wb_we_o <= cmd_i(0);\r
+       \r
+\r
+    --+-------------------------------------------------------------------------+\r
+       --|  Syncronized PCI outs                                                                                                       |\r
+    --+-------------------------------------------------------------------------+\r
+       \r
+       PCISIG: process( nrst_i, clk_i, devselNX_n, trdyNX_n)\r
+       begin\r
+\r
+               if( nrst_i = '0' ) then \r
+                       devsel          <= '1';\r
+                       trdy            <= '1';\r
+               elsif( rising_edge(clk_i) ) then \r
+               \r
+                       devsel          <= devselNX_n;\r
+                       trdy            <= trdyNX_n;\r
+                       \r
+               end if;\r
+               \r
+       end process PCISIG;\r
+\r
+       devsel_o <= devsel when ( targOE = '1' ) else 'Z';\r
+       trdy_o   <= trdy   when ( targOE = '1' ) else 'Z';\r
+       \r
+\r
+    --+-------------------------------------------------------------------------+\r
+       --|  Other outs                                                                                                                         |\r
+    --+-------------------------------------------------------------------------+\r
+\r
+       --  rd/wr Configuration Space Registers\r
+       wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0';\r
+       rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0';\r
+       rdcfg_o <= rdcfg;\r
+       \r
+       -- LoaD enable signals\r
+       pciadrLD_o <= not frame_i;\r
+       wbdatLD_o  <= wb_ack_i;\r
+\r
+       -- Mux control signals\r
+       wbrgdMX_o <= not rdcfg;\r
+       wbd16MX_o <= '1' when ( cbe_i(3) = '0' or cbe_i(2) = '0' ) else '0';\r
+       \r
+    --+-------------------------------------------------------------------------+\r
+       --|  debug outs                                                                                                                         |\r
+    --+-------------------------------------------------------------------------+\r
+       \r
+       process (nrst_i, clk_i)\r
+       begin\r
+               if ( nrst_i = '0' ) then\r
+                       debug_init <= '0';\r
+                       elsif clk_i'event and clk_i = '1' then\r
+                               if devsel = '0' then\r
+                                       debug_init <= '1';\r
+                               end if;\r
+               end if;\r
+       end process;    \r
+       \r
+       process (nrst_i, clk_i)\r
+       begin\r
+               if ( nrst_i = '0' ) then\r
+                       debug_access <= '0';\r
+                       elsif clk_i'event and clk_i = '1' then\r
+                               if wb_stb_o = '1' then\r
+                                       debug_access <= '1';\r
+                               end if;\r
+               end if;\r
+       end process; \r
+\r
+end rtl;\r
diff --git a/dhwk_old/source/pfs.v b/dhwk_old/source/pfs.v
new file mode 100644 (file)
index 0000000..4746c7d
--- /dev/null
@@ -0,0 +1,11 @@
+module pfs2 (clk, a, b);
+       input clk;
+       input a;
+       output b;
+       reg b;
+
+       always @(posedge clk)
+       begin
+               b <= a;
+       end
+endmodule
diff --git a/dhwk_old/source/pfs.vhd b/dhwk_old/source/pfs.vhd
new file mode 100644 (file)
index 0000000..b2fbc5d
--- /dev/null
@@ -0,0 +1,35 @@
+--+-----------------------------------------+
+--|  pfs                                    |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pfs is
+port (
+   clk         : in std_logic;
+   a           : in std_logic;
+   y           : out std_logic
+
+);   
+end pfs;
+
+architecture rtl of pfs is
+
+       signal a_s      : std_logic;
+       
+begin
+
+       SYNCP: process( clk, a )
+       begin
+       
+        if ( rising_edge(clk) ) then
+                       a_s <= a;
+               end if;
+        
+       end process SYNCP;
+
+       y <= a and (not a_s);
+       
+end rtl;
+
diff --git a/dhwk_old/source/sync.v b/dhwk_old/source/sync.v
new file mode 100644 (file)
index 0000000..798d742
--- /dev/null
@@ -0,0 +1,11 @@
+module sync2 (clk, d, q);
+       input clk;
+       input d;
+       output q;
+       reg     q;
+
+       always @(posedge clk)
+       begin
+               q <= d;
+       end
+endmodule
diff --git a/dhwk_old/source/test.v b/dhwk_old/source/test.v
new file mode 100644 (file)
index 0000000..719afab
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+`define PCIIDLE    1'h0;
+`define B_BUSY     1'h1;
+`define S_DATA1    1'h2;
+`define S_DATA2    1'h3;
+`define TURN_AR    1'h4;
+*/
+
+paramater PCIIDLE    = 1'h0;
+paramater B_BUSY     = 1'h1;
+paramater S_DATA1    = 1'h2;
+paramater S_DATA2    = 1'h3;
+paramater TURN_AR    = 1'h4;
+
diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
new file mode 100644 (file)
index 0000000..7c965c1
--- /dev/null
@@ -0,0 +1,204 @@
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  File:                     top.vhd                                                                         |\r
+--|                                                                                                                                                                                                    |\r
+--|  Components:       pci32lite.vhd                                                                   |\r
+--|                        pciwbsequ.vhd                                                                                                                       |\r
+--|                        pcidmux.vhd                                                                                                                                 |\r
+--|                        pciregs.vhd                                                                                                                                 |\r
+--|                        pcipargen.vhd                                                                                                                               |\r
+--|                        -- Libs --                                                                                                                                  |\r
+--|                        ona.vhd                                                                                                                                             |\r
+--|                                                                                                                                                                                                    |\r
+--|     Description:   RS1 PCI Demo : (TOP) Main file.                                                                                 |\r
+--|                                                                                                                                                                                            |\r
+--|                                                                                                                                                                            |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--|                                                                                                                                                                                                    |\r
+--|  Revision history :                                                                                                                                                                |\r
+--|  Date                Version       Author  Description                                                                                                             |\r
+--|                                                                                                                                                                                                    |\r
+--|                                                                                                                                                                                                    |\r
+--|  To do:                                                                                                                                                                                    |\r
+--|                                                                                                                                                                                                    |\r
+--+-------------------------------------------------------------------------------------------------+\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    LIBRARIES                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    ENTITY                                                                          |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity dhwk is\r
+port (\r
+\r
+    -- General \r
+    PCI_CLK     : in std_logic;\r
+    PCI_nRES    : in std_logic;\r
+    \r
+    -- PCI target 32bits\r
+    PCI_AD      : inout std_logic_vector(31 downto 0);\r
+    PCI_CBE     : in std_logic_vector(3 downto 0);\r
+    PCI_PAR     : out std_logic;  \r
+    PCI_nFRAME  : in std_logic;\r
+    PCI_nIRDY   : in std_logic;\r
+    PCI_nTRDY   : out std_logic;\r
+    PCI_nDEVSEL : out std_logic;\r
+    PCI_nSTOP   : out std_logic;\r
+    PCI_IDSEL   : in std_logic;\r
+    PCI_nPERR   : out std_logic;\r
+    PCI_nSERR   : out std_logic;\r
+    PCI_nINT    : out std_logic;\r
\r
+       -- debug signals\r
+       LED3    : out std_logic;\r
+       LED2    : out std_logic;\r
+       LED4            : out std_logic;\r
+       LED5            : out std_logic\r
+\r
+);\r
+end dhwk;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    ARCHITECTURE                                                            |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+architecture dhwk_arch of dhwk is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    COMPONENTS                                                                      |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+component pci32tlite\r
+port (\r
+\r
+    -- General \r
+    clk33       : in std_logic;\r
+    nrst           : in std_logic;\r
+    \r
+    -- PCI target 32bits\r
+    ad          : inout std_logic_vector(31 downto 0);\r
+    cbe         : in std_logic_vector(3 downto 0);\r
+    par         : out std_logic;  \r
+    frame       : in std_logic;\r
+    irdy        : in std_logic;\r
+    trdy        : out std_logic;\r
+    devsel      : out std_logic;\r
+    stop        : out std_logic;\r
+    idsel       : in std_logic;\r
+    perr        : out std_logic;\r
+    serr        : out std_logic;\r
+    intb        : out std_logic;\r
+      \r
+       -- Master whisbone\r
+    wb_adr_o     : out std_logic_vector(24 downto 1);     \r
+       wb_dat_i     : in std_logic_vector(15 downto 0);\r
+    wb_dat_o     : out std_logic_vector(15 downto 0);\r
+       wb_sel_o     : out std_logic_vector(1 downto 0);\r
+    wb_we_o      : out std_logic;\r
+       wb_stb_o     : out std_logic;\r
+       wb_cyc_o     : out std_logic;\r
+       wb_ack_i     : in std_logic;\r
+       wb_err_i     : in std_logic;\r
+       wb_int_i     : in std_logic;\r
+\r
+       -- debug signals\r
+       debug_init       : out std_logic;\r
+       debug_access : out std_logic \r
+\r
+       );\r
+end component;\r
+\r
+component heartbeat\r
+port (\r
+       clk_i : in std_logic;\r
+       nrst_i : in std_logic;\r
+       led2_o : out std_logic;\r
+       led3_o : out std_logic;\r
+       led4_o : out std_logic;\r
+       led5_o : out std_logic\r
+);\r
+end component;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    CONSTANTS                                                                       |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--|                                                                    SIGNALS                                                                         |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+       signal  wb_adr :                std_logic_vector(24 downto 1);   \r
+       signal  wb_dat_out :    std_logic_vector(15 downto 0);\r
+       signal  wb_dat_in :             std_logic_vector(15 downto 0);\r
+       signal  wb_sel :                std_logic_vector(1 downto 0);\r
+       signal  wb_we :                 std_logic;\r
+       signal  wb_stb :                std_logic;\r
+       signal  wb_cyc :                std_logic;\r
+       signal  wb_ack :                std_logic;\r
+       signal  wb_err :                std_logic;\r
+       signal  wb_int :                std_logic;\r
+\r
+\r
+begin\r
+\r
+--+-----------------------------------------+\r
+--|  PCI Target                                                        |\r
+--+-----------------------------------------+\r
+\r
+u_pci: component pci32tlite\r
+port map(\r
+       clk33 =>                PCI_CLK,\r
+       nrst =>                 PCI_nRES,\r
+       ad =>                   PCI_AD,\r
+       cbe =>                  PCI_CBE,\r
+       par =>                  PCI_PAR,\r
+       frame =>                PCI_nFRAME,\r
+       irdy =>         PCI_nIRDY,\r
+       trdy =>         PCI_nTRDY,\r
+       devsel =>       PCI_nDEVSEL,\r
+       stop =>         PCI_nSTOP,\r
+       idsel =>        PCI_IDSEL,\r
+       perr =>         PCI_nPERR,\r
+       serr =>         PCI_nSERR,\r
+       intb =>         PCI_nINT,\r
+       wb_adr_o =>             wb_adr,    \r
+               wb_dat_i =>             wb_dat_out,\r
+       wb_dat_o =>     wb_dat_in,\r
+               wb_sel_o =>             wb_sel,         \r
+       wb_we_o =>              wb_we,\r
+               wb_stb_o =>             wb_stb, \r
+               wb_cyc_o =>             wb_cyc,\r
+               wb_ack_i =>             wb_ack,\r
+               wb_err_i =>             wb_err,\r
+               wb_int_i =>             wb_int\r
+--             debug_init =>   LED3,\r
+--             debug_access => LED2\r
+               );\r
+\r
+--+-----------------------------------------+\r
+--|  WB-7seg                                                   |\r
+--+-----------------------------------------+\r
+\r
+my_heartbeat: component heartbeat\r
+port map( \r
+       clk_i => PCI_CLK,\r
+       nrst_i => PCI_nRES,\r
+       led2_o => LED2,\r
+       led3_o => LED3,\r
+       led4_o => LED4,\r
+       led5_o => LED5\r
+);\r
+\r
+end dhwk_arch;\r
diff --git a/dhwk_old/source/vga_main.vhd b/dhwk_old/source/vga_main.vhd
new file mode 100644 (file)
index 0000000..ca50c05
--- /dev/null
@@ -0,0 +1,103 @@
+---------------------------------------------------------------------\r
+-- vga_main.vhd  Demo VGA configuration module.\r
+---------------------------------------------------------------------\r
+--     Author: Barron Barnett\r
+--            Copyright 2004 Digilent, Inc.\r
+---------------------------------------------------------------------\r
+--\r
+-- This project is compatible with Xilinx ISE or Xilinx WebPack tools.\r
+--\r
+-- Inputs: \r
+--             mclk  - System Clock\r
+-- Outputs:\r
+--             hs              - Horizontal Sync\r
+--             vs              - Vertical Sync\r
+--             red     - Red Output\r
+--             grn     - Green Output\r
+--             blu     - Blue Output\r
+--\r
+-- This module creates a three line pattern on a vga display using a\r
+-- a vertical refresh rate of 60Hz.  This is done by dividing the\r
+-- system clock in half and using that for the pixel clock.  This in\r
+-- turn drives the vertical sync when the horizontal sync has reached\r
+-- its reset point.  All data displayed is done by basic value\r
+-- comparisons.\r
+------------------------------------------------------------------------\r
+-- Revision History:\r
+--      07/01/2004(BarronB): created\r
+------------------------------------------------------------------------\r
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+\r
+entity vgaController is\r
+    Port ( mclk : in std_logic;\r
+           hs : out std_logic;\r
+           vs : out std_logic;\r
+           red : out std_logic;\r
+           grn : out std_logic;\r
+           blu : out std_logic);\r
+end vgaController;\r
+\r
+architecture Behavioral of vgaController is\r
+\r
+\r
+       constant hpixels                : std_logic_vector(9 downto 0) := "1100100000";  --Value of pixels in a horizontal line\r
+       constant vlines         : std_logic_vector(9 downto 0) := "1000001001";  --Number of horizontal lines in the display\r
+       \r
+       constant hbp                    : std_logic_vector(9 downto 0) := "0010010000";  --Horizontal back porch\r
+       constant hfp                    : std_logic_vector(9 downto 0) := "1100010000";  --Horizontal front porch\r
+       constant        vbp                     : std_logic_vector(9 downto 0) := "0000011111";  --Vertical back porch\r
+       constant vfp                    : std_logic_vector(9    downto 0) := "0111111111";       --Vertical front porch\r
+       \r
+       signal hc, vc                   : std_logic_vector(9 downto 0);                                          --These are the Horizontal and Vertical counters\r
+       signal clkdiv                   : std_logic;                                                                                             --Clock divider\r
+       signal vidon                    : std_logic;                                                                                             --Tells whether or not its ok to display data\r
+       signal vsenable         : std_logic;                                                                                             --Enable for the Vertical counter\r
+\r
+begin\r
+       --This cuts the 50Mhz clock in half\r
+       process(mclk)\r
+               begin\r
+                       if(mclk = '1' and mclk'EVENT) then\r
+                               clkdiv <= not clkdiv;\r
+                       end if;\r
+               end process;                                                                                                                                                    \r
+\r
+       --Runs the horizontal counter\r
+       process(clkdiv)\r
+               begin\r
+                       if(clkdiv = '1' and clkdiv'EVENT) then\r
+                               if hc = hpixels then                                                                                                             --If the counter has reached the end of pixel count\r
+                                       hc <= "0000000000";                                                                                                      --reset the counter\r
+                                       vsenable <= '1';                                                                                                                 --Enable the vertical counter to increment\r
+                               else\r
+                                       hc <= hc + 1;                                                                                                                    --Increment the horizontal counter\r
+                                       vsenable <= '0';                                                                                                                 --Leave the vsenable off\r
+                               end if;\r
+               end if;\r
+       end process;\r
+\r
+       hs <= '1' when hc(9 downto 7) = "000" else '0';                                                          --Horizontal Sync Pulse\r
+\r
+       process(clkdiv)\r
+       begin\r
+               if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then                        --Increment when enabled\r
+                       if vc = vlines then                                                                                                                      --Reset when the number of lines is reached\r
+                               vc <= "0000000000";\r
+                       else vc <= vc + 1;                                                                                                                       --Increment the vertical counter\r
+                       end if;\r
+               end if;\r
+       end process;\r
+\r
+       vs <= '1' when vc(9 downto 1) = "000000000" else '0';                                            --Vertical Sync Pulse\r
+\r
+       red <= '1' when (hc = "1010101100" and vidon ='1') else '0';                     --Red pixel on at a specific horizontal count\r
+       grn <= '1' when (hc = "0100000100" and vidon ='1') else '0';                     --Green pixel on at a specific horizontal count\r
+       blu <= '1' when (vc = "0100100001" and vidon ='1') else '0';                     --Blue pixel on at a specific vertical count\r
+\r
+       vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0';        --Enable video out when within the porches\r
+\r
+end Behavioral;\r
diff --git a/dhwk_old/source/wb_7seg.v b/dhwk_old/source/wb_7seg.v
new file mode 100644 (file)
index 0000000..a378eb3
--- /dev/null
@@ -0,0 +1,87 @@
+module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
+       wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED);\r
+\r
+       input clk_i;\r
+       input nrst_i;\r
+       input [24:1] wb_adr_i;\r
+       output [15:0] wb_dat_o;\r
+       input [15:0] wb_dat_i;\r
+       input [1:0] wb_sel_i;\r
+       input wb_we_i;\r
+       input wb_stb_i;\r
+       input wb_cyc_i;\r
+       output wb_ack_o;\r
+       output wb_err_o;\r
+       output wb_int_o;\r
+       output reg [3:0] DISP_SEL;\r
+       output reg [6:0] DISP_LED;\r
+\r
+       reg [15:0]      data_reg;\r
+       reg     [6:0]   disp_cnt;\r
+       reg     [3:0]   disp_data;\r
+       wire    [6:0]   disp_data_led;\r
+       reg     [3:0]   disp_pos;\r
+\r
+       always @(posedge clk_i or negedge nrst_i)\r
+       begin\r
+               if (nrst_i == 0)\r
+                       data_reg <= 16'hABCD;\r
+               else \r
+                       if (wb_stb_i && wb_we_i)\r
+                               data_reg <= wb_dat_i;\r
+       end\r
+\r
+       assign wb_ack_o = wb_stb_i;\r
+       assign wb_err_o = 1'b0;\r
+       assign wb_int_o = 1'b0;\r
+       assign wb_dat_o = data_reg;\r
+\r
+       always @(posedge clk_i or negedge nrst_i)\r
+       begin\r
+               if (nrst_i == 0)\r
+                       disp_cnt <= 7'b0000000;\r
+               else \r
+                       disp_cnt <= disp_cnt + 1;\r
+       end\r
+\r
+       always @(posedge clk_i or negedge nrst_i)\r
+       begin\r
+               if (nrst_i == 0)\r
+                       disp_pos <= 4'b0010;\r
+               else \r
+                       if (disp_cnt == 7'b1111111)\r
+                               disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]};\r
+       end\r
+\r
+       always @(posedge clk_i or negedge nrst_i)\r
+       begin\r
+               if (nrst_i == 0)\r
+                       disp_data <= 4'b0000;\r
+               else \r
+                       case (DISP_SEL)\r
+                               4'b1000: disp_data <= data_reg[3:0];\r
+                               4'b0100: disp_data <= data_reg[7:4];\r
+                               4'b0010: disp_data <= data_reg[11:8];\r
+                               4'b0001: disp_data <= data_reg[15:12];\r
+                       endcase\r
+       end\r
+\r
+       disp_dec u0 (disp_data, disp_data_led);\r
+\r
+       always @(posedge clk_i or negedge nrst_i)\r
+       begin\r
+               if (nrst_i == 0)\r
+                       DISP_LED <= 7'b0000000;\r
+               else \r
+                       DISP_LED <= disp_data_led;\r
+       end\r
+\r
+       always @(posedge clk_i or negedge nrst_i)\r
+       begin\r
+               if (nrst_i == 0)\r
+                       DISP_SEL <= 0;\r
+               else \r
+                       DISP_SEL <= disp_pos;\r
+       end\r
+\r
+endmodule\r
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