dhwk

[raggedstone] / dhwk_old / source / pcidec.v

diff --git a/dhwk_old/source/pcidec.v b/dhwk_old/source/pcidec.v
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+//  Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r
+//  Copyright (C) 2006 Jeff Carr, jcarr@opencores.org\r
+//     Copyleft GPL v2\r
+\r
+module pcidec_new (clk_i, nrst_i, ad_i, cbe_i, idsel_i, bar0_i, memEN_i,\r
+       pciadrLD_i, adrcfg_o, adrmem_o, adr_o, cmd_o);\r
+\r
+       // General \r
+       input clk_i;\r
+       input nrst_i;\r
+       // pci \r
+       input [31:0] ad_i;\r
+       input [3:0] cbe_i;\r
+       input idsel_i;\r
+       // control\r
+       input [31:25] bar0_i;\r
+       input memEN_i;\r
+       input pciadrLD_i;\r
+       output adrcfg_o;\r
+       output adrmem_o;\r
+       output [24:1] adr_o;\r
+       output [3:0] cmd_o;\r
+\r
+       reg [31:0] adr;\r
+       reg [3:0] cmd;\r
+       reg idsel_s;\r
+       wire a1;\r
+\r
+       //+-------------------------------------------------------------------------+\r
+       //|  Load PCI Signals                                                                                                           |\r
+       //+-------------------------------------------------------------------------+\r
+\r
+       always @( negedge nrst_i or posedge clk_i )\r
+       begin\r
+               if( nrst_i == 0 )\r
+               begin\r
+                       adr <= 23'b1111_1111_1111_1111_1111_111;\r
+                       cmd <= 3'b111;\r
+                       idsel_s <= 1'b0;\r
+               end\r
+               else\r
+                       if ( pciadrLD_i == 1 )\r
+                       begin\r
+                               adr <= ad_i;\r
+                               cmd <= cbe_i;\r
+                               idsel_s <= idsel_i;\r
+                       end\r
+       end\r
+\r
+       assign adrmem_o = (\r
+               ( memEN_i == 1'b1 ) &&\r
+               ( adr [31:25] == bar0_i ) &&\r
+               ( adr [1:0] == 2'b00 ) &&\r
+               ( cmd [3:1] == 3'b011 )\r
+       ) ? 1'b1 : 1'b0;\r
+\r
+       assign adrcfg_o = (\r
+               ( idsel_s == 1'b1 ) &&\r
+               ( adr [1:0] == 2'b00 ) &&\r
+               ( cmd [3:1] == 3'b101 )\r
+       ) ? 1'b1 : 1'b0;\r
+\r
+       assign a1 = ~ ( cbe_i [3] && cbe_i [2] );\r
+       assign adr_o = {adr [24:2], a1};\r
+       assign cmd_o = cmd;\r
+\r
+endmodule\r