dhwk

[raggedstone] / dhwk_old / source / pcidmux.v

diff --git a/dhwk_old/source/pcidmux.v b/dhwk_old/source/pcidmux.v
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+// Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r
+// Copyright (C) 2006 Jeff Carr, jcarr@opencores.org\r
+//\r
+// I think what this does is handle 16 vs 32 bit pci accesses\r
+\r
+module pcidmux ( clk_i, nrst_i, d_io, pcidatout_o, pcidOE_i, wbdatLD_i, wbrgdMX_i,\r
+       wbd16MX_i, wb_dat_i, wb_dat_o, rg_dat_i, rg_dat_o);\r
+\r
+       input clk_i;\r
+       input nrst_i;\r
+\r
+       // d_io                 : inout std_logic_vector(31 downto 0);\r
+       inout [31:0] d_io;\r
+       output [31:0] pcidatout_o;\r
+\r
+       input pcidOE_i;\r
+       input wbdatLD_i;\r
+       input wbrgdMX_i;\r
+       input wbd16MX_i;\r
+\r
+       input [15:0] wb_dat_i;\r
+       output [15:0] wb_dat_o;\r
+       input [31:0] rg_dat_i;\r
+       output [31:0] rg_dat_o;\r
+\r
+       wire [31:0] pcidatin;\r
+       wire [31:0] pcidatout;\r
+\r
+       reg [15:0] wb_dat_is;\r
+\r
+       // always @(negedge nrst_i or posedge clk_i or posedge wbdatLD_i or posedge wb_dat_i)\r
+       always @(negedge nrst_i or posedge clk_i)\r
+       begin\r
+               if ( nrst_i == 0 )\r
+                       wb_dat_is <= 16'b1111_1111_1111_1111;\r
+               else\r
+                       if ( wbdatLD_i == 1 )\r
+                               wb_dat_is <= wb_dat_i;\r
+       end\r
+\r
+       assign pcidatin = d_io;\r
+       assign d_io = (pcidOE_i == 1'b1 ) ? pcidatout : 32'bZ;\r
+\r
+       assign pcidatout [31:24] = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0]  : rg_dat_i [31:24];\r
+       assign pcidatout [23:16] = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [23:16];\r
+       assign pcidatout [15:8]  = (wbrgdMX_i == 1'b1) ? wb_dat_is [7:0]  : rg_dat_i [15:8];\r
+       assign pcidatout [7:0]   = (wbrgdMX_i == 1'b1) ? wb_dat_is [15:8] : rg_dat_i [7:0];\r
+\r
+       assign pcidatout_o = pcidatout;\r
+       assign rg_dat_o = pcidatin;\r
+\r
+       assign wb_dat_o [15:8] = (wbd16MX_i == 1'b1) ? pcidatin [23:16] : pcidatin [7:0];\r
+       assign wb_dat_o [7:0]  = (wbd16MX_i == 1'b1) ? pcidatin [31:24] : pcidatin [15:8];\r
+\r
+endmodule \r