dhwk

[raggedstone] / dhwk_old / source / pcipargen.v

diff --git a/dhwk_old/source/pcipargen.v b/dhwk_old/source/pcipargen.v
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+//\r
+//                  PCI Parity Generator.\r
+//\r
+// PCI Target generates PAR in the data phase of a read cycle. \r
+// The 1's sum on AD, CBE and PAR is even.\r
+//\r
+//   Date                Version       Author  Description\r
+//   2005-05-13   R00A00       PAU             First alfa revision     (eng)\r
+//\r
+//  Copyright (C) 2005 Peio Azkarate, peio@opencores.org\r
+//\r
+//   This source file is free software; you can redistribute it     |\r
+//   and/or modify it under the terms of the GNU Lesser General     |\r
+//   Public License as published by the Free Software Foundation;   |\r
+//   either version 2.1 of the License, or (at your option) any     |\r
+//   later version.                                                 |\r
+\r
+\r
+module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o);\r
+\r
+       input clk_i;\r
+       input [31:0] pcidatout_i;\r
+       input [3:0] cbe_i;\r
+       input parOE_i;\r
+       output par_o;\r
+\r
+\r
+       wire [31:0] d;\r
+       wire pardat;\r
+       wire parcbe;\r
+       wire par;\r
+       wire par_s;\r
+\r
+       assign d = pcidatout_i;\r
+\r
+       assign pardat = d[0]  ^ d[1]  ^ d[2]  ^ d[3]  ^ d[4]  ^ d[5]  ^ d[6]  ^ d[7]  ^ \r
+                          d[8]  ^ d[9]  ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ \r
+                          d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ \r
+                          d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];\r
+                                               \r
+       assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3]; \r
+\r
+       assign par = pardat ^ parcbe;\r
+\r
+    // PAR\r
+       assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ;\r
+\r
+endmodule\r
+/*\r
+component sync\r
+port (\r
+    clk             : in std_logic;\r
+    d           : in std_logic;\r
+    q               : out std_logic\r
+);\r
+end component;\r
+\r
+component sync2\r
+port (\r
+    clk             : in std_logic;\r
+    d           : in std_logic;\r
+    q               : out std_logic\r
+);\r
+end component;\r
+\r
+begin\r
+\r
+\r
+\r
+    u1: sync2 port map (\r
+               clk => clk_i,\r
+               d => par,\r
+               q => par_s\r
+       );\r
+       \r
+\r
+\r
+\r
+end rtl;\r
+*/\r