dos2unix *.vhd

[raggedstone] / dhwk / source / Verg_2.vhd

diff --git a/dhwk/source/Verg_2.vhd b/dhwk/source/Verg_2.vhd
index 39d51acc147504371f2b2156232c049cf4107a74..94aa714cee8b6e863dbaf10f7e27899a6eff6f95 100644 (file)
--- a/dhwk/source/Verg_2.vhd
+++ b/dhwk/source/Verg_2.vhd
@@ -1,31 +1,31 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_2.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity VERG_2  is\r
-       port\r
-       (\r
-       IN_A            :in             std_logic_vector(1 downto 0);\r
-       IN_B            :in             std_logic_vector(1 downto 0);\r
-       GLEICH  :out    std_logic\r
-       );\r
-end entity VERG_2 ;\r
-\r
-architecture VERG_2_DESIGN of VERG_2 is\r
-\r
-begin\r
-\r
-       process (IN_A,IN_B) \r
-       begin \r
-\r
-               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
-                       else                                                                                    GLEICH  <=      '0';   \r
-               end if;\r
-\r
-       end process;\r
-\r
-end architecture VERG_2_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_2.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity VERG_2  is
+       port
+       (
+       IN_A            :in             std_logic_vector(1 downto 0);
+       IN_B            :in             std_logic_vector(1 downto 0);
+       GLEICH  :out    std_logic
+       );
+end entity VERG_2 ;
+
+architecture VERG_2_DESIGN of VERG_2 is
+
+begin
+
+       process (IN_A,IN_B) 
+       begin 
+
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
+                       else                                                                                    GLEICH  <=      '0';   
+               end if;
+
+       end process;
+
+end architecture VERG_2_DESIGN ;