--- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity CONFIG_SPACE_HEADER is\r
- Port ( AD_REG : In std_logic_vector (31 downto 0);\r
- ADDR_REG : In std_logic_vector (31 downto 0);\r
- CBE_REGn : In std_logic_vector (3 downto 0);\r
- CF_RD_COM : In std_logic;\r
- CF_WR_COM : In std_logic;\r
- IRDY_REGn : In std_logic;\r
- PCI_CLOCK : In std_logic;\r
- PCI_RSTn : In std_logic;\r
- PERR : In std_logic;\r
- REVISION_ID : In std_logic_vector (7 downto 0);\r
- SERR : In std_logic;\r
- TRDYn : In std_logic;\r
- VENDOR_ID : In std_logic_vector (15 downto 0);\r
- CONF_DATA : Out std_logic_vector (31 downto 0);\r
- CONF_DATA_04H : Out std_logic_vector (31 downto 0);\r
- CONF_DATA_10H : Out std_logic_vector (31 downto 0) );\r
-end CONFIG_SPACE_HEADER;\r
-\r
-architecture SCHEMATIC of CONFIG_SPACE_HEADER is\r
-\r
- SIGNAL gnd : std_logic := '0';\r
- SIGNAL vcc : std_logic := '1';\r
-\r
- signal CONF_WR_04H : std_logic;\r
- signal CONF_WR_10H : std_logic;\r
- signal CONF_WR_3CH : std_logic;\r
- signal CONF_READ_SEL : std_logic_vector (2 downto 0);\r
- signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);\r
- signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);\r
- signal CONF_DATA_3CH : std_logic_vector (31 downto 0);\r
- signal CONF_DATA_08H : std_logic_vector (31 downto 0);\r
- signal CONF_DATA_00H : std_logic_vector (31 downto 0);\r
-\r
- component CONFIG_MUX_0\r
- Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);\r
- CONF_DATA_04H : In std_logic_vector (31 downto 0);\r
- CONF_DATA_08H : In std_logic_vector (31 downto 0);\r
- CONF_DATA_10H : In std_logic_vector (31 downto 0);\r
- CONF_DATA_3CH : In std_logic_vector (31 downto 0);\r
- READ_SEL : In std_logic_vector (2 downto 0);\r
- CONF_DATA : Out std_logic_vector (31 downto 0) );\r
- end component;\r
-\r
- component CONFIG_RD_0\r
- Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
- CF_RD_COM : In std_logic;\r
- READ_SEL : Out std_logic_vector (2 downto 0) );\r
- end component;\r
-\r
- component CONFIG_WR_0\r
- Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
- CF_WR_COM : In std_logic;\r
- IRDY_REGn : In std_logic;\r
- TRDYn : In std_logic;\r
- CONF_WR_04H : Out std_logic;\r
- CONF_WR_10H : Out std_logic;\r
- CONF_WR_3CH : Out std_logic );\r
- end component;\r
-\r
- component CONFIG_3CH\r
- Port ( AD_REG : In std_logic_vector (31 downto 0);\r
- CBE_REGn : In std_logic_vector (3 downto 0);\r
- CONF_WR_3CH : In std_logic;\r
- PCI_CLOCK : In std_logic;\r
- PCI_RSTn : In std_logic;\r
- CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );\r
- end component;\r
-\r
- component CONFIG_10H\r
- Port ( AD_REG : In std_logic_vector (31 downto 0);\r
- CBE_REGn : In std_logic_vector (3 downto 0);\r
- CONF_WR_10H : In std_logic;\r
- PCI_CLOCK : In std_logic;\r
- PCI_RSTn : In std_logic;\r
- CONF_DATA_10H : Out std_logic_vector (31 downto 0) );\r
- end component;\r
-\r
- component CONFIG_08H\r
- Port ( REVISION_ID : In std_logic_vector (7 downto 0);\r
- CONF_DATA_08H : Out std_logic_vector (31 downto 0) );\r
- end component;\r
-\r
- component CONFIG_00H\r
- Port ( VENDOR_ID : In std_logic_vector (15 downto 0);\r
- CONF_DATA_00H : Out std_logic_vector (31 downto 0) );\r
- end component;\r
-\r
- component CONFIG_04H\r
- Port ( AD_REG : In std_logic_vector (31 downto 0);\r
- CBE_REGn : In std_logic_vector (3 downto 0);\r
- CONF_WR_04H : In std_logic;\r
- PCI_CLOCK : In std_logic;\r
- PCI_RSTn : In std_logic;\r
- PERR : In std_logic;\r
- SERR : In std_logic;\r
- CONF_DATA_04H : Out std_logic_vector (31 downto 0) );\r
- end component;\r
-\r
-begin\r
-\r
- CONF_DATA_04H <= CONF_DATA_04H_DUMMY;\r
- CONF_DATA_10H <= CONF_DATA_10H_DUMMY;\r
-\r
- I10 : CONFIG_MUX_0\r
- Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),\r
- CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),\r
- CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),\r
- CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),\r
- CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),\r
- READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),\r
- CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );\r
- I9 : CONFIG_RD_0\r
- Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
- CF_RD_COM=>CF_RD_COM,\r
- READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );\r
- I8 : CONFIG_WR_0\r
- Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
- CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,\r
- TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,\r
- CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );\r
- I6 : CONFIG_3CH\r
- Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
- CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,\r
- PCI_RSTn=>PCI_RSTn,\r
- CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );\r
- I5 : CONFIG_10H\r
- Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
- CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,\r
- PCI_RSTn=>PCI_RSTn,\r
- CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );\r
- I4 : CONFIG_08H\r
- Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),\r
- CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );\r
- I3 : CONFIG_00H\r
- Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
- CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );\r
- I2 : CONFIG_04H\r
- Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
- CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
- CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,\r
- PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,\r
- CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity CONFIG_SPACE_HEADER is
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ ADDR_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ CF_RD_COM : In std_logic;
+ CF_WR_COM : In std_logic;
+ IRDY_REGn : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR : In std_logic;
+ REVISION_ID : In std_logic_vector (7 downto 0);
+ SERR : In std_logic;
+ TRDYn : In std_logic;
+ VENDOR_ID : In std_logic_vector (15 downto 0);
+ CONF_DATA : Out std_logic_vector (31 downto 0);
+ CONF_DATA_04H : Out std_logic_vector (31 downto 0);
+ CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
+end CONFIG_SPACE_HEADER;
+
+architecture SCHEMATIC of CONFIG_SPACE_HEADER is
+
+ SIGNAL gnd : std_logic := '0';
+ SIGNAL vcc : std_logic := '1';
+
+ signal CONF_WR_04H : std_logic;
+ signal CONF_WR_10H : std_logic;
+ signal CONF_WR_3CH : std_logic;
+ signal CONF_READ_SEL : std_logic_vector (2 downto 0);
+ signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
+ signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
+ signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
+ signal CONF_DATA_08H : std_logic_vector (31 downto 0);
+ signal CONF_DATA_00H : std_logic_vector (31 downto 0);
+
+ component CONFIG_MUX_0
+ Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
+ CONF_DATA_04H : In std_logic_vector (31 downto 0);
+ CONF_DATA_08H : In std_logic_vector (31 downto 0);
+ CONF_DATA_10H : In std_logic_vector (31 downto 0);
+ CONF_DATA_3CH : In std_logic_vector (31 downto 0);
+ READ_SEL : In std_logic_vector (2 downto 0);
+ CONF_DATA : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component CONFIG_RD_0
+ Port ( ADDR_REG : In std_logic_vector (31 downto 0);
+ CF_RD_COM : In std_logic;
+ READ_SEL : Out std_logic_vector (2 downto 0) );
+ end component;
+
+ component CONFIG_WR_0
+ Port ( ADDR_REG : In std_logic_vector (31 downto 0);
+ CF_WR_COM : In std_logic;
+ IRDY_REGn : In std_logic;
+ TRDYn : In std_logic;
+ CONF_WR_04H : Out std_logic;
+ CONF_WR_10H : Out std_logic;
+ CONF_WR_3CH : Out std_logic );
+ end component;
+
+ component CONFIG_3CH
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ CONF_WR_3CH : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component CONFIG_10H
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ CONF_WR_10H : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component CONFIG_08H
+ Port ( REVISION_ID : In std_logic_vector (7 downto 0);
+ CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component CONFIG_00H
+ Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
+ CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
+ end component;
+
+ component CONFIG_04H
+ Port ( AD_REG : In std_logic_vector (31 downto 0);
+ CBE_REGn : In std_logic_vector (3 downto 0);
+ CONF_WR_04H : In std_logic;
+ PCI_CLOCK : In std_logic;
+ PCI_RSTn : In std_logic;
+ PERR : In std_logic;
+ SERR : In std_logic;
+ CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
+ end component;
+
+begin
+
+ CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
+ CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
+
+ I10 : CONFIG_MUX_0
+ Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
+ CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
+ CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
+ CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
+ CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
+ READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
+ CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
+ I9 : CONFIG_RD_0
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CF_RD_COM=>CF_RD_COM,
+ READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
+ I8 : CONFIG_WR_0
+ Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+ CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
+ TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
+ CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
+ I6 : CONFIG_3CH
+ Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn,
+ CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
+ I5 : CONFIG_10H
+ Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn,
+ CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
+ I4 : CONFIG_08H
+ Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
+ CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
+ I3 : CONFIG_00H
+ Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+ CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
+ I2 : CONFIG_04H
+ Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+ CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+ CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
+ PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
+ CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
+
+end SCHEMATIC;
projects / raggedstone / blobdiff