+= ignore
authorsithglan <sithglan>
Sun, 11 Feb 2007 22:01:03 +0000 (22:01 +0000)
committersithglan <sithglan>
Sun, 11 Feb 2007 22:01:03 +0000 (22:01 +0000)
dhwk_old/.cvsignore [new file with mode: 0644]
dhwk_old/dhwk.prj

diff --git a/dhwk_old/.cvsignore b/dhwk_old/.cvsignore
new file mode 100644 (file)
index 0000000..c9cbd7c
--- /dev/null
@@ -0,0 +1,33 @@
+_impact*
+_ngo
+dhwk-xcf02s.mcs
+dhwk-xcf02s.prm
+dhwk-xcf04s.mcs
+dhwk-xcf04s.prm
+dhwk.bgn
+dhwk.bit
+dhwk.bld
+dhwk.drc
+dhwk.lso
+dhwk.ncd
+dhwk.ngc
+dhwk.ngd
+dhwk.ngr
+dhwk.pad
+dhwk.par
+dhwk.pcf
+dhwk.syr
+dhwk.twr
+dhwk.twx
+dhwk.unroutes
+dhwk.xpi
+dhwk_map.map
+dhwk_map.mrp
+dhwk_map.ncd
+dhwk_map.ngm
+dhwk_pad.csv
+dhwk_pad.txt
+dhwk_summary.xml
+dhwk_usage.xml
+timing.twr
+xst
index 148efef398c9a6286608e1dbce5874ac7f8fdd15..74e10b37d96dc32ef45d58800e67328f1c9a67a1 100644 (file)
@@ -1,6 +1,7 @@
 verilog work "source/sync.v"
 verilog work "source/pcidec.v"
 verilog work "source/pcidmux.v"
+verilog work "source/generic_fifo_sc_a.v"
 
 verilog work "source/pciwbsequ.v"
 verilog work "source/pcipargen.v"
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