rollback
authorsithglan <sithglan>
Sun, 11 Mar 2007 12:24:35 +0000 (12:24 +0000)
committersithglan <sithglan>
Sun, 11 Mar 2007 12:24:35 +0000 (12:24 +0000)
27 files changed:
dhwk/dhwk.prj
dhwk/source/par_ser_con.vhd
dhwk/source/pci/address_register.vhd
dhwk/source/pci/comm_dec.vhd
dhwk/source/pci/comm_fsm.vhd
dhwk/source/pci/config_00h.vhd [new file with mode: 0644]
dhwk/source/pci/config_04h.vhd [new file with mode: 0644]
dhwk/source/pci/config_08h.vhd [new file with mode: 0644]
dhwk/source/pci/config_10h.vhd [new file with mode: 0644]
dhwk/source/pci/config_3Ch.vhd [new file with mode: 0644]
dhwk/source/pci/config_mux_0.vhd [new file with mode: 0644]
dhwk/source/pci/config_rd_0.vhd [new file with mode: 0644]
dhwk/source/pci/config_space_header.vhd
dhwk/source/pci/config_wr_0.vhd [new file with mode: 0644]
dhwk/source/pci/connecting_fsm.vhd
dhwk/source/pci/cont_fsm.vhd
dhwk/source/pci/fifo_io_control.vhd
dhwk/source/pci/flag_bus.vhd
dhwk/source/pci/interrupt.vhd
dhwk/source/pci/io_reg.vhd
dhwk/source/pci/parity_out.vhd
dhwk/source/pci/pci_interface.vhd
dhwk/source/pci/verg_2.vhd [new file with mode: 0644]
dhwk/source/pci/verg_4.vhd [new file with mode: 0644]
dhwk/source/pci/verg_8.vhd [new file with mode: 0644]
dhwk/source/pci/vergleich.vhd [new file with mode: 0644]
dhwk/source/ser_par_con.vhd

index 33b048cb0fb300f20c6ac0dc44f964ec366926a5..113fec6997e53a7fddcccee7a6ebbf67c745d5a6 100644 (file)
@@ -3,7 +3,15 @@ vhdl work "source/ser_par_con.vhd"
 vhdl work "source/pci/address_register.vhd"
 vhdl work "source/pci/comm_dec.vhd"
 vhdl work "source/pci/comm_fsm.vhd"
 vhdl work "source/pci/address_register.vhd"
 vhdl work "source/pci/comm_dec.vhd"
 vhdl work "source/pci/comm_fsm.vhd"
+vhdl work "source/pci/config_00h.vhd"
+vhdl work "source/pci/config_04h.vhd"
+vhdl work "source/pci/config_08h.vhd"
+vhdl work "source/pci/config_10h.vhd"
+vhdl work "source/pci/config_3Ch.vhd"
+vhdl work "source/pci/config_mux_0.vhd"
+vhdl work "source/pci/config_rd_0.vhd"
 vhdl work "source/pci/config_space_header.vhd"
 vhdl work "source/pci/config_space_header.vhd"
+vhdl work "source/pci/config_wr_0.vhd"
 vhdl work "source/pci/connecting_fsm.vhd"
 vhdl work "source/pci/cont_fsm.vhd"
 vhdl work "source/pci/data_mux.vhd"
 vhdl work "source/pci/connecting_fsm.vhd"
 vhdl work "source/pci/cont_fsm.vhd"
 vhdl work "source/pci/data_mux.vhd"
@@ -28,3 +36,7 @@ vhdl work "source/pci/synplify.vhd"
 vhdl work "source/pci/top.vhd"
 vhdl work "source/pci/user_io.vhd"
 vhdl work "source/pci/ven_rev_id.vhd"
 vhdl work "source/pci/top.vhd"
 vhdl work "source/pci/user_io.vhd"
 vhdl work "source/pci/ven_rev_id.vhd"
+vhdl work "source/pci/verg_2.vhd"
+vhdl work "source/pci/verg_4.vhd"
+vhdl work "source/pci/verg_8.vhd"
+vhdl work "source/pci/vergleich.vhd"
index 155bb2729077b6a092582ab5f98317acd5e27b51..2f183d9c07f66355cc3012abd54b03179e63e94c 100644 (file)
@@ -1,4 +1,4 @@
--- $Id: par_ser_con.vhd,v 1.2 2007-03-11 09:14:58 sithglan Exp $
+-- $Id: par_ser_con.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
 
 library ieee;
 use ieee.std_logic_1164.all;
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -43,7 +43,7 @@ begin
 
         process(PCI_CLOCK)
         begin
 
         process(PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
@@ -115,7 +115,7 @@ begin
 
         process(PCI_CLOCK)
         begin
 
         process(PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         SYNC <= SPC_RDY_IN;
                 end if;
         end process;
                         SYNC <= SPC_RDY_IN;
                 end if;
         end process;
index 56c480eb2087d0c92e211c94a3a399764eec05b2..99360c5f65d419438adaa9dd7297a781f60ae2a7 100644 (file)
@@ -25,7 +25,7 @@ begin
                if      PCI_RSTn = '0'  then
                         REG_ADDR       <= X"00000000";
 
                if      PCI_RSTn = '0'  then
                         REG_ADDR       <= X"00000000";
 
-               elsif (rising_edge(PCI_CLOCK)) then
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
                        if LOAD_ADDR_REG = '1' then
                                 REG_ADDR       <=      AD_REG;
                        else
                        if LOAD_ADDR_REG = '1' then
                                 REG_ADDR       <=      AD_REG;
                        else
index 2cd7bebb7ef2b13f25ab019c7f8efe19a2f3c0f0..c28d22224dd8631f0a2c758f15e2e4176e9302b3 100644 (file)
@@ -89,7 +89,7 @@ begin
         process (PCI_CLOCK, PCI_RSTn)
         begin
                 if PCI_RSTn = '0' then FRAME_REG_REGn <= '1';
         process (PCI_CLOCK, PCI_RSTn)
         begin
                 if PCI_RSTn = '0' then FRAME_REG_REGn <= '1';
-        elsif (rising_edge(PCI_CLOCK)) then
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
 
                 FRAME_REG_REGn <= FRAME_REGn;
 
 
                 FRAME_REG_REGn <= FRAME_REGn;
 
index 773512898f5e45cbf676db2a9334de7f1c25e1a3..82ecece801a6b2b304c7c24e07cec11d8428d31c 100644 (file)
@@ -63,7 +63,7 @@ begin
         if PCI_RSTn = '0' then
                 COMM_STATE <= "0000";
 
         if PCI_RSTn = '0' then
                 COMM_STATE <= "0000";
 
-        elsif (rising_edge(PCI_CLOCK)) then
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
                 case COMM_STATE is
                 when ST_IDLE_COMM =>
                         if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
                 case COMM_STATE is
                 when ST_IDLE_COMM =>
                         if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
diff --git a/dhwk/source/pci/config_00h.vhd b/dhwk/source/pci/config_00h.vhd
new file mode 100644 (file)
index 0000000..98b4532
--- /dev/null
@@ -0,0 +1,28 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_00H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_00H is
+        port
+        (
+                VENDOR_ID :in std_logic_vector (15 downto 0);
+                CONF_DATA_00H :out std_logic_vector (31 downto 0)
+        );
+end entity CONFIG_00H;
+
+architecture CONFIG_00H_DESIGN of CONFIG_00H is
+
+ -- PCI Configuration Space Header Addr : HEX 00 --
+
+        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";--????
+        --constant CONF_VENDOR_ID :std_logic_vector(15 downto 0) := X"BAFF";--????
+
+begin
+
+        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
+
+end architecture CONFIG_00H_DESIGN;
diff --git a/dhwk/source/pci/config_04h.vhd b/dhwk/source/pci/config_04h.vhd
new file mode 100644 (file)
index 0000000..70d0c9f
--- /dev/null
@@ -0,0 +1,113 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_04H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_04H is
+        port
+        (
+                PCI_CLOCK :in std_logic;
+                PCI_RSTn :in std_logic;
+                SERR :in std_logic;
+                PERR :in std_logic;
+                AD_REG :in std_logic_vector(31 downto 0);
+                CBE_REGn :in std_logic_vector( 3 downto 0);
+                CONF_WR_04H :in std_logic;
+                CONF_DATA_04H :out std_logic_vector(31 downto 0)
+        );
+end entity CONFIG_04H;
+
+architecture CONFIG_04H_DESIGN of CONFIG_04H is
+
+        signal CONF_STATUS :std_logic_vector(31 downto 16);
+        signal CONF_COMMAND :std_logic_vector(15 downto 0);
+
+begin
+
+ --*******************************************************************
+ --************* PCI Configuration Space Header "STATUS" *************
+ --*******************************************************************
+
+        CONF_STATUS(20 downto 16) <= "00000";-- Reserved
+        CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
+        CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
+        CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
+        CONF_STATUS(24 ) <= '0';-- Master :
+        --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
+        CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
+        --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
+        --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
+        CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
+        CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
+        CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
+        --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
+        --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR
+
+        process (PCI_CLOCK,PCI_RSTn)
+        begin
+        if PCI_RSTn = '0' then
+                CONF_STATUS(30) <= '0';
+                CONF_STATUS(31) <= '0';
+
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
+                        CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
+                        CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
+
+                else
+                        CONF_STATUS(30) <= SERR or CONF_STATUS(30);
+                        CONF_STATUS(31) <= PERR or CONF_STATUS(31);
+
+                end if;
+        end if;
+end process;
+
+ --*******************************************************************
+ --*********** PCI Configuration Space Header "COMMAND" **************
+ --*******************************************************************
+
+-- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
+-- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
+-- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
+-- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
+-- CONF_COMMAND( 4) <= '0';-- Master ???
+-- CONF_COMMAND( 5) <= '0';-- VGA ???
+-- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
+CONF_COMMAND( 7) <= '0';-- address/data stepping ???
+-- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
+-- CONF_COMMAND( 9) <= '0';-- fast back-to-back
+-- CONF_COMMAND(10) <= '0';-- Reserved
+-- CONF_COMMAND(11) <= '0';-- Reserved
+-- CONF_COMMAND(12) <= '0';-- Reserved
+-- CONF_COMMAND(13) <= '0';-- Reserved
+-- CONF_COMMAND(14) <= '0';-- Reserved
+-- CONF_COMMAND(15) <= '0';-- Reserved
+
+process (PCI_CLOCK,PCI_RSTn)
+begin
+        if PCI_RSTn = '0' then
+                CONF_COMMAND(15 downto 8) <= (others =>'0');
+                CONF_COMMAND( 6 downto 0) <= (others =>'0');
+
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
+                        CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
+                else
+                        CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
+                end if;
+
+                if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
+                        CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
+                else
+                        CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
+                end if;
+        end if;
+end process;
+
+CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
+
+end architecture CONFIG_04H_DESIGN;
diff --git a/dhwk/source/pci/config_08h.vhd b/dhwk/source/pci/config_08h.vhd
new file mode 100644 (file)
index 0000000..7b19df6
--- /dev/null
@@ -0,0 +1,28 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_08H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_08H is
+        port
+        (
+                REVISION_ID :in std_logic_vector ( 7 downto 0);
+                CONF_DATA_08H :out std_logic_vector (31 downto 0)
+        );
+end entity CONFIG_08H;
+
+architecture CONFIG_08H_DESIGN of CONFIG_08H is
+
+ -- PCI Configuration Space Header Addr : HEX 08 --
+
+        constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";--other comm. device
+        --constant CONF_REVISION_ID :std_logic_vector ( 7 downto 0) := X"00";
+
+begin
+
+        CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
+
+end architecture CONFIG_08H_DESIGN;
diff --git a/dhwk/source/pci/config_10h.vhd b/dhwk/source/pci/config_10h.vhd
new file mode 100644 (file)
index 0000000..ad55b17
--- /dev/null
@@ -0,0 +1,77 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_10H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_10H is
+        port
+        (
+                PCI_CLOCK :in std_logic;
+                PCI_RSTn :in std_logic;
+                AD_REG :in std_logic_vector(31 downto 0);
+                CBE_REGn :in std_logic_vector( 3 downto 0);
+                CONF_WR_10H :in std_logic;
+                CONF_DATA_10H :out std_logic_vector(31 downto 0)
+        );
+end entity CONFIG_10H;
+
+architecture CONFIG_10H_DESIGN of CONFIG_10H is
+
+        signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
+
+begin
+
+ --*******************************************************************
+ --***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******
+ --*******************************************************************
+
+        CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
+        CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
+
+        process (PCI_CLOCK,PCI_RSTn)
+        begin
+
+ -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
+        if PCI_RSTn = '0' then
+                CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
+
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
+                        CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
+                else
+                        CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
+                end if;
+
+                if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
+                        CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
+                else
+                        CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
+                end if;
+
+                if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
+                        CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
+                else
+                        CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
+                end if;
+
+                -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
+                --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
+                -- else
+                --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
+                -- end if;
+
+                if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
+                        CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
+                else
+                        CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
+                end if;
+        end if;
+end process;
+
+CONF_DATA_10H <= CONF_BAS_ADDR_REG;
+
+end architecture CONFIG_10H_DESIGN;
diff --git a/dhwk/source/pci/config_3Ch.vhd b/dhwk/source/pci/config_3Ch.vhd
new file mode 100644 (file)
index 0000000..2c79f4f
--- /dev/null
@@ -0,0 +1,59 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_3CH.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_3CH is
+        port (
+                     PCI_CLOCK :in std_logic;
+                     PCI_RSTn :in std_logic;
+                     AD_REG :in std_logic_vector (31 downto 0);
+                     CBE_REGn :in std_logic_vector ( 3 downto 0);
+                     CONF_WR_3CH :in std_logic;
+                     CONF_DATA_3CH :out std_logic_vector (31 downto 0)
+             );
+end entity CONFIG_3CH;
+
+architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
+
+ -- PCI Configuration Space Header Addr : HEX 3C --
+
+        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
+        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
+        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
+        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
+
+        constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
+begin
+
+ --*******************************************************************
+ --*********** PCI Configuration Space Header "INTERRUPT" ************
+ --*******************************************************************
+
+        CONF_MAX_LAT <= X"00";
+        CONF_MIN_GNT <= X"00";
+        -- CONF_INT_PIN <= X"00"; -- Interrupt -
+        CONF_INT_PIN <= X"01"; -- Interrupt A
+        -- CONF_INT_PIN <= X"02"; -- Interrupt B
+        -- CONF_INT_PIN <= X"03"; -- Interrupt C
+        -- CONF_INT_PIN <= X"04"; -- Interrupt D
+        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
+
+        process (PCI_CLOCK,PCI_RSTn)
+        begin
+                if PCI_RSTn = '0' then
+                        CONF_INT_LINE <= (others => '0');
+
+                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                        if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
+                                CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
+                        end if;
+                end if;
+        end process;
+
+        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
+
+end architecture CONFIG_3CH_DESIGN;
diff --git a/dhwk/source/pci/config_mux_0.vhd b/dhwk/source/pci/config_mux_0.vhd
new file mode 100644 (file)
index 0000000..f1b34f7
--- /dev/null
@@ -0,0 +1,43 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_MUX_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_MUX_0 is
+        port
+        (
+                READ_SEL :in std_logic_vector( 2 downto 0);
+                CONF_DATA_00H :in std_logic_vector(31 downto 0);
+                CONF_DATA_04H :in std_logic_vector(31 downto 0);
+                CONF_DATA_08H :in std_logic_vector(31 downto 0);
+                CONF_DATA_10H :in std_logic_vector(31 downto 0);
+                CONF_DATA_3CH :in std_logic_vector(31 downto 0);
+                --CONF_DATA_40H :in std_logic_vector(31 downto 0);
+                CONF_DATA :out std_logic_vector(31 downto 0)
+        );
+end entity CONFIG_MUX_0;
+
+architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is
+
+        signal MUX :std_logic_vector (31 downto 0);
+
+begin
+
+ --*******************************************************************
+ --******************* PCI Read Config-MUX **************************
+ --*******************************************************************
+
+        MUX <= CONF_DATA_00H when READ_SEL <= "000" else
+               CONF_DATA_04H when READ_SEL <= "001" else
+               CONF_DATA_08H when READ_SEL <= "010" else
+               CONF_DATA_10H when READ_SEL <= "011" else
+               CONF_DATA_3CH when READ_SEL <= "100" else
+               -- CONF_DATA_40H when READ_SEL <= "101" else
+               X"00000000";
+
+        CONF_DATA <= MUX;
+
+end architecture CONFIG_MUX_0_DESIGN;
diff --git a/dhwk/source/pci/config_rd_0.vhd b/dhwk/source/pci/config_rd_0.vhd
new file mode 100644 (file)
index 0000000..92b6a98
--- /dev/null
@@ -0,0 +1,134 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_RD_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_RD_0 is
+        port
+        (
+                ADDR_REG :in std_logic_vector (31 downto 0);
+                CF_RD_COM :in std_logic;
+                READ_SEL :out std_logic_vector ( 2 downto 0)
+        );
+end entity CONFIG_RD_0;
+
+architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is
+
+ --
+ --
+ --
+ --
+ --
+ -- PCI Configuration Space Header
+ --
+ -- \ Bit
+ -- \
+ --Address |31 24|23 16|15 8|7 0|
+ -----------------------------------------------------------------
+ --00 |Device ID |Vendor ID |
+ --04 |Status |Command |
+ --08 |Class Code |Revision ID|
+ --0C |BIST |Header Type|Latency T. |Cache L.S. |
+ --10-24 |Base Address Register |
+ --28 |Cardbus CIS Pointer |
+ --2C |Subsystem ID |Subsystem Vendor ID |
+ --30 |Expansion ROM Base Address |
+ --34 |Reserved |
+ --38 |Reserved |
+ --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
+ --40-FF | |
+ -----------------------------------------------------------------
+
+
+ --PCI Bus Commands
+ --C/BE[3..0] Command Type
+ --------------------------------------
+ -- 0000 Interrupt Acknowledge
+ -- 0001 Special Cycle
+ -- 0010 I/O Read
+ -- 0011 I/O Write
+ -- 0100 Reserved
+ -- 0101 Reserved
+ -- 0110 Memory Read
+ -- 0111 Memory Write
+ --
+ -- 1000 Reserved
+ -- 1001 Reserved
+ -- 1010 Configuration Read
+ -- 1011 Configuration Write
+ -- 1100 Memory Read Multiple
+ -- 1101 Dual Address Cycle
+ -- 1110 Memory Read Line
+ -- 1111 Memory Write and Invalidate
+
+
+ --PCI Byte Enable
+ --C/BE[3..0] gueltige Datenbits
+ -------------------------------
+ -- 0000 AD 31..0
+ -- 1000 AD 23..0
+ -- 1100 AD 15..0
+ -- 1110 AD 7..0
+
+        constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
+        constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
+        constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
+        constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
+        constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
+        constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
+        constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
+        constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
+        constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
+        constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
+        constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
+        constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
+        constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
+        constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
+        constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
+        constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+        signal MUX :std_logic_vector(31 downto 0);
+        signal CONFIG_ADDR :std_logic_vector( 7 downto 0);
+
+begin
+
+        CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+ --*******************************************************************
+ --*********************** PCI Read Address **************************
+ --*******************************************************************
+
+        process (CF_RD_COM, CONFIG_ADDR)
+        begin
+
+                if CF_RD_COM = '1' then
+                        if CONFIG_ADDR = X"00" then
+                                READ_SEL <= "000";
+
+                        elsif CONFIG_ADDR = X"04" then
+                                READ_SEL <= "001";
+
+                        elsif CONFIG_ADDR = X"08" then
+                                READ_SEL <= "010";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                READ_SEL <= "011";
+
+                        elsif CONFIG_ADDR = X"3C" then
+                                READ_SEL <= "100";
+
+                        elsif CONFIG_ADDR = X"40" then
+                                READ_SEL <= "101";
+
+                        else
+                                READ_SEL <= "111";
+                        end if;
+                else
+                        READ_SEL <= "111";
+                end if;
+        end process;
+
+end architecture CONFIG_RD_0_DESIGN;
index 1adc96a2ba391ec57cffa0c9b7cd510bb887189b..15db761375688bbf78f5f44f9071e2e50aa0d795 100644 (file)
@@ -1,3 +1,5 @@
+-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
+
 LIBRARY ieee;
 
 USE ieee.std_logic_1164.ALL;
 LIBRARY ieee;
 
 USE ieee.std_logic_1164.ALL;
@@ -25,91 +27,6 @@ end CONFIG_SPACE_HEADER;
 
 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
 
 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
-        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
-        --other comm. device
-        constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
-
-        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
-        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
-        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
-        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
-
-        signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
-
-        signal CONF_STATUS :std_logic_vector(31 downto 16);
-        signal CONF_COMMAND :std_logic_vector(15 downto 0);
-
-        -- PCI Configuration Space Header
-        --
-        -- \ Bit
-        -- \
-        --Address |31 24|23 16|15 8|7 0|
-        -----------------------------------------------------------------
-        --00 |Device ID |Vendor ID |
-        --04 |Status |Command |
-        --08 |Class Code |Revision ID |
-        --0C |BIST |Header Type |Latency T. |Cache L.S. |
-        --10-24 |Base Address Register |
-        --28 |Cardbus CIS Pointer |
-        --2C |Subsystem ID |Subsystem Vendor ID |
-        --30 |Expansion ROM Base Address |
-        --34 |Reserved |
-        --38 |Reserved |
-        --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
-        --40-FF | |
-        -----------------------------------------------------------------
-
-
-        --PCI Bus Commands
-        --C/BE[3..0] Command Type
-        --------------------------------------
-        -- 0000 Interrupt Acknowledge
-        -- 0001 Special Cycle
-        -- 0010 I/O Read
-        -- 0011 I/O Write
-        -- 0100 Reserved
-        -- 0101 Reserved
-        -- 0110 Memory Read
-        -- 0111 Memory Write
-        --
-        -- 1000 Reserved
-        -- 1001 Reserved
-        -- 1010 Configuration Read
-        -- 1011 Configuration Write
-        -- 1100 Memory Read Multiple
-        -- 1101 Dual Address Cycle
-        -- 1110 Memory Read Line
-        -- 1111 Memory Write and Invalidate
-
-
-        --PCI Byte Enable
-        --C/BE[3..0] gueltige Datenbits
-        -------------------------------
-        -- 0000 AD 31..0
-        -- 1000 AD 23..0
-        -- 1100 AD 15..0
-        -- 1110 AD 7..0
-
-        constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
-        constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
-        constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
-        constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
-        constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
-        constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
-        constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
-        constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
-        constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
-        constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
-        constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
-        constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
-        constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
-        constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
-        constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
-        constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
-
-        signal CONFIG_ADDR :std_logic_vector(7 downto 0);
-        signal CONFIG_WRITE :std_logic_vector(3 downto 0);
-
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
@@ -117,228 +34,122 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
+        signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
+        signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 
-begin
-        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
-        CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
-        CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
-
-        CONF_MAX_LAT <= X"00";
-        CONF_MIN_GNT <= X"00";
-        -- CONF_INT_PIN <= X"00"; -- Interrupt -
-        CONF_INT_PIN <= X"01"; -- Interrupt A
-        -- CONF_INT_PIN <= X"02"; -- Interrupt B
-        -- CONF_INT_PIN <= X"03"; -- Interrupt C
-        -- CONF_INT_PIN <= X"04"; -- Interrupt D
-        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
-        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
-
-        CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
-        CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
-        CONF_DATA_10H <= CONF_BAS_ADDR_REG;
-
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-        if PCI_RSTn = '0' then
-                CONF_INT_LINE <= (others => '0');
-
-        elsif (rising_edge(PCI_CLOCK)) then
-                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
-                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
-                end if;
-        end if;
-        end process;
-
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-
-        -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
-        if PCI_RSTn = '0' then
-                CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
-
-        elsif (rising_edge(PCI_CLOCK)) then
-
-                if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
-                        CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
-                else
-                        CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
-                end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
-                        CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
-                else
-                        CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
-                end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
-                        CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
-                else
-                        CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
-                end if;
-
-                -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
-                --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
-                -- else
-                --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
-                -- end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
-                        CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
-                else
-                        CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
-                end if;
-        end if;
-        end process;
-
-        --*******************************************************************
-        --************* PCI Configuration Space Header "STATUS" *************
-        --*******************************************************************
-
-        CONF_STATUS(20 downto 16) <= "00000";-- Reserved
-        CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
-        CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
-        CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
-        CONF_STATUS(24 ) <= '0';-- Master :
-        --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
-        CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
-        --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
-        --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
-        CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
-        CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
-        CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
-        --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
-        --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR
-
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-        if PCI_RSTn = '0' then
-                CONF_STATUS(30) <= '0';
-                CONF_STATUS(31) <= '0';
+        component CONFIG_MUX_0
+                Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_04H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_08H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_10H : In std_logic_vector (31 downto 0);
+                       CONF_DATA_3CH : In std_logic_vector (31 downto 0);
+                       READ_SEL : In std_logic_vector (2 downto 0);
+                       CONF_DATA : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_RD_0
+                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
+                       CF_RD_COM : In std_logic;
+                       READ_SEL : Out std_logic_vector (2 downto 0) );
+        end component;
+
+        component CONFIG_WR_0
+                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
+                       CF_WR_COM : In std_logic;
+                       IRDY_REGn : In std_logic;
+                       TRDYn : In std_logic;
+                       CONF_WR_04H : Out std_logic;
+                       CONF_WR_10H : Out std_logic;
+                       CONF_WR_3CH : Out std_logic );
+        end component;
+
+        component CONFIG_3CH
+                Port ( AD_REG : In std_logic_vector (31 downto 0);
+                       CBE_REGn : In std_logic_vector (3 downto 0);
+                       CONF_WR_3CH : In std_logic;
+                       PCI_CLOCK : In std_logic;
+                       PCI_RSTn : In std_logic;
+                       CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_10H
+                Port ( AD_REG : In std_logic_vector (31 downto 0);
+                       CBE_REGn : In std_logic_vector (3 downto 0);
+                       CONF_WR_10H : In std_logic;
+                       PCI_CLOCK : In std_logic;
+                       PCI_RSTn : In std_logic;
+                       CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_08H
+                Port ( REVISION_ID : In std_logic_vector (7 downto 0);
+                       CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_00H
+                Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
+                       CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
+        end component;
+
+        component CONFIG_04H
+                Port ( AD_REG : In std_logic_vector (31 downto 0);
+                       CBE_REGn : In std_logic_vector (3 downto 0);
+                       CONF_WR_04H : In std_logic;
+                       PCI_CLOCK : In std_logic;
+                       PCI_RSTn : In std_logic;
+                       PERR : In std_logic;
+                       SERR : In std_logic;
+                       CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
+        end component;
 
 
-        elsif (rising_edge(PCI_CLOCK)) then
-                if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
-                        CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
-                        CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
-
-                else
-                        CONF_STATUS(30) <= SERR or CONF_STATUS(30);
-                        CONF_STATUS(31) <= PERR or CONF_STATUS(31);
-
-                end if;
-        end if;
-        end process;
-
-        --*******************************************************************
-        --*********** PCI Configuration Space Header "COMMAND" **************
-        --*******************************************************************
-
-        -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
-        -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
-        -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
-        -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
-        -- CONF_COMMAND( 4) <= '0';-- Master ???
-        -- CONF_COMMAND( 5) <= '0';-- VGA ???
-        -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
-        CONF_COMMAND( 7) <= '0';-- address/data stepping ???
-        -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
-        -- CONF_COMMAND( 9) <= '0';-- fast back-to-back
-        -- CONF_COMMAND(10) <= '0';-- Reserved
-        -- CONF_COMMAND(11) <= '0';-- Reserved
-        -- CONF_COMMAND(12) <= '0';-- Reserved
-        -- CONF_COMMAND(13) <= '0';-- Reserved
-        -- CONF_COMMAND(14) <= '0';-- Reserved
-        -- CONF_COMMAND(15) <= '0';-- Reserved
-
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-                if PCI_RSTn = '0' then
-                        CONF_COMMAND(15 downto 8) <= (others =>'0');
-                        CONF_COMMAND( 6 downto 0) <= (others =>'0');
-
-                elsif (rising_edge(PCI_CLOCK)) then
-
-                        if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
-                                CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
-                        else
-                                CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
-                        end if;
-
-                        if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
-                                CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
-                        else
-                                CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
-                        end if;
-                end if;
-        end process;
-
-
-        --*******************************************************************
-        --******************* PCI Write Configuration Address ***************
-        --*******************************************************************
-
-        CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
-
-
-        process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
-        begin
-
-                if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
-
-                        if CONFIG_ADDR = X"04" then
-                                CONFIG_WRITE <= "0001";
-
-                        elsif CONFIG_ADDR = X"10" then
-                                CONFIG_WRITE <= "0010";
-
-                        elsif CONFIG_ADDR = X"3C" then
-                                CONFIG_WRITE <= "0100";
-
-                        -- elsif CONFIG_ADDR = X"40" then
-                        --         CONFIG_WRITE <= "1000";
-                        else
-                                CONFIG_WRITE <= "0000";
-                        end if;
-                else
-                        CONFIG_WRITE <= "0000";
-                end if;
-        end process;
-
-        CONF_WR_04H <= CONFIG_WRITE(0);
-        CONF_WR_10H <= CONFIG_WRITE(1);
-        CONF_WR_3CH <= CONFIG_WRITE(2);
-        --CONF_WR_40H <= CONFIG_WRITE(3);
-
-        process (CF_RD_COM, CONFIG_ADDR)
-        begin
-
-                if CF_RD_COM = '1' then
-                        if CONFIG_ADDR = X"00" then
-                                CONF_READ_SEL <= "000";
-
-                        elsif CONFIG_ADDR = X"04" then
-                                CONF_READ_SEL <= "001";
-
-                        elsif CONFIG_ADDR = X"08" then
-                                CONF_READ_SEL <= "010";
-
-                        elsif CONFIG_ADDR = X"10" then
-                                CONF_READ_SEL <= "011";
-
-                        elsif CONFIG_ADDR = X"3C" then
-                                CONF_READ_SEL <= "100";
-
-                        elsif CONFIG_ADDR = X"40" then
-                                CONF_READ_SEL <= "101";
+begin
 
 
-                        else
-                                CONF_READ_SEL <= "111";
-                        end if;
-                else
-                        CONF_READ_SEL <= "111";
-                end if;
-        end process;
+        CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
+        CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
+
+        I10 : CONFIG_MUX_0
+        Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
+        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
+        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
+        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
+        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
+        READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
+        CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
+        I9 : CONFIG_RD_0
+        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                   CF_RD_COM=>CF_RD_COM,
+                   READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
+        I8 : CONFIG_WR_0
+        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                   CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
+                   TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
+                   CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
+        I6 : CONFIG_3CH
+        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+        CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
+        PCI_RSTn=>PCI_RSTn,
+        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
+        I5 : CONFIG_10H
+        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+        CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
+        PCI_RSTn=>PCI_RSTn,
+        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
+        I4 : CONFIG_08H
+        Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
+        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
+        I3 : CONFIG_00H
+        Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+        CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
+        I2 : CONFIG_04H
+        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+        CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
+        PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
+        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
 
 end SCHEMATIC;
 
 end SCHEMATIC;
diff --git a/dhwk/source/pci/config_wr_0.vhd b/dhwk/source/pci/config_wr_0.vhd
new file mode 100644 (file)
index 0000000..9e1e2dc
--- /dev/null
@@ -0,0 +1,140 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_WR_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_WR_0 is
+        port
+        (
+                ADDR_REG :in std_logic_vector(31 downto 0);
+                CF_WR_COM :in std_logic;
+                IRDY_REGn :in std_logic;
+                TRDYn :in std_logic;
+                CONF_WR_04H :out std_logic;
+                CONF_WR_10H :out std_logic;
+                CONF_WR_3CH :out std_logic
+                --CONF_WR_40H :out std_logic
+        );
+end entity CONFIG_WR_0;
+
+architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is
+
+ --
+ --
+ --
+ --
+ --
+ -- PCI Configuration Space Header
+ --
+ -- \ Bit
+ -- \
+ --Address |31 24|23 16|15 8|7 0|
+ -----------------------------------------------------------------
+ --00 |Device ID |Vendor ID |
+ --04 |Status |Command |
+ --08 |Class Code |Revision ID |
+ --0C |BIST |Header Type |Latency T. |Cache L.S. |
+ --10-24 |Base Address Register |
+ --28 |Cardbus CIS Pointer |
+ --2C |Subsystem ID |Subsystem Vendor ID |
+ --30 |Expansion ROM Base Address |
+ --34 |Reserved |
+ --38 |Reserved |
+ --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
+ --40-FF | |
+ -----------------------------------------------------------------
+
+
+ --PCI Bus Commands
+ --C/BE[3..0] Command Type
+ --------------------------------------
+ -- 0000 Interrupt Acknowledge
+ -- 0001 Special Cycle
+ -- 0010 I/O Read
+ -- 0011 I/O Write
+ -- 0100 Reserved
+ -- 0101 Reserved
+ -- 0110 Memory Read
+ -- 0111 Memory Write
+ --
+ -- 1000 Reserved
+ -- 1001 Reserved
+ -- 1010 Configuration Read
+ -- 1011 Configuration Write
+ -- 1100 Memory Read Multiple
+ -- 1101 Dual Address Cycle
+ -- 1110 Memory Read Line
+ -- 1111 Memory Write and Invalidate
+
+
+ --PCI Byte Enable
+ --C/BE[3..0] gueltige Datenbits
+ -------------------------------
+ -- 0000 AD 31..0
+ -- 1000 AD 23..0
+ -- 1100 AD 15..0
+ -- 1110 AD 7..0
+
+        constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
+        constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
+        constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
+        constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
+        constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
+        constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
+        constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
+        constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
+        constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
+        constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
+        constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
+        constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
+        constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
+        constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
+        constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
+        constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+        signal CONFIG_ADDR :std_logic_vector(7 downto 0);
+        signal CONFIG_WRITE :std_logic_vector(3 downto 0);
+
+
+begin
+
+ --*******************************************************************
+ --******************* PCI Write Configuration Address ***************
+ --*******************************************************************
+
+        CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+
+        process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
+        begin
+
+                if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
+
+                        if CONFIG_ADDR = X"04" then
+                                CONFIG_WRITE <= "0001";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                CONFIG_WRITE <= "0010";
+
+                        elsif CONFIG_ADDR = X"3C" then
+                                CONFIG_WRITE <= "0100";
+
+                        -- elsif CONFIG_ADDR = X"40" then
+                        --         CONFIG_WRITE <= "1000";
+                        else
+                                CONFIG_WRITE <= "0000";
+                        end if;
+                else
+                        CONFIG_WRITE <= "0000";
+                end if;
+        end process;
+
+        CONF_WR_04H <= CONFIG_WRITE(0);
+        CONF_WR_10H <= CONFIG_WRITE(1);
+        CONF_WR_3CH <= CONFIG_WRITE(2);
+        --CONF_WR_40H <= CONFIG_WRITE(3);
+
+end architecture CONFIG_WR_0_DESIGN;
index 421132f3f6cb3647523a066f85558ef65eac93bc..eb444eaf02654dfb666421c4117aaba6502ff18a 100644 (file)
@@ -66,7 +66,7 @@ begin
 
         process (PCI_CLOCK)
         begin
 
         process (PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if SIG_LOAD = '1' then
                                 REG <= S_FIFO_Q_OUT;
 
                         if SIG_LOAD = '1' then
                                 REG <= S_FIFO_Q_OUT;
 
@@ -82,7 +82,7 @@ begin
 
 process (PCI_CLOCK)
 begin
 
 process (PCI_CLOCK)
 begin
-        if (rising_edge(PCI_CLOCK)) then
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
 
                 if RESET = '1' then
                         STATES <= S0;
 
                 if RESET = '1' then
                         STATES <= S0;
index 7ebd4c0ca2bf72c6aeefe8ee11c87c2da6898403..4600784de3573369f390fa805c8b82ccd4f803f9 100644 (file)
@@ -88,7 +88,7 @@ begin
         begin
                 if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE;
 
         begin
                 if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE;
 
-        elsif (rising_edge(PCI_CLOCK)) then
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
 
                 case CONTROL_STATE is
                 when ST_IDLE =>
 
                 case CONTROL_STATE is
                 when ST_IDLE =>
index 43f3a43bc7e5f7e12da7010add5ce226a516c2ba..03f914ac38a39f6d6ad6cdd6ab50b59d1f2d2e94 100644 (file)
@@ -1,4 +1,4 @@
--- $Id: fifo_io_control.vhd,v 1.2 2007-03-11 09:14:58 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
 
 library IEEE;
 use IEEE.std_logic_1164.all;
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -35,7 +35,7 @@ begin
 
         process (PCI_CLOCK)
         begin
 
         process (PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if (RESET = '1') then
                                 S_FIFO_WRITEn <= '1';
                                 SIG_S_ERROR <= '0';
                         if (RESET = '1') then
                                 S_FIFO_WRITEn <= '1';
                                 SIG_S_ERROR <= '0';
index 5e6ba0211dce8b0c2593ce0b40e0497947cd7a4c..2b3c654646d0d5f693e64ce345f841d35829178f 100644 (file)
@@ -46,7 +46,7 @@ begin
 
         process (PCI_CLOCK)
         begin
 
         process (PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         FF1_S_EFn <= not S_EFn;
                         FF1_S_HFn <= not S_HFn;
                         FF1_S_FFn <= not S_FFn;
                         FF1_S_EFn <= not S_EFn;
                         FF1_S_HFn <= not S_HFn;
                         FF1_S_FFn <= not S_FFn;
@@ -59,7 +59,7 @@ begin
 
         process (PCI_CLOCK)
         begin
 
         process (PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if HOLD = '0' then
                                 FF2_S_EFn <= FF1_S_EFn;
                                 FF2_S_HFn <= FF1_S_HFn;
                         if HOLD = '0' then
                                 FF2_S_EFn <= FF1_S_EFn;
                                 FF2_S_HFn <= FF1_S_HFn;
index 1266a9ed9fd076998a8e9cbbb08218a0a0005796..1c1e6e8276aab897a1772288854d1c5a10f4597a 100644 (file)
@@ -75,7 +75,7 @@ begin
                         FF_A <= "00000000";
                         FF_B <= "00000000";
 
                         FF_A <= "00000000";
                         FF_B <= "00000000";
 
-                elsif (rising_edge(PCI_CLOCK)) then
+                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if (RESET = '1') then
                                 SET <= "00000000";
                                 FF_A <= "00000000";
                         if (RESET = '1') then
                                 SET <= "00000000";
                                 FF_A <= "00000000";
@@ -105,7 +105,7 @@ begin
                 if (PCI_RSTn = '0') then
                         REG <= "00000000";
 
                 if (PCI_RSTn = '0') then
                         REG <= "00000000";
 
-                elsif(rising_edge(PCI_CLOCK)) then
+                elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if(RESET = '1') then
                                 REG <= "00000000";
 
                         if(RESET = '1') then
                                 REG <= "00000000";
 
@@ -132,7 +132,7 @@ begin
 
         process (PCI_CLOCK)
         begin
 
         process (PCI_CLOCK)
         begin
-                if(rising_edge(PCI_CLOCK)) then
+                if(PCI_CLOCK'event and PCI_CLOCK = '1') then
                         SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
                 end if;
         end process;
                         SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
                 end if;
         end process;
index 3003c367563076b62053cf9deef580566625a2dd..ecbd9d67dbdbae908d0cc8cad8947b66e2361736 100644 (file)
@@ -49,7 +49,7 @@ begin
                         REG_IDSEL <= '0';
                         REG_PAR <= '0';
 
                         REG_IDSEL <= '0';
                         REG_PAR <= '0';
 
-                elsif (rising_edge(PCI_CLOCK)) then
+                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         REG_AD <= IO_DATA;
                         REG_CBEn <= PCI_CBEn;
                         REG_FRAMEn <= PCI_FRAMEn;
                         REG_AD <= IO_DATA;
                         REG_CBEn <= PCI_CBEn;
                         REG_FRAMEn <= PCI_FRAMEn;
index e169ba3df172b7634c749b09216b477f1bf25ead..c8ecfa7859a450832b4e4dda1e251e632e300713 100644 (file)
@@ -44,7 +44,7 @@ begin
                 PERR_FF <= '0';
                 SERR_FF <= '0';
 
                 PERR_FF <= '0';
                 SERR_FF <= '0';
 
-        elsif (rising_edge(PCI_CLOCK)) then
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
                 SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
                 PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
         end if;
                 SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
                 PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
         end if;
index d15f9da8412f4e1dfe95dee7c48484d855c3a1cb..722cce6dde2ce77956fed8992ed83024289beeeb 100644 (file)
@@ -109,6 +109,12 @@ architecture SCHEMATIC of PCI_INTERFACE is
                        SERR : Out std_logic );
         end component;
 
                        SERR : Out std_logic );
         end component;
 
+        component VERGLEICH
+                Port ( IN_A : In std_logic_vector (31 downto 0);
+                       IN_B : In std_logic_vector (31 downto 0);
+                       GLEICH_OUT : Out std_logic );
+        end component;
+
         component IO_MUX_REG
                 Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
                        LOAD_ADDR_REG : In std_logic;
         component IO_MUX_REG
                 Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
                        LOAD_ADDR_REG : In std_logic;
@@ -183,6 +189,10 @@ begin
                    SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
                    PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
                    PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
                    SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
                    PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
                    PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
+        I4 : VERGLEICH
+        Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
+        IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+        GLEICH_OUT=>MY_ADDR );
         I2 : IO_MUX_REG
         Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
                    LOAD_ADDR_REG=>LAR,
         I2 : IO_MUX_REG
         Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
                    LOAD_ADDR_REG=>LAR,
@@ -212,17 +222,4 @@ begin
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
 
         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
 
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-        if PCI_RSTn = '0' then
-                MY_ADDR <= '0';
-
-        elsif (rising_edge(PCI_CLOCK)) then
-                if (CONF_DATA_10H(31 downto 2) = ADDR_REG_DUMMY(31 downto 2)) then
-                        MY_ADDR <= '1';
-                else
-                        MY_ADDR <= '0';
-                end if;
-        end if;
-        end process;
 end SCHEMATIC;
 end SCHEMATIC;
diff --git a/dhwk/source/pci/verg_2.vhd b/dhwk/source/pci/verg_2.vhd
new file mode 100644 (file)
index 0000000..bbea0ea
--- /dev/null
@@ -0,0 +1,33 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_2.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_2 is
+        port
+        (
+                IN_A :in std_logic_vector(1 downto 0);
+                IN_B :in std_logic_vector(1 downto 0);
+                GLEICH :out std_logic
+        );
+end entity VERG_2;
+
+architecture VERG_2_DESIGN of VERG_2 is
+
+begin
+
+        process (IN_A,IN_B)
+        begin
+
+        if IN_A = IN_B then
+                GLEICH <= '1';
+        else
+                GLEICH <= '0';
+        end if;
+
+end process;
+
+end architecture VERG_2_DESIGN;
diff --git a/dhwk/source/pci/verg_4.vhd b/dhwk/source/pci/verg_4.vhd
new file mode 100644 (file)
index 0000000..02edc30
--- /dev/null
@@ -0,0 +1,33 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_4 is
+        port
+        (
+                IN_A :in std_logic_vector(3 downto 0);
+                IN_B :in std_logic_vector(3 downto 0);
+                GLEICH :out std_logic
+        );
+end entity VERG_4;
+
+architecture VERG_4_DESIGN of VERG_4 is
+
+begin
+
+        process (IN_A,IN_B)
+        begin
+
+                if IN_A = IN_B then
+                        GLEICH <= '1';
+                else
+                        GLEICH <= '0';
+                end if;
+        end process;
+
+end architecture VERG_4_DESIGN;
+
diff --git a/dhwk/source/pci/verg_8.vhd b/dhwk/source/pci/verg_8.vhd
new file mode 100644 (file)
index 0000000..ea7a499
--- /dev/null
@@ -0,0 +1,27 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_8.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_8 is
+        port
+        (
+                GLEICH :in std_logic_vector(7 downto 0);
+                GLEICH_OUT :out std_logic
+        );
+
+end entity VERG_8;
+
+architecture VERG_8_DESIGN of VERG_8 is
+
+begin
+
+ -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
+
+ -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0';
+    GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0';
+
+end architecture VERG_8_DESIGN;
diff --git a/dhwk/source/pci/vergleich.vhd b/dhwk/source/pci/vergleich.vhd
new file mode 100644 (file)
index 0000000..55aacd3
--- /dev/null
@@ -0,0 +1,69 @@
+-- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity VERGLEICH is
+        Port ( IN_A : In std_logic_vector (31 downto 0);
+               IN_B : In std_logic_vector (31 downto 0);
+               GLEICH_OUT : Out std_logic );
+end VERGLEICH;
+
+architecture SCHEMATIC of VERGLEICH is
+
+        SIGNAL gnd : std_logic := '0';
+        SIGNAL vcc : std_logic := '1';
+
+        signal GLEICH : std_logic_vector (7 downto 0);
+
+        component VERG_2
+                Port ( IN_A : In std_logic_vector (1 downto 0);
+                       IN_B : In std_logic_vector (1 downto 0);
+                       GLEICH : Out std_logic );
+        end component;
+
+        component VERG_8
+                Port ( GLEICH : In std_logic_vector (7 downto 0);
+                       GLEICH_OUT : Out std_logic );
+        end component;
+
+        component VERG_4
+                Port ( IN_A : In std_logic_vector (3 downto 0);
+                       IN_B : In std_logic_vector (3 downto 0);
+                       GLEICH : Out std_logic );
+        end component;
+
+begin
+
+        I11 : VERG_2
+        Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),
+        IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );
+        I9 : VERG_8
+        Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),
+                   GLEICH_OUT=>GLEICH_OUT );
+        I8 : VERG_4
+        Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),
+        IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );
+        I7 : VERG_4
+        Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),
+        IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );
+        I6 : VERG_4
+        Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),
+        IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );
+        I5 : VERG_4
+        Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),
+        IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );
+        I4 : VERG_4
+        Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),
+        IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );
+        I3 : VERG_4
+        Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),
+        IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );
+        I2 : VERG_4
+        Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),
+        IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );
+
+end SCHEMATIC;
index f0b7896b6d3c13bf544386a2905e4f95a3d9be4c..d68124d3920f59c513161bdb8fa376acda83594e 100644 (file)
@@ -1,4 +1,4 @@
--- $Id: ser_par_con.vhd,v 1.2 2007-03-11 09:14:58 sithglan Exp $
+-- $Id: ser_par_con.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
 
 library ieee;
 use ieee.std_logic_1164.all;
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -46,7 +46,7 @@ begin
 
         process(PCI_CLOCK)
         begin
 
         process(PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
@@ -129,7 +129,7 @@ begin
 
         process(PCI_CLOCK)
         begin
 
         process(PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
                 end if;
         end process;
                         SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
                 end if;
         end process;
@@ -137,7 +137,7 @@ begin
 
         process(PCI_CLOCK)
         begin
 
         process(PCI_CLOCK)
         begin
-                if (rising_edge(PCI_CLOCK)) then
+                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
                         if (RESET = '1') then
                                 STARTBIT <= "0000";
                         else
                         if (RESET = '1') then
                                 STARTBIT <= "0000";
                         else
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