consolidate more

diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj
index 30cbe67a0e57e9fdabbe403880cfd7d3227141a5..8d0f4f7bb3d4accdeb59294d4a784d3dd0e9cc06 100644 (file)
--- a/dhwk/dhwk.prj
+++ b/dhwk/dhwk.prj
@@ -4,8 +4,6 @@ vhdl work "source/pci/address_register.vhd"
 vhdl work "source/pci/comm_dec.vhd"
 vhdl work "source/pci/comm_fsm.vhd"
 vhdl work "source/pci/config_04h.vhd"
 vhdl work "source/pci/comm_dec.vhd"
 vhdl work "source/pci/comm_fsm.vhd"
 vhdl work "source/pci/config_04h.vhd"

-vhdl work "source/pci/config_10h.vhd"
-vhdl work "source/pci/config_mux_0.vhd"

 vhdl work "source/pci/config_rd_0.vhd"
 vhdl work "source/pci/config_space_header.vhd"
 vhdl work "source/pci/config_wr_0.vhd"
 vhdl work "source/pci/config_rd_0.vhd"
 vhdl work "source/pci/config_space_header.vhd"
 vhdl work "source/pci/config_wr_0.vhd"

diff --git a/dhwk/source/pci/config_10h.vhd b/dhwk/source/pci/config_10h.vhd
deleted file mode 100644 (file)
index 4660c6f..0000000
--- a/dhwk/source/pci/config_10h.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--- J.STELZNER
--- INFORMATIK-3 LABOR
--- 23.08.2006
--- File: CONFIG_10H.VHD
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity CONFIG_10H is
-        port
-        (
-                PCI_CLOCK :in std_logic;
-                PCI_RSTn :in std_logic;
-                AD_REG :in std_logic_vector(31 downto 0);
-                CBE_REGn :in std_logic_vector( 3 downto 0);
-                CONF_WR_10H :in std_logic;
-                CONF_DATA_10H :out std_logic_vector(31 downto 0)
-        );
-end entity CONFIG_10H;
-
-architecture CONFIG_10H_DESIGN of CONFIG_10H is
-
-        signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
-
-begin
-
- --*******************************************************************
- --***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******
- --*******************************************************************
-
-        CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
-        CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
-
-        process (PCI_CLOCK,PCI_RSTn)
-        begin
-
- -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
-        if PCI_RSTn = '0' then
-                CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
-
-        elsif (rising_edge(PCI_CLOCK)) then
-
-                if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
-                        CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
-                else
-                        CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
-                end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
-                        CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
-                else
-                        CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
-                end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
-                        CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
-                else
-                        CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
-                end if;
-
-                -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
-                --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
-                -- else
-                --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
-                -- end if;
-
-                if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
-                        CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
-                else
-                        CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
-                end if;
-        end if;
-end process;
-
-CONF_DATA_10H <= CONF_BAS_ADDR_REG;
-
-end architecture CONFIG_10H_DESIGN;

diff --git a/dhwk/source/pci/config_space_header.vhd b/dhwk/source/pci/config_space_header.vhd
index 9114785f5c75f6df64246c4686a27ea38e987717..722b931cac03ea21acff8726c08c235b105b4267 100644 (file)
--- a/dhwk/source/pci/config_space_header.vhd
+++ b/dhwk/source/pci/config_space_header.vhd
@@ -36,6 +36,8 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONF_INT_PIN :std_logic_vector (15 downto 8);
         signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
 
         signal CONF_INT_PIN :std_logic_vector (15 downto 8);
         signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
 

+        signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
+

         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 


@@ -43,22 +45,11 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);

-        signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);

         signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 
         signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 

-        component CONFIG_MUX_0
-                Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
-                       CONF_DATA_04H : In std_logic_vector (31 downto 0);
-                       CONF_DATA_08H : In std_logic_vector (31 downto 0);
-                       CONF_DATA_10H : In std_logic_vector (31 downto 0);
-                       CONF_DATA_3CH : In std_logic_vector (31 downto 0);
-                       READ_SEL : In std_logic_vector (2 downto 0);
-                       CONF_DATA : Out std_logic_vector (31 downto 0) );
-        end component;
-

         component CONFIG_RD_0
                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
                        CF_RD_COM : In std_logic;
         component CONFIG_RD_0
                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
                        CF_RD_COM : In std_logic;


@@ -75,15 +66,6 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
                        CONF_WR_3CH : Out std_logic );
         end component;
 
                        CONF_WR_3CH : Out std_logic );
         end component;
 

-        component CONFIG_10H
-                Port ( AD_REG : In std_logic_vector (31 downto 0);
-                       CBE_REGn : In std_logic_vector (3 downto 0);
-                       CONF_WR_10H : In std_logic;
-                       PCI_CLOCK : In std_logic;
-                       PCI_RSTn : In std_logic;
-                       CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
-        end component;
-

         component CONFIG_04H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);
         component CONFIG_04H
                 Port ( AD_REG : In std_logic_vector (31 downto 0);
                        CBE_REGn : In std_logic_vector (3 downto 0);


@@ -100,7 +82,6 @@ begin
         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
 
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
 
         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;

-        CONF_DATA_10H <= CONF_DATA_10H_DUMMY;

 
         CONF_MAX_LAT <= X"00";
         CONF_MIN_GNT <= X"00";
 
         CONF_MAX_LAT <= X"00";
         CONF_MIN_GNT <= X"00";


@@ -112,14 +93,10 @@ begin
         -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
         CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
 
         -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
         CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
 

-        I10 : CONFIG_MUX_0
-        Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
-        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
-        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
-        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
-        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
-        READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
-        CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
+        CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
+        CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
+        CONF_DATA_10H <= CONF_BAS_ADDR_REG;
+

         I9 : CONFIG_RD_0
         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                    CF_RD_COM=>CF_RD_COM,
         I9 : CONFIG_RD_0
         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                    CF_RD_COM=>CF_RD_COM,


@@ -129,12 +106,6 @@ begin
                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );

-        I5 : CONFIG_10H
-        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
-        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
-        CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
-        PCI_RSTn=>PCI_RSTn,
-        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );

         I2 : CONFIG_04H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
         I2 : CONFIG_04H
         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),


@@ -144,13 +115,54 @@ begin
 
         process (PCI_CLOCK,PCI_RSTn)
         begin
 
         process (PCI_CLOCK,PCI_RSTn)
         begin

-                if PCI_RSTn = '0' then
-                        CONF_INT_LINE <= (others => '0');
+        if PCI_RSTn = '0' then
+                CONF_INT_LINE <= (others => '0');
+
+        elsif (rising_edge(PCI_CLOCK)) then
+                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
+                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
+                end if;
+        end if;
+        end process;
+
+        process (PCI_CLOCK,PCI_RSTn)
+        begin
+
+        -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
+        if PCI_RSTn = '0' then
+                CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
+
+        elsif (rising_edge(PCI_CLOCK)) then
+
+                if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
+                        CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
+                else
+                        CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
+                end if;
+
+                if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
+                        CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
+                else
+                        CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
+                end if;
+
+                if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
+                        CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
+                else
+                        CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
+                end if;
+
+                -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
+                --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
+                -- else
+                --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
+                -- end if;

 
 

-                elsif (rising_edge(PCI_CLOCK)) then
-                        if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
-                                CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
-                        end if;
+                if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
+                        CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
+                else
+                        CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);

                 end if;
                 end if;

+        end if;

         end process;
 end SCHEMATIC;
         end process;
 end SCHEMATIC;