NET "MD_PAD_IO" LOC = "Y1" | IOSTANDARD = LVCMOS33;
NET "MDC_PAD_O" LOC = "U2" | IOSTANDARD = LVCMOS33;
+NET "PHY_CLOCK" LOC = "L5" | IOSTANDARD = LVCMOS33;
+
NET "LED_2" LOC = "AB5" | IOSTANDARD = LVTTL | DRIVE = 24 ;
MD_PAD_IO : INOUT std_logic;
MDC_PAD_O : OUT std_logic;
+ PHY_CLOCK : OUT std_logic;
+
LED_2 : OUT std_logic
);
end ethernet;
wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2);
wb_clk_i <= PCI_CLOCK;
+PHY_CLOCK <= PCI_CLOCK;
data(31 downto 0) <= wbm_adr_o;
data(40 downto 33) <= wbm_adr_o (7 downto 0);