use IOBUFs for PCI communication

diff --git a/ethernet/source/pci/pci_user_constants.v b/ethernet/source/pci/pci_user_constants.v
index 70c9b0e9a36dc170b29b5bb73b0f7ce9f1fb2e19..af419f169ca3c9a66acc33e7c3bcdf423b56f446 100644 (file)
--- a/ethernet/source/pci/pci_user_constants.v
+++ b/ethernet/source/pci/pci_user_constants.v
@@ -143,8 +143,8 @@
 
 // these two defines allow user to select active high or low output enables on PCI bus signals, depending on
 // output buffers instantiated. Xilinx FPGAs use active low output enables.
 
 // these two defines allow user to select active high or low output enables on PCI bus signals, depending on
 // output buffers instantiated. Xilinx FPGAs use active low output enables.

-// `define ACTIVE_LOW_OE
-`define ACTIVE_HIGH_OE
+`define ACTIVE_LOW_OE
+//`define ACTIVE_HIGH_OE

 
 // HOST/GUEST implementation selection - see design document and specification for description of each implementation
 // only one can be defined at same time
 
 // HOST/GUEST implementation selection - see design document and specification for description of each implementation
 // only one can be defined at same time

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index f7c5bd9ad33f02ebb0793dfec585450362f210d8..899bc12318e94a191171845069b159aecd7ab085 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -1,5 +1,7 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;

+Library UNISIM;
+use UNISIM.vcomponents.all;

 
 entity ethernet is
 PORT(
 
 entity ethernet is
 PORT(


@@ -179,31 +181,43 @@ port ( CLKIN_IN        : in    std_logic;
        LOCKED_OUT      : out   std_logic);
 end component;
 
        LOCKED_OUT      : out   std_logic);
 end component;
 

+signal pci_rst_i : std_logic;

 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;

+signal pci_inta_i : std_logic;

 signal pci_inta_o : std_logic;
 signal pci_inta_oe_o : std_logic;
 signal pci_req_o : std_logic;
 signal pci_req_oe_o : std_logic;
 signal pci_inta_o : std_logic;
 signal pci_inta_oe_o : std_logic;
 signal pci_req_o : std_logic;
 signal pci_req_oe_o : std_logic;

+signal pci_frame_i : std_logic;

 signal pci_frame_o : std_logic;
 signal pci_frame_oe_o : std_logic;
 signal pci_frame_o : std_logic;
 signal pci_frame_oe_o : std_logic;

+signal pci_irdy_i : std_logic;

 signal pci_irdy_o : std_logic;
 signal pci_irdy_oe_o : std_logic;
 signal pci_irdy_o : std_logic;
 signal pci_irdy_oe_o : std_logic;

+signal pci_devsel_i : std_logic;

 signal pci_devsel_o : std_logic;
 signal pci_devsel_oe_o : std_logic;
 signal pci_devsel_o : std_logic;
 signal pci_devsel_oe_o : std_logic;

+signal pci_trdy_i : std_logic;

 signal pci_trdy_o : std_logic;
 signal pci_trdy_oe_o : std_logic;
 signal pci_trdy_o : std_logic;
 signal pci_trdy_oe_o : std_logic;

+signal pci_stop_i : std_logic;

 signal pci_stop_o : std_logic;
 signal pci_stop_oe_o : std_logic;
 signal pci_stop_o : std_logic;
 signal pci_stop_oe_o : std_logic;

+signal pci_par_i : std_logic;

 signal pci_par_o : std_logic;
 signal pci_par_oe_o : std_logic;
 signal pci_par_o : std_logic;
 signal pci_par_oe_o : std_logic;

+signal pci_perr_i : std_logic;

 signal pci_perr_o : std_logic;
 signal pci_perr_oe_o : std_logic;
 signal pci_perr_o : std_logic;
 signal pci_perr_oe_o : std_logic;

+signal pci_serr_i : std_logic;

 signal pci_serr_o : std_logic;
 signal pci_serr_oe_o : std_logic;
 signal pci_ad_oe_o : std_logic_vector(31 downto 0);
 signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
 signal pci_serr_o : std_logic;
 signal pci_serr_oe_o : std_logic;
 signal pci_ad_oe_o : std_logic_vector(31 downto 0);
 signal pci_cbe_oe_o : std_logic_vector(3 downto 0);

+signal pci_ad_i : std_logic_vector (31 downto 0);

 signal pci_ad_o : std_logic_vector (31 downto 0);
 signal pci_ad_o : std_logic_vector (31 downto 0);

+signal pci_cbe_i : std_logic_vector (3 downto 0);

 signal pci_cbe_o : std_logic_vector (3 downto 0);
 
 signal wb_clk_i : std_logic;
 signal pci_cbe_o : std_logic_vector (3 downto 0);
 
 signal wb_clk_i : std_logic;


@@ -226,6 +240,7 @@ signal m_wb_cyc_o : std_logic;
 signal m_wb_stb_o : std_logic;
 signal m_wb_ack_i : std_logic;
 signal m_wb_err_i : std_logic;
 signal m_wb_stb_o : std_logic;
 signal m_wb_ack_i : std_logic;
 signal m_wb_err_i : std_logic;

+signal md_pad_i : std_logic;

 signal md_pad_o : std_logic;
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal md_pad_o : std_logic;
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;


@@ -242,25 +257,108 @@ signal trig0 : std_logic_vector(31 downto 0);
 
 BEGIN
 
 
 BEGIN
 

-PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
-PCI_INTAn   <= pci_inta_o   when (pci_inta_oe_o = '1')    else 'Z';
-PCI_REQn    <= pci_req_o    when (pci_req_oe_o = '1')     else 'Z';
-PCI_FRAMEn  <= pci_frame_o  when (pci_frame_oe_o = '1')     else 'Z';
-PCI_IRDYn   <= pci_irdy_o   when (pci_irdy_oe_o = '1')    else 'Z';
-PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1')  else 'Z';
-PCI_TRDYn   <= pci_trdy_o   when (pci_trdy_oe_o = '1')    else 'Z';
-PCI_STOPn   <= pci_stop_o   when (pci_stop_oe_o = '1')    else 'Z';
-PCI_PAR     <= pci_par_o    when (pci_par_oe_o = '1')     else 'Z';
-PCI_PERRn   <= pci_perr_o   when (pci_perr_oe_o = '1')    else 'Z';
-PCI_SERRn   <= pci_serr_o   when (pci_serr_oe_o = '1')    else 'Z';
-MD_PAD_IO   <= md_pad_o     when (md_padoe_o = '1')       else 'Z';
+IOBUF_PCI_RSTn: IOBUF
+port map (
+       IO => PCI_RSTn,
+       T => pci_rst_oe_o,
+       I => pci_rst_o,
+       O => pci_rst_i
+);
+IOBUF_PCI_INTAn: IOBUF
+port map (
+       IO => PCI_INTAn,
+       T => pci_inta_oe_o,
+       I => pci_inta_o,
+       O => pci_inta_i
+);
+OBUFT_PCI_REQn: OBUFT
+port map (
+       O => PCI_REQn,
+       T => pci_req_oe_o,
+       I => pci_req_o
+);
+IOBUF_PCI_FRAMEn: IOBUF
+port map (
+       IO => PCI_FRAMEn,
+       T => pci_frame_oe_o,
+       I => pci_frame_o,
+       O => pci_frame_i
+);
+IOBUF_PCI_IRDYn: IOBUF
+port map (
+       IO => PCI_IRDYn,
+       T => pci_irdy_oe_o,
+       I => pci_irdy_o,
+       O => pci_irdy_i
+);
+IOBUF_PCI_DEVSELn: IOBUF
+port map (
+       IO => PCI_DEVSELn,
+       T => pci_devsel_oe_o,
+       I => pci_devsel_o,
+       O => pci_devsel_i
+);
+IOBUF_PCI_TRDYn: IOBUF
+port map (
+       IO => PCI_TRDYn,
+       T => pci_trdy_oe_o,
+       I => pci_trdy_o,
+       O => pci_trdy_i
+);
+IOBUF_PCI_STOPn: IOBUF
+port map (
+       IO => PCI_STOPn,
+       T => pci_stop_oe_o,
+       I => pci_stop_o,
+       O => pci_stop_i
+);
+IOBUF_PCI_PAR: IOBUF
+port map (
+       IO => PCI_PAR,
+       T => pci_par_oe_o,
+       I => pci_par_o,
+       O => pci_par_i
+);
+IOBUF_PCI_PERRn: IOBUF
+port map (
+       IO => PCI_PERRn,
+       T => pci_perr_oe_o,
+       I => pci_perr_o,
+       O => pci_perr_i
+);
+IOBUF_PCI_SERRn: IOBUF
+port map (
+       IO => PCI_SERRn,
+       T => pci_serr_oe_o,
+       I => pci_serr_o,
+       O => pci_serr_i
+);
+IOBUF_MD_PAD_IO: IOBUF
+port map (
+       IO => MD_PAD_IO,
+       T => md_padoe_o,
+       I => md_pad_o,
+       O => md_pad_i
+);

 
 BLA1: FOR i in 31 downto 0 generate
 
 BLA1: FOR i in 31 downto 0 generate

-PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
+IOBUF_PCI_AD: IOBUF
+port map (
+       IO => PCI_AD(i),
+       T => pci_ad_oe_o(i),
+       I => pci_ad_o(i),
+       O => pci_ad_i(i)
+);

 end generate;
 
 BLA2: FOR i in 3 downto 0 generate
 end generate;
 
 BLA2: FOR i in 3 downto 0 generate

-PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
+IOBUF_PCI_CBEn: IOBUF
+port map (
+       IO => PCI_CBEn(i),
+       T => pci_cbe_oe_o(i),
+       I => pci_cbe_o(i),
+       O => pci_cbe_i(i)
+);

 end generate;
 
 wb_adr_i(11 downto 8) <= (others => '0');
 end generate;
 
 wb_adr_i(11 downto 8) <= (others => '0');


@@ -270,17 +368,18 @@ wb_clk_i <= PCI_CLOCK;
 
 data(31 downto 0)  <= wbm_adr_o;
 data(39 downto 32) <= wbm_adr_o (7 downto 0);
 
 data(31 downto 0)  <= wbm_adr_o;
 data(39 downto 32) <= wbm_adr_o (7 downto 0);

-data(40) <= MD_PAD_IO;
+data(40) <= md_pad_i;

 data(41) <= md_pad_o;
 data(42) <= md_padoe_o;
 data(43) <= mdc_pad_o_watch;
 data(44) <= pci_inta_o;
 data(41) <= md_pad_o;
 data(42) <= md_padoe_o;
 data(43) <= mdc_pad_o_watch;
 data(44) <= pci_inta_o;

-MDC_PAD_O <= mdc_pad_o_watch;

 data(63 downto 45) <= (others => '0');
 
 data(63 downto 45) <= (others => '0');
 

+MDC_PAD_O <= mdc_pad_o_watch;
+

 trig0(31 downto 0) <= (
        0 => wb_stb_i,
 trig0(31 downto 0) <= (
        0 => wb_stb_i,

-       1 => MD_PAD_IO,
+       1 => md_pad_i,

        2 => md_pad_o,
        3 => md_padoe_o,
        others => '0'
        2 => md_pad_o,
        3 => md_padoe_o,
        others => '0'


@@ -317,16 +416,16 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wbm_rty_i => '0',
         wbm_err_i => wb_err_o,
         pci_clk_i => PCI_CLOCK,
         wbm_rty_i => '0',
         wbm_err_i => wb_err_o,
         pci_clk_i => PCI_CLOCK,

-        pci_rst_i => PCI_RSTn,
+        pci_rst_i => pci_rst_i,

         pci_rst_o => pci_rst_o ,
         pci_rst_oe_o => pci_rst_oe_o,
         pci_rst_o => pci_rst_o ,
         pci_rst_oe_o => pci_rst_oe_o,

-        pci_inta_i => PCI_INTAn,
+        pci_inta_i => pci_inta_i,

         pci_inta_o => pci_inta_o,
         pci_inta_oe_o => pci_inta_oe_o,
         pci_req_o => pci_req_o,
         pci_req_oe_o => pci_req_oe_o,
         pci_gnt_i => PCI_GNTn,
         pci_inta_o => pci_inta_o,
         pci_inta_oe_o => pci_inta_oe_o,
         pci_req_o => pci_req_o,
         pci_req_oe_o => pci_req_oe_o,
         pci_gnt_i => PCI_GNTn,

-        pci_frame_i => PCI_FRAMEn,
+        pci_frame_i => pci_frame_i,

         pci_frame_o => pci_frame_o,
         pci_frame_oe_o => pci_frame_oe_o,
         pci_irdy_oe_o => pci_irdy_oe_o,
         pci_frame_o => pci_frame_o,
         pci_frame_oe_o => pci_frame_oe_o,
         pci_irdy_oe_o => pci_irdy_oe_o,


@@ -335,23 +434,23 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP(
         pci_stop_oe_o => pci_stop_oe_o,
         pci_ad_oe_o => pci_ad_oe_o,
         pci_cbe_oe_o => pci_cbe_oe_o,
         pci_stop_oe_o => pci_stop_oe_o,
         pci_ad_oe_o => pci_ad_oe_o,
         pci_cbe_oe_o => pci_cbe_oe_o,

-        pci_irdy_i => PCI_IRDYn,
+        pci_irdy_i => pci_irdy_i,

         pci_irdy_o => pci_irdy_o,
         pci_idsel_i => PCI_IDSEL,
         pci_irdy_o => pci_irdy_o,
         pci_idsel_i => PCI_IDSEL,

-        pci_devsel_i => PCI_DEVSELn,
+        pci_devsel_i => pci_devsel_i,

         pci_devsel_o => pci_devsel_o,
         pci_devsel_o => pci_devsel_o,

-        pci_trdy_i => PCI_TRDYn,
+        pci_trdy_i => pci_trdy_i,

         pci_trdy_o => pci_trdy_o,
         pci_trdy_o => pci_trdy_o,

-        pci_stop_i => PCI_STOPn,
+        pci_stop_i => pci_stop_i,

         pci_stop_o => pci_stop_o,
         pci_stop_o => pci_stop_o,

-        pci_ad_i => PCI_AD,
+        pci_ad_i => pci_ad_i,

         pci_ad_o => pci_ad_o,
         pci_ad_o => pci_ad_o,

-        pci_cbe_i => PCI_CBEn,
+        pci_cbe_i => pci_cbe_i,

         pci_cbe_o => pci_cbe_o,
         pci_cbe_o => pci_cbe_o,

-        pci_par_i => PCI_PAR,
+        pci_par_i => pci_par_i,

         pci_par_o => pci_par_o,
         pci_par_oe_o => pci_par_oe_o,
         pci_par_o => pci_par_o,
         pci_par_oe_o => pci_par_oe_o,

-        pci_perr_i => PCI_PERRn,
+        pci_perr_i => pci_perr_i,

         pci_perr_o => pci_perr_o,
         pci_perr_oe_o => pci_perr_oe_o,
         pci_serr_o => pci_serr_o,
         pci_perr_o => pci_perr_o,
         pci_perr_oe_o => pci_perr_oe_o,
         pci_serr_o => pci_serr_o,


@@ -390,7 +489,7 @@ Inst_eth_top: eth_top PORT MAP(
         mcoll_pad_i => MCOLL_PAD_I,
         mcrs_pad_i => MCRS_PAD_I,
         mdc_pad_o => mdc_pad_o_watch,
         mcoll_pad_i => MCOLL_PAD_I,
         mcrs_pad_i => MCRS_PAD_I,
         mdc_pad_o => mdc_pad_o_watch,

-        md_pad_i => MD_PAD_IO,
+        md_pad_i => md_pad_i,

         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,
         m_wb_cti_o => m_wb_cti_o,
         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,
         m_wb_cti_o => m_wb_cti_o,


@@ -414,7 +513,7 @@ port map (
 eth_dcm : phydcm
 port map (
        CLKIN_IN => PCI_CLOCK,
 eth_dcm : phydcm
 port map (
        CLKIN_IN => PCI_CLOCK,

-       RST_IN => not PCI_RSTn,
+       RST_IN => not pci_rst_i,

        CLKFX_OUT => PHY_CLOCK,
        CLK0_OUT => open,
        LOCKED_OUT => open
        CLKFX_OUT => PHY_CLOCK,
        CLK0_OUT => open,
        LOCKED_OUT => open