+--+-------------------------------------------------------------------------------------------------+\r
+--| |\r
+--| File: pciregs.vhd |\r
+--| |\r
+--| Project: pci32tlite_oc |\r
+--| |\r
+--| Description: Registros PCI |\r
+--| BAR0 is used externally by decoder. |\r
+--| |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| | PCI CONFIGURATION SPACE REGISTERS | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| | INTPIN | 001111 (r) | 3D | 1 | 1 | |\r
+--| +-------------------------------------------------------------------+ |\r
+--| (w*) Reseteable |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | VENDORID (r) Vendor ID register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Identifies manufacturer of device. | |\r
+--| | VENDORIDr : vendorID (generic) | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | DEVICEID (r) Device ID register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Identifies the device. | |\r
+--| | DEVICEIDr : deviceID (generic) | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | CMD (r/w) CoMmanD register | |\r
+--| +-----------------------------------------------+----------------------------+ |\r
+--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) |\r
+--| +----------------------------------------------------------------------------+ |\r
+--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) |\r
+--| +----------------------------------------------------------------------------+ |\r
+--| | SERRENb : System ERRor ENable (1 = Enabled) | |\r
+--| | PERRENb : Parity ERRor ENable (1 = Enabled) | |\r
+--| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | ST (r/w*) STatus register | |\r
+--| +-----------------------------------------------+-------------------------+ |\r
+--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) |\r
+--| +-------------------------------------------------------------------------+ |\r
+--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) |\r
+--| +-------------------------------------------------------------------------+ |\r
+--| | PERRDTb : Parity ERRor DeTected | |\r
+--| | SERRSIb : System ERRor SIgnaled | |\r
+--| | TABORTSIb : Target ABORT SIgnaled | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | REVISIONID (r) Revision ID register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Identifies a device revision. | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| +-----------------------------------------------+ |\r
+--| | CLASSCODE (r) CLASS CODE register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Identifies the generic funtion of the device. | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| +-----------------------------------------------+ |\r
+--| | HEADERTYPE (r) Header Type register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Identifies the layout of the second part of the predefined header. | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | BAR0 (r/w) Base AddRess 0 register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | BAR032MBb(6..0) | -- | (31-24) |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Identifies vendor of add-in board or subsystem. | |\r
+--| | SUBSYSTEMVIDr : subsystemvID (generic) | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | SUBSYSTEMID (r) SUBSYSTEM ID register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Vendor specific. | |\r
+--| | SUBSYTEMIDr : subsytemID (generic) | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | INTLINE (r/w) INTerrupt LINE register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | INTLINEr(7..0) | (7..0) |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| | Interrupt Line routing information | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--| +-----------------------------------------------+ |\r
+--| | INTPIN (r) INTerrupt PIN register | |\r
+--| +-----------------------------------------------+-----------------------+ |\r
+--| | Tells which interrupt pin the device uses: 01=INTA | |\r
+--| +-----------------------------------------------------------------------+ |\r
+--| |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--| |\r
+--| Revision history : |\r
+--| Date Version Author Description |\r
+--| 2005-05-13 R00A00 PAU First alfa revision (eng) |\r
+--| |\r
+--| To do: |\r
+--| |\r
+--+-------------------------------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------+\r
+--| |\r
+--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | \r
+--| |\r
+--| This source file may be used and distributed without |\r
+--| restriction provided that this copyright statement is not |\r
+--| removed from the file and that any derivative work contains |\r
+--| the original copyright notice and the associated disclaimer. |\r
+--| |\r
+--| This source file is free software; you can redistribute it |\r
+--| and/or modify it under the terms of the GNU Lesser General |\r
+--| Public License as published by the Free Software Foundation; |\r
+--| either version 2.1 of the License, or (at your option) any |\r
+--| later version. |\r
+--| |\r
+--| This source is distributed in the hope that it will be |\r
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |\r
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |\r
+--| PURPOSE. See the GNU Lesser General Public License for more |\r
+--| details. |\r
+--| |\r
+--| You should have received a copy of the GNU Lesser General |\r
+--| Public License along with this source; if not, download it |\r
+--| from http://www.opencores.org/lgpl.shtml |\r
+--| |\r
+--+-----------------------------------------------------------------+ \r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| LIBRARIES |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| ENTITY |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+entity pciregs is\r
+generic (\r
+\r
+ vendorID : std_logic_vector(15 downto 0);\r
+ deviceID : std_logic_vector(15 downto 0);\r
+ revisionID : std_logic_vector(7 downto 0);\r
+ subsystemID : std_logic_vector(15 downto 0);\r
+ subsystemvID : std_logic_vector(15 downto 0);\r
+ jcarr1ID : std_logic_vector(31 downto 0);\r
+ jcarr2ID : std_logic_vector(31 downto 0);\r
+ jcarr3ID : std_logic_vector(31 downto 0);\r
+ jcarr4ID : std_logic_vector(31 downto 0);\r
+ jcarr5ID : std_logic_vector(31 downto 0);\r
+ jcarr6ID : std_logic_vector(31 downto 0);\r
+ jcarr7ID : std_logic_vector(31 downto 0);\r
+ jcarr8ID : std_logic_vector(31 downto 0);\r
+ jcarr9ID : std_logic_vector(31 downto 0);\r
+ jcarr10ID : std_logic_vector(31 downto 0);\r
+ jcarr11ID : std_logic_vector(31 downto 0);\r
+ jcarr12ID : std_logic_vector(31 downto 0);\r
+ jcarr13ID : std_logic_vector(31 downto 0);\r
+ jcarr14ID : std_logic_vector(31 downto 0);\r
+ jcarr15ID : std_logic_vector(31 downto 0);\r
+ jcarr16ID : std_logic_vector(31 downto 0);\r
+ jcarr17ID : std_logic_vector(31 downto 0);\r
+ jcarr18ID : std_logic_vector(31 downto 0);\r
+ jcarr19ID : std_logic_vector(31 downto 0);\r
+ jcarr20ID : std_logic_vector(31 downto 0);\r
+ jcarr21ID : std_logic_vector(31 downto 0);\r
+ jcarr22ID : std_logic_vector(31 downto 0);\r
+ jcarr23ID : std_logic_vector(31 downto 0);\r
+ jcarr24ID : std_logic_vector(31 downto 0);\r
+ jcarr25ID : std_logic_vector(31 downto 0);\r
+ jcarr26ID : std_logic_vector(31 downto 0);\r
+ jcarr27ID : std_logic_vector(31 downto 0);\r
+ jcarr28ID : std_logic_vector(31 downto 0);\r
+ jcarr29ID : std_logic_vector(31 downto 0);\r
+ jcarr30ID : std_logic_vector(31 downto 0);\r
+ jcarr31ID : std_logic_vector(31 downto 0);\r
+ jcarr32ID : std_logic_vector(31 downto 0);\r
+ jcarr33ID : std_logic_vector(31 downto 0);\r
+ jcarr34ID : std_logic_vector(31 downto 0);\r
+ jcarr35ID : std_logic_vector(31 downto 0);\r
+ jcarr36ID : std_logic_vector(31 downto 0);\r
+ jcarr37ID : std_logic_vector(31 downto 0);\r
+ jcarr38ID : std_logic_vector(31 downto 0);\r
+ jcarr39ID : std_logic_vector(31 downto 0);\r
+ jcarr40ID : std_logic_vector(31 downto 0);\r
+ jcarr41ID : std_logic_vector(31 downto 0);\r
+ jcarr42ID : std_logic_vector(31 downto 0)\r
+\r
+);\r
+port (\r
+\r
+ -- General \r
+ clk_i : in std_logic;\r
+ nrst_i : in std_logic;\r
+ -- \r
+ adr_i : in std_logic_vector(5 downto 0);\r
+ cbe_i : in std_logic_vector(3 downto 0);\r
+ dat_i : in std_logic_vector(31 downto 0);\r
+ dat_o : out std_logic_vector(31 downto 0);\r
+ --\r
+ wrcfg_i : in std_logic;\r
+ rdcfg_i : in std_logic;\r
+ perr_i : in std_logic;\r
+ serr_i : in std_logic;\r
+ tabort_i : in std_logic;\r
+ --\r
+ bar0_o : out std_logic_vector(31 downto 25);\r
+ perrEN_o : out std_logic;\r
+ serrEN_o : out std_logic;\r
+ memEN_o : out std_logic\r
+ \r
+); \r
+end pciregs;\r
+\r
+\r
+architecture rtl of pciregs is\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| COMPONENTS |\r
+--+-----------------------------------------------------------------------------+\r
+--+-----------------------------------------------------------------------------+\r
+--| CONSTANTS |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+ constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice\r
+ constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81...\r
+ constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; \r
+ constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed\r
+ constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; \r
+ constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; \r
+ constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; \r
+ constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; \r
+ constant JCARR1IDr : std_logic_vector(31 downto 0) := jcarr1ID;\r
+ constant JCARR2IDr : std_logic_vector(31 downto 0) := jcarr2ID;\r
+ constant JCARR3IDr : std_logic_vector(31 downto 0) := jcarr3ID;\r
+ constant JCARR4IDr : std_logic_vector(31 downto 0) := jcarr4ID;\r
+ constant JCARR5IDr : std_logic_vector(31 downto 0) := jcarr5ID;\r
+ constant JCARR6IDr : std_logic_vector(31 downto 0) := jcarr6ID;\r
+ constant JCARR7IDr : std_logic_vector(31 downto 0) := jcarr7ID;\r
+ constant JCARR8IDr : std_logic_vector(31 downto 0) := jcarr8ID;\r
+ constant JCARR9IDr : std_logic_vector(31 downto 0) := jcarr9ID;\r
+ constant JCARR10IDr : std_logic_vector(31 downto 0) := jcarr10ID;\r
+ constant JCARR11IDr : std_logic_vector(31 downto 0) := jcarr11ID;\r
+ constant JCARR12IDr : std_logic_vector(31 downto 0) := jcarr12ID;\r
+ constant JCARR13IDr : std_logic_vector(31 downto 0) := jcarr13ID;\r
+ constant JCARR14IDr : std_logic_vector(31 downto 0) := jcarr14ID;\r
+ constant JCARR15IDr : std_logic_vector(31 downto 0) := jcarr15ID;\r
+ constant JCARR16IDr : std_logic_vector(31 downto 0) := jcarr16ID;\r
+ constant JCARR17IDr : std_logic_vector(31 downto 0) := jcarr17ID;\r
+ constant JCARR18IDr : std_logic_vector(31 downto 0) := jcarr18ID;\r
+ constant JCARR19IDr : std_logic_vector(31 downto 0) := jcarr19ID;\r
+ constant JCARR20IDr : std_logic_vector(31 downto 0) := jcarr20ID;\r
+ constant JCARR21IDr : std_logic_vector(31 downto 0) := jcarr21ID;\r
+ constant JCARR22IDr : std_logic_vector(31 downto 0) := jcarr22ID;\r
+ constant JCARR23IDr : std_logic_vector(31 downto 0) := jcarr23ID;\r
+ constant JCARR24IDr : std_logic_vector(31 downto 0) := jcarr24ID;\r
+ constant JCARR25IDr : std_logic_vector(31 downto 0) := jcarr25ID;\r
+ constant JCARR26IDr : std_logic_vector(31 downto 0) := jcarr26ID;\r
+ constant JCARR27IDr : std_logic_vector(31 downto 0) := jcarr27ID;\r
+ constant JCARR28IDr : std_logic_vector(31 downto 0) := jcarr28ID;\r
+ constant JCARR29IDr : std_logic_vector(31 downto 0) := jcarr29ID;\r
+ constant JCARR30IDr : std_logic_vector(31 downto 0) := jcarr30ID;\r
+ constant JCARR31IDr : std_logic_vector(31 downto 0) := jcarr31ID;\r
+ constant JCARR32IDr : std_logic_vector(31 downto 0) := jcarr32ID;\r
+ constant JCARR33IDr : std_logic_vector(31 downto 0) := jcarr33ID;\r
+ constant JCARR34IDr : std_logic_vector(31 downto 0) := jcarr34ID;\r
+ constant JCARR35IDr : std_logic_vector(31 downto 0) := jcarr35ID;\r
+ constant JCARR36IDr : std_logic_vector(31 downto 0) := jcarr36ID;\r
+ constant JCARR37IDr : std_logic_vector(31 downto 0) := jcarr37ID;\r
+ constant JCARR38IDr : std_logic_vector(31 downto 0) := jcarr38ID;\r
+ constant JCARR39IDr : std_logic_vector(31 downto 0) := jcarr39ID;\r
+ constant JCARR40IDr : std_logic_vector(31 downto 0) := jcarr40ID;\r
+ constant JCARR41IDr : std_logic_vector(31 downto 0) := jcarr41ID;\r
+ constant JCARR42IDr : std_logic_vector(31 downto 0) := jcarr42ID;\r
+ constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA#\r
+\r
+\r
+--+-----------------------------------------------------------------------------+\r
+--| SIGNALS |\r
+--+-----------------------------------------------------------------------------+\r
+\r
+ signal dataout : std_logic_vector(31 downto 0);\r
+ signal tabortPFS : std_logic;\r
+ signal serrPFS : std_logic;\r
+ signal perrPFS : std_logic;\r
+ signal adrSTCMD : std_logic;\r
+ signal adrBAR0 : std_logic;\r
+ signal adrINT : std_logic;\r
+ signal we0CMD : std_logic;\r
+ signal we1CMD : std_logic;\r
+ signal we3ST : std_logic;\r
+ signal we3BAR0 : std_logic;\r
+ signal we0INT : std_logic;\r
+ signal we1INT : std_logic;\r
+ signal st11SEN : std_logic;\r
+ signal st11REN : std_logic;\r
+ signal st14SEN : std_logic;\r
+ signal st14REN : std_logic;\r
+ signal st15SEN : std_logic;\r
+ signal st15REN : std_logic;\r
+\r
+\r
+ --+---------------------------------------------------------+\r
+ --| CONFIGURATION SPACE REGISTERS |\r
+ --+---------------------------------------------------------+\r
+\r
+ -- INTERRUPT LINE register \r
+ signal INTLINEr : std_logic_vector(7 downto 0);\r
+ -- COMMAND register bits\r
+ signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit)\r
+ signal PERRENb : std_logic; -- Parity ERRor ENable (bit)\r
+ signal SERRENb : std_logic; -- SERR ENable (bit)\r
+ -- STATUS register bits\r
+ --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits)\r
+ signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit)\r
+ signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit)\r
+ signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit)\r
+ -- BAR0 register bits\r
+ signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits)\r
+ \r
+\r
+component pfs\r
+port (\r
+ clk : in std_logic;\r
+ a : in std_logic;\r
+ y : out std_logic\r
+); \r
+\r
+end component;\r
+\r
+begin\r
+\r
+ --+-------------------------------------------------------------------------+\r
+ --| Component instances |\r
+ --+-------------------------------------------------------------------------+\r
+\r
+ u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS );\r
+ u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS );\r
+ u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS );\r
+ \r
+\r
+ --+-------------------------------------------------------------------------+\r
+ --| Registers Address Decoder |\r
+ --+-------------------------------------------------------------------------+\r
+\r
+ adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0';\r
+ adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0';\r
+ adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0';\r
+\r
+\r
+ --+-------------------------------------------------------------------------+\r
+ --| WRITE ENABLE REGISTERS |\r
+ --+-------------------------------------------------------------------------+\r
+\r
+ --+-----------------------------------------+\r
+ --| Write Enable Registers |\r
+ --+-----------------------------------------+\r
+ \r
+ we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0));\r
+ we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1));\r
+ --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2));\r
+ we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3));\r
+ --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2));\r
+ we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3));\r
+ we0INT <= adrINT and wrcfg_i and (not cbe_i(0));\r
+ --we1INT <= adrINT and wrcfg_i and (not cbe_i(1));\r
+\r
+ --+-----------------------------------------+\r
+ --| Set Enable & Reset Enable bits |\r
+ --+-----------------------------------------+\r
+ st11SEN <= tabortPFS; \r
+ st11REN <= we3ST and dat_i(27);\r
+ st14SEN <= serrPFS; \r
+ st14REN <= we3ST and dat_i(30);\r
+ st15SEN <= perrPFS; \r
+ st15REN <= we3ST and dat_i(31);\r
+\r
+\r
+ --+-------------------------------------------------------------------------+\r
+ --| WRITE REGISTERS |\r
+ --+-------------------------------------------------------------------------+\r
+\r
+ --+---------------------------------------------------------+\r
+ --| COMMAND REGISTER Write |\r
+ --+---------------------------------------------------------+\r
+\r
+ REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i )\r
+ begin\r
+\r
+ if( nrst_i = '0' ) then\r
+ MEMSPACEENb <= '0';\r
+ PERRENb <= '0';\r
+ SERRENb <= '0'; \r
+ elsif( rising_edge( clk_i ) ) then\r
+\r
+ -- Byte 0\r
+ if( we0CMD = '1' ) then\r
+ MEMSPACEENb <= dat_i(1);\r
+ PERRENb <= dat_i(6); \r
+ end if;\r
+ \r
+ -- Byte 1\r
+ if( we1CMD = '1' ) then\r
+ SERRENb <= dat_i(8); \r
+ end if;\r
+\r
+ end if;\r
+\r
+ end process REGCMDWR;\r
+\r
+\r
+ --+---------------------------------------------------------+\r
+ --| STATUS REGISTER WRITE (Reset only) |\r
+ --+---------------------------------------------------------+\r
+\r
+ REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN )\r
+ begin\r
+\r
+ if( nrst_i = '0' ) then\r
+ TABORTSIb <= '0';\r
+ SERRSIb <= '0';\r
+ PERRDTb <= '0';\r
+ elsif( rising_edge( clk_i ) ) then\r
+\r
+ -- TarGet ABORT SIgnaling bit\r
+ if( st11SEN = '1' ) then\r
+ TABORTSIb <= '1';\r
+ elsif ( st11REN = '1' ) then\r
+ TABORTSIb <= '0'; \r
+ end if;\r
+\r
+ -- System ERRor SIgnaling bit\r
+ if( st14SEN = '1' ) then\r
+ SERRSIb <= '1';\r
+ elsif ( st14REN = '1' ) then\r
+ SERRSIb <= '0'; \r
+ end if;\r
+\r
+ -- Parity ERRor DEtected bit\r
+ if( st15SEN = '1' ) then\r
+ PERRDTb <= '1';\r
+ elsif ( st15REN = '1' ) then\r
+ PERRDTb <= '0'; \r
+ end if;\r
+ \r
+ end if;\r
+\r
+ end process REGSTWR;\r
+\r
+\r
+ --+---------------------------------------------------------+\r
+ --| INTERRUPT REGISTER Write |\r
+ --+---------------------------------------------------------+\r
+\r
+ REGINTWR: process( clk_i, nrst_i, we0INT, dat_i )\r
+ begin\r
+\r
+ if( nrst_i = '0' ) then\r
+ INTLINEr <= ( others => '0' );\r
+ elsif( rising_edge( clk_i ) ) then\r
+\r
+ -- Byte 0\r
+ if( we0INT = '1' ) then\r
+ INTLINEr <= dat_i(7 downto 0);\r
+ end if;\r
+ \r
+\r
+ end if;\r
+\r
+ end process REGINTWR;\r
+\r
+\r
+ --+---------------------------------------------------------+\r
+ --| BAR0 32MBytes address space (bits 31-25) |\r
+ --+---------------------------------------------------------+\r
+\r
+ REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i )\r
+ begin\r
+\r
+ if( nrst_i = '0' ) then\r
+ BAR032MBb <= ( others => '1' );\r
+ elsif( rising_edge( clk_i ) ) then\r
+\r
+ -- Byte 3\r
+ if( we3BAR0 = '1' ) then\r
+ BAR032MBb <= dat_i(31 downto 25);\r
+ end if;\r
+ \r
+ end if;\r
+\r
+ end process REGBAR0WR;\r
+\r
+\r
+ --+-------------------------------------------------------------------------+\r
+ --| Registers MUX (READ) |\r
+ --+-------------------------------------------------------------------------+\r
+--+-------------------------------------------------------------------------------------------------+\r
+\r
+ RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, \r
+ INTLINEr, rdcfg_i )\r
+ begin\r
+\r
+ if ( rdcfg_i = '1' ) then\r
+ \r
+ case adr_i is\r
+\r
+ when b"000000" => \r
+ dataout <= DEVICEIDr & VENDORIDr;\r
+ when b"000001" => \r
+ dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" &\r
+ b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0";\r
+ when b"000010" => \r
+ dataout <= CLASSCODEr & REVISIONIDr;\r
+ when b"000100" => \r
+ dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000";\r
+ when b"001011" => \r
+ dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr;\r
+ when b"001111" => \r
+ dataout <= b"0000000000000000" & INTPINr & INTLINEr;\r
+ when b"010001" =>\r
+ dataout <= JCARR1IDr;\r
+ when b"010010" =>\r
+ dataout <= JCARR2IDr;\r
+ when b"010011" =>\r
+ dataout <= JCARR3IDr;\r
+ when b"010100" =>\r
+ dataout <= JCARR4IDr;\r
+ when b"010101" =>\r
+ dataout <= JCARR5IDr;\r
+ when b"010110" =>\r
+ dataout <= JCARR6IDr;\r
+ when b"010111" =>\r
+ dataout <= JCARR7IDr;\r
+ when b"011000" =>\r
+ dataout <= JCARR8IDr;\r
+ when b"011001" =>\r
+ dataout <= JCARR9IDr;\r
+ when b"011010" =>\r
+ dataout <= JCARR10IDr;\r
+ when b"011011" =>\r
+ dataout <= JCARR11IDr;\r
+ when b"011100" =>\r
+ dataout <= JCARR12IDr;\r
+ when b"011101" =>\r
+ dataout <= JCARR13IDr;\r
+ when b"011110" =>\r
+ dataout <= JCARR14IDr;\r
+ when b"011111" =>\r
+ dataout <= JCARR15IDr;\r
+ when b"100000" =>\r
+ dataout <= JCARR16IDr;\r
+ when b"100001" =>\r
+ dataout <= JCARR17IDr;\r
+ when b"100010" =>\r
+ dataout <= JCARR18IDr;\r
+ when b"100011" =>\r
+ dataout <= JCARR19IDr;\r
+ when b"100100" =>\r
+ dataout <= JCARR20IDr;\r
+ when b"100101" =>\r
+ dataout <= JCARR21IDr;\r
+ when b"100110" =>\r
+ dataout <= JCARR22IDr;\r
+ when b"100111" =>\r
+ dataout <= JCARR23IDr;\r
+ when b"101000" =>\r
+ dataout <= JCARR24IDr;\r
+ when b"101001" =>\r
+ dataout <= JCARR25IDr;\r
+ when b"101010" =>\r
+ dataout <= JCARR26IDr;\r
+ when b"101011" =>\r
+ dataout <= JCARR27IDr;\r
+ when b"101100" =>\r
+ dataout <= JCARR28IDr;\r
+ when b"101101" =>\r
+ dataout <= JCARR29IDr;\r
+ when b"101110" =>\r
+ dataout <= JCARR30IDr;\r
+ when b"101111" =>\r
+ dataout <= JCARR31IDr;\r
+ when b"110000" =>\r
+ dataout <= JCARR32IDr;\r
+ when b"110001" =>\r
+ dataout <= JCARR33IDr;\r
+ when b"110010" =>\r
+ dataout <= JCARR34IDr;\r
+ when b"110011" =>\r
+ dataout <= JCARR35IDr;\r
+ when b"110100" =>\r
+ dataout <= JCARR36IDr;\r
+ when b"110101" =>\r
+ dataout <= JCARR37IDr;\r
+ when b"110110" =>\r
+ dataout <= JCARR38IDr;\r
+ when b"110111" =>\r
+ dataout <= JCARR39IDr;\r
+ when b"111000" =>\r
+ dataout <= JCARR40IDr;\r
+ when b"111001" =>\r
+ dataout <= JCARR41IDr;\r
+ when b"111010" =>\r
+ dataout <= JCARR42IDr;\r
+ when others => \r
+ dataout <= ( others => '0' );\r
+\r
+ end case;\r
+ \r
+ else\r
+ \r
+ dataout <= ( others => '0' );\r
+ \r
+ end if;\r
+\r
+ end process RRMUX;\r
+\r
+ dat_o <= dataout;\r
+ \r
+ \r
+ --+-------------------------------------------------------------------------+\r
+ --| BAR0 & COMMAND REGS bits outputs |\r
+ --+-------------------------------------------------------------------------+\r
+ \r
+ bar0_o <= BAR032MBb;\r
+ perrEN_o <= PERRENb;\r
+ serrEN_o <= SERRENb; \r
+ memEN_o <= MEMSPACEENb;\r
+\r
+ \r
+end rtl;\r
projects / raggedstone / commitdiff