// CVS Revision History
//
// $Log: generic_dpram.v,v $
-// Revision 1.1 2007-02-11 22:05:26 sithglan
+// Revision 1.2 2007-02-11 22:15:39 sithglan
+// define xilinix and fpga
+//
+// Revision 1.1 2007/02/11 22:05:26 sithglan
// += dpram
//
// Revision 1.4 2002/09/28 08:18:52 rherveille
//`include "timescale.v"
-//`define VENDOR_FPGA
-//`define VENDOR_XILINX
+`define VENDOR_FPGA
+`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(