galaxians
[fpga-games] / galaxian / src / mc_clock.v
CommitLineData
782690d0
MG
1//---------------------------------------------------------------------\r
2// FPGA MOONCRESTA CLOCK GEN \r
3//\r
4// Version : 1.00\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14//---------------------------------------------------------------------\r
15\r
16\r
17\r
18module mc_clock(\r
19\r
20I_CLK_18M,\r
21O_CLK_12M,\r
22O_CLK_06M,\r
23O_CLK_06Mn\r
24\r
25);\r
26\r
27input I_CLK_18M;\r
28output O_CLK_12M;\r
29output O_CLK_06M;\r
30output O_CLK_06Mn;\r
31\r
32// 2/3 clock divider(duty 33%)\r
33reg [1:0] clk_ff1,clk_ff2;\r
34//I_CLK 1010101010101010101\r
35//c_ff10 0011110011110011110\r
36//c_ff11 0011000011000011000\r
37//c_ff20 0000110000110000110\r
38//c_ff21 0110000110000110000\r
39//O_12M 0000110110110110110\r
40always @(posedge I_CLK_18M)\r
41begin\r
42 clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1];\r
43 clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
44 clk_ff2[0] <= clk_ff1[0] & clk_ff1[1];\r
45end\r
46always @(negedge I_CLK_18M)\r
47 clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
48\r
49// 2/3 clock (duty 66%)\r
50assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];\r
51 \r
52// 1/3 clock divider (duty 50%)\r
53reg CLK_6M , CLK_6Mn;\r
54always @(posedge O_CLK_12M)\r
55begin\r
56 CLK_6Mn <= CLK_6M;\r
57 CLK_6M <= ~CLK_6M;\r
58end\r
59assign O_CLK_06M = CLK_6M;\r
60assign O_CLK_06Mn = CLK_6Mn;\r
61\r
62\r
63endmodule
Impressum, Datenschutz