--- /dev/null
+#!/bin/sh
+set -x
+
+./romgen/romgen roms/1h.bin GALAXIAN_1H 11 l r e >roms/galaxian_1h.vhd
+./romgen/romgen roms/1k.bin GALAXIAN_1K 11 l r e >roms/galaxian_1k.vhd
+./romgen/romgen roms/7l GALAXIAN_7L 11 l r e >roms/galaxian_7l.vhd
+./romgen/romgen roms/galmidw.u GALAXIAN_U 11 l r e >roms/galaxian_u.vhd
+./romgen/romgen roms/galmidw.v GALAXIAN_V 11 l r e >roms/galaxian_v.vhd
+./romgen/romgen roms/galmidw.w GALAXIAN_W 11 l r e >roms/galaxian_w.vhd
+./romgen/romgen roms/galmidw.y GALAXIAN_Y 11 l r e >roms/galaxian_y.vhd
+./romgen/romgen roms/6l.bpr GALAXIAN_6L 5 b r e >roms/galaxian_6l.vhd
+
+#./romgen mc_wav_2.bin GALAXIAN_WAV 18 l r e >roms/galaxian_wav.vhd
--- /dev/null
+#/bin/sh
+
+set -x
+
+name=galaxian
+rom_path=roms/
+echo use build_xst /xil to skip synthesis stage.
+
+rm -rf build/
+mkdir -p build
+cd build/
+
+cp -r ../src .
+cp -r ../t80_ip .
+cp ../roms/*.vhd .
+cp ../${name}.ucf ${name}.ucf
+cp ../${name}.ut .
+cp ../${name}.scr .
+cp ../${name}.prj .
+echo "work" >${name}.lso
+
+xst -ifn ${name}.scr -ofn ${name}.srp
+
+ngdbuild -nt on -uc ${name}.ucf ${name}.ngc ${name}.ngd
+map -pr b ${name}.ngd -o ${name}.ncd ${name}.pcf
+par -w -ol high ${name}.ncd ${name}.ncd ${name}.pcf
+trce -v 10 -o ${name}.twr ${name}.ncd ${name}.pcf
+bitgen ${name}.ncd ${name}.bit -w -f ${name}.ut
+
+echo Done
--- /dev/null
+**************************************************************************************************\r
+* 2004- 9-24 Katsumi Degawa *\r
+* ALTERA(CYCLONE)-FPGA-GALAXIAN \82Ö\82æ\82¤\82±\82» *\r
+* *\r
+**************************************************************************************************\r
+\81y\81@ \82Í\82¶\82ß\82É\81@ \81z\r
+\81@\81@\82±\82ÌALTERA(CYCLONE)-FPGA-GALAXIAN\82Í\81A1980\94N\91ã\82É\8f\89\82ß\82É\94\95\\82³\82ê\81@\83Q\81[\83\80\83Z\83\93\83^\81[\82È\82Ç\82Å\8a\88\96ô\81H\r
+\81@\82µ\82Ä\82¢\82½\81@\8aî\94Â\82Æ\89ñ\98H\90}\82ð\8c³\82ÉVerilogHDL\82Å\90Ý\8cv\82µ\81AFPGA\82Å\93®\8dì\82·\82é\82æ\82¤\82É\82µ\82½\82à\82Ì\82Å\82·\81B\r
+\r
+\81y\81@\95Ï\8dX\93_\81Fv2.50\81@\81z\r
+\r
+\81@\81@1.T80_IP\82Å\82Í\81A1.5MHz\93®\8dì\82Å\82µ\82½\82ª\81@V2.50\82©\82ç\81@3.0MHz\82Å\93®\8dì\82µ\82Ä\82¢\82Ü\82·.\r
+\r
+\81@\81@2.V1.xx\82Å\82Í\81A\83f\83o\83C\83X\82âCPU_IP\82É\82æ\82Á\82Ä\95ª\82©\82ê\82Ä\82¢\82½\83t\83@\83C\83\8b\82ð\88ê\82Â\82É\91\8d\8d\87\82µ\82Ü\82µ\82½\81B\r
+\r
+\81@\81@\81@\82½\82¾\82µ\81@\83f\83o\83C\83X\82É\82æ\82è\8d\\92z\95û\96@\82ª\88Ù\82È\82é\82½\82ß\81@\83f\83o\83C\83X\95Ê\82Ì\83e\83L\83X\83g\82ð\8eQ\8fÆ\82µ\82Ä\89º\82³\82¢\81B\r
+\r
+\81y\81@\95K\97v\82ÈHARD\81@\81z\r
+\81@1.\81@ALTERA\81@CPLD.FPGA\8aJ\94Tool\81@¢Quartus II 4.0 SP1 Web Edition£\81@\82ª\93®\8dì\82·\82éPC\r
+\81@\81@\81@ *OS\82Í\81AWINDOWS2000\81@or\81@WINDOWS\81@XP \r
+\r
+\81@2.\81@ALTERA BYTE BLASTER-MV Parallel Port Download Cable \96\94\82Í\81AEPCS4(Config-ROM)\82É\8f\91\82«\8d\9e\82Þ\8fê\8d\87\82Í\81A\r
+\81@\81@\81@ALTERA BYTE BLASTER-\87U Parallel Port Download Cable\81@\82ª\95K\97v\81B\r
+\r
+\81@3.\81@ALTERA FPGA DEVICE\r
+\r
+\81y\81@\95K\97v\82ÈSOFT\81@\81z\r
+\81@1.\81@ALTERA_Quartus\87U_WebEdition_ver4.0\r
+\81@\81@\81@\89º\8bLURL\82æ\82è\81@\83_\83E\83\93\83\8d\81[\83h\82µ\82Ä\82\82¾\82³\82¢\81B\8bN\93®\82·\82é\82½\82ß\82É\82Í\81A\83\89\83C\83Z\83\93\83X\82ª\95K\97v\82É\82È\82é\82Ì\82ÅFree\82Ì\r
+\81@\81@\81@\83\89\83C\83Z\83\93\83X\82ð\8eæ\93¾\82µ\82Ä\82\82¾\82³\82¢\81B\r
+\81@\81@\81@http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html\r
+\r
+\81@2.\81@bhc.exe /* Binary data <-> Intel Hex data Converter Ver 1.0.3 */\r
+ \89º\8bLURL\82æ\82è\81@\83_\83E\83\93\83\8d\81[\83h\82µ\82Ä\82\82¾\82³\82¢\81B \89ð\93\80\8cã\81@bhc.exe\82ð"\make_rom"\83t\83H\83\8b\83_\82É\83R\83s\81[ \82·\82é\81B\r
+\81@\81@\81@http://www.vector.co.jp/soft/win95/util/se057995.html\81@\r
+\r
+\81y\81@GALAXIAN ROM-\8d\\92z\81@\81z\r
+\81@1.\81@GALAXIAN \8aî\94Â\82ÌROM\83f\81[\83^\82ð\89º\8bLFile\96¼\82Å\83R\83s\81[\82·\82é\81B\r
+\r
+\81@\81@ IC(ROM) \81@ \81@\81@ADDERSS (SIZE)\81@\81@\81@\81@\81@File-Name\r
+ 7H \81@0x0000 - 0x07FF(0x0800) galmidw.u\r
+ 0x0800 - 0x0FFF(0x0800) galmidw.v\r
+ 0x1000 - 0x17FF(0x0800) galmidw.w\r
+ 0x1800 - 0x1FFF(0x0800) galmidw.y\r
+ 7L \81@0x2000 - 0x27FF(0x0800) 7l\r
+ 1K (0x0800) 1k.bin\r
+ 1H (0x0800) 1h.bin\r
+ 6L (0x0020) 6l.bpr\r
+\r
+ \81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@* File\96¼\82Í\81A\83A\81[\83P\81[\83h\83G\83~\83\85\83\8c\81[\83^\81[\82Æ\82µ\82Ä\8dÅ\82à\97L\96¼\82È\r
+\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@M.A.M.E(http://www.mame.net/)\82É\8d\87\82í\82¹\82Ä\82¢\82Ü\82·. \r
+\r
+\81@2.\81@1.\82ÌROM-File\82ð"\make_rom"\83t\83H\83\8b\83_\82É\83R\83s\81[\82·\82é\81B\r
+\81@3.\81@make_rom.bat \82ð\8eÀ\8ds\r
+\r
+ address map\r
+ --------------------------------------------------\r
+ 0x00000 - 0x007FF galmidw.u CPU-ROM\r
+ 0x00800 - 0x00FFF galmidw.v CPU-ROM\r
+ 0x01000 - 0x017FF galmidw.w CPU-ROM\r
+ 0x01800 - 0x01FFF galmidw.y CPU-ROM\r
+ 0x02000 - 0x027FF 7l CPU-ROM\r
+ 0x04000 - 0x047FF 1k.bin VID-ROM\r
+ 0x05000 - 0x057FF 1h.bin VID-ROM \r
+ 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data \r
+\r
+\81@4.\81@galaxian_sf.bin\81@\82ðROM \82É\83_\83E\83\93\83\8d\81[\83h\82·\82é\81B\r
+\81@\81@\81@\81@ROM \82Í\81A\97e\97Ê\82ª\81@2Mbit\81@\88È\8fã\82ÌEP-ROM\81@or\81@EEP-ROM\81@\82ð\8eg\97p\82·\82é\81B\r
+ 5.\81@galaxian_prj\83t\83H\83\8b\83_\89º\82É\81@6l.hex\81@\82ª\8fo\97\88\82Ä\82¢\82é\82±\82Æ\82ð\8am\94F\82µ\82Ä\82\82¾\82³\82¢\81B\r
+\81@\81@\81@\81@\r
+\81y\81@ALTERA-FPGA-DATA(mc_top.pof)\82Ì\8dì\90¬\81\95\83_\83E\83\93\83\8d\81[\83h\81@\81z\r
+\82P\81Dgalaxian_prj\83t\83H\83\8b\83_\82Ì\81hmc_top.quartus\81h\82ð\83_\83u\83\8b\83N\83\8a\83b\83N\82µ\82ÄQuartus\87U\82ð\8bN\93®\82µ\82Ä\82\82¾\82³\82¢\81B\r
+\81@\81@FPGA-GALAXIAN \82É\95K\97v\82ÈFile\82ð\89º\8bL\82É\8bL\8dÚ\82µ\82Ü\82·\81B\r
+\r
+ VERILOG_FILE = src\mc_top.v;\r
+ VERILOG_FILE = src\mc_clock.v;\r
+ VERILOG_FILE = src\mc_adec.v;\r
+ VERILOG_FILE = src\mc_inport.v;\r
+ VERILOG_FILE = src\mc_hv_count.v;\r
+ VERILOG_FILE = src\mc_ld_pls.v;\r
+ VERILOG_FILE = src\mc_video.v;\r
+ VERILOG_FILE = src\mc_missile.v;\r
+ VERILOG_FILE = src\mc_stars.v;\r
+ VERILOG_FILE = src\mc_col_pal.v;\r
+ VERILOG_FILE = src\mc_vedio_mix.v;\r
+ VERILOG_FILE = src\mc_vga_if_alt.v;\r
+ VERILOG_FILE = src\mc_sound_a.v;\r
+ VERILOG_FILE = src\mc_sound_b.v;\r
+ VERILOG_FILE = src\mc_logic.v;\r
+ VERILOG_FILE = src\mc_bram_if_alt.v;\r
+ VERILOG_FILE = src\psPAD_conf.v;\r
+ VERILOG_FILE = src\psPAD_top.v;\r
+ VERILOG_FILE = src\fpga_arcade_if.v;\r
+ VERILOG_FILE = src\alt_ram_256_5.v;\r
+ VERILOG_FILE = src\alt_ram_256_8.v;\r
+ VERILOG_FILE = src\alt_ram_1024_8.v;\r
+ VERILOG_FILE = src\alt_rom_6l.v;\r
+ VERILOG_FILE = src\dac.v;\r
+ VERILOG_FILE = src\z80ip.v;\r
+ VHDL_FILE = t80_ip\T80_Pack.vhd;\r
+ VHDL_FILE = t80_ip\T80_ALU.VHD;\r
+ VHDL_FILE = t80_ip\T80_MCode.vhd;\r
+ VHDL_FILE = t80_ip\T80_Reg.vhd;\r
+ VHDL_FILE = t80_ip\T80.VHD;\r
+ VHDL_FILE = t80_ip\T80as.vhd;\r
+\r
+\82Q\81DFPGA\82ÌIN/OUT\82ÌPIN\94z\92u\82Ì\90Ý\92è\82ð\82µ\82Ä\82\82¾\82³\82¢\81B\r
+\r
+\82R\81Dplaystation\82Ì\83R\83\93\83g\83\8d\81[\83\89\82ð\8eg\97p\82·\82é\8fê\8d\87\82Í\81Amc_conf.v \82Ì\81@\81h`define PSPAD_USE\81h\82Ì\r
+\81@\81@\83R\83\81\83\93\83g\83A\83E\83g\82ð\8aO\82µ\82Ä\89º\82³\82¢.\r
+\81@\81@\81@\81@\81@//\81@`define PSPAD_USE\81@\81@\81Ë\81@`define PSPAD_USE\r
+\r
+\82S\81D\83\82\83j\83^\82Í\81APC\97p\82ÌVGA\83\82\83j\83^\82ð\90\84\8f§\82µ\82Ü\82·.\81@\82µ\82©\82µ16KH\82\9a(H).60Hz(V)\82ÌRGB\83\82\83j\83^\82à\8eg\97p\82·\82é\r
+\81@\81@\82±\82Æ\82ª\8fo\97\88\82Ü\82·.\81@\82±\82Ì\8fê\8d\87\81Amc_conf.v \82Ì\81@\81h`define VGA_USE\81h\82ð\83R\83\81\83\93\83g\83A\83E\83g\82µ\82Ä\89º\82³\82¢.\r
+\81@\81@\81@\81@\81@\81@`define VGA_USE\81@\81@\81Ë\81@// `define VGA_USE\r
+\r
+\82T\81DQuartus\87U\81ËProcessing\81ËStart Compilation \82ð\83N\83\8a\83b\83N\82µ\82Ä\83R\83\93\83p\83C\83\8b\82ð\8eÀ\8ds\r
+\81@\81@\81@\81@\81@\81@\81@\r
+\81@\81@Fitting\82ª\90¬\8c÷\82·\82é\82Æ\89º\8bL\83\81\83b\83Z\81[\83W\82ª\95\\8e¦\82³\82ê\82Ü\82·\81B\r
++---------------------------------------------------------------+\r
+; Fitter Summary ;\r
++-----------------------+---------------------------------------+\r
+; Fitter Status ; Successful - Sat Sep 18 12:34:48 2004 ;\r
+; Revision Name ; mc_top ;\r
+; Top-level Entity Name ; mc_top ;\r
+; Family ; Cyclone ;\r
+; Device ; EP1C12Q240C8 ;\r
+; Total logic elements ; 3,046 / 12,060 ( 23 % ) ;\r
+; Total pins ; 59 / 173 ( 34 % ) ;\r
+; Total memory bits ; 24,064 / 239,616 ( 10 % ) ;\r
+; Total PLLs ; 0 / 2 ( 0 % ) ;\r
++-----------------------+---------------------------------------+\r
+\r
+\82U\81DQuartus\87U\82É\82æ\82Á\82Ä\90¶\90¬\82³\82ê\82½\81hmc_top.pof\81h\82ð\83_\83E\83\93\83\8d\81[\83h\82µ\82Ä\8a®\97¹\82Å\82·\81B\r
+\r
+\81y\81@FPGA-MoonCresta \83R\83\93\83g\83\8d\81[\83\8b\81@\81z\r
+\81@\81y I_PSW[4:0] \81z\r
+\81@LEFT 1P/2P : LEFT (I_SW[2])\r
+\81@RIGHT 1P/2P : RIGHT (I_SW[3])\r
+\81@UP 1P/2P : UP (I_SW[0]) ... NOT USE\r
+\81@DOWN 1P/2P : DOWN (I_SW[1]) ... NOT USE\r
+\81@FIRE\81@1P/2P : JP (I_SW[4])\r
+\81@START 1P : LEFT + JP \r
+\81@START 2P : RIGHT + JP\r
+\81@COIN1 : LEFT + RIGHT + UP (and DOWN off)\r
+\r
+ \81y PS_PAD \81z\r
+\81@LEFT 1P/2P : LEFT\81@\81iRight Joystick\81j\r
+\81@RIGHT 1P/2P : RIGHT \81iRight Joystick\81j\r
+\81@UP 1P/2P : UP \81iRight Joystick\81j ... NOT USE\r
+\81@DOWN 1P/2P : DOWN \81iRight Joystick\81j ... NOT USE\r
+\81@FIRE\81@1P/2P : \81« \r
+\81@START 1P : START\r
+\81@START 2P : SELCT\r
+\81@COIN1 : \81\9b\r
+\r
+ Enjoy!\r
+\81@\r
+\81y\81@\92\98\8dì\8c \81\95\96Æ\90Ó\81@\81z\r
+\81@fpga-galaxian\81@\82Ì\92\98\8dì\8c \82Í\81AKatsumi Degawa \82É\91®\82µ\82Ü\82·.\r
+\81@fpga-mooncresta\82Ì\92\98\8dì\8c \82Í\81AKatsumi Degawa \82É\91®\82µ\82Ü\82·.\r
+\81@pspad\81@\81@\81@ \82Ì\92\98\8dì\8c \82Í\81AKatsumi Degawa \82É\91®\82µ\82Ü\82·.\r
+\81@T80(Z80_IP)\81@\81@\82Ì\92\98\8dì\8c \82Í\81ADaniel Wallner\8e\81 \82É\91®\82µ\82Ü\82·.\r
+\r
+\81@\96{\83\\81[\83X\83t\83@\83C\83\8b\82ð\8eg\97p\82µ\82½\82±\82Æ\82É\82æ\82è\90¶\82¶\82½\82¢\82©\82È\82é\8fá\8aQ\81A\91¹\8aQ\82É\82¨\82¢\82Ä\8dì\8eÒ\82Í\88ê\90Ø\90Ó\94C\82ð\95\89\82í\r
+ \82È\82¢\82à\82Ì\82Æ\82µ\82Ü\82·\81B\r
+\81@\8ae\8e©\82Ì\90Ó\94C\82É\82¨\82¢\82Ä\8eg\97p\82µ\82Ä\82\82¾\82³\82¢\81B\r
+\r
+\81y\81@\98A\97\8d\90æ\81@\81z\r
+\81@\82²\88Ó\8c©\81A\82²\97v\96]\93\99\82 \82è\82Ü\82è\82½\82ç\90¥\94ñ\88È\89º\82Ì\82Ü\82Å\82²\98A\97\8d\82ð\82¨\8aè\82¢\82µ\82Ü\82·\81B\r
+\81@\82½\82¾\82µROM\83C\83\81\81[\83W\93\99\82Ì\82²\8e¿\96â\82Í\81A\82¨\93\9a\82¦\82Å\82«\82Ü\82¹\82ñ\81B\r
+\r
+ E-mail : office_dsan@infoseek.jp\r
+\r
--- /dev/null
+**************************************************************************************************\r
+* 2004- 9-24 Katsumi Degawa *\r
+* XILINX(SPARTAN\87UE)-FPGA-GALAXIAN \82Ö\82æ\82¤\82±\82» *\r
+* *\r
+**************************************************************************************************\r
+\81y\81@ \82Í\82¶\82ß\82É\81@ \81z\r
+ \82±\82ÌXILINX(SPARTAN\87UE)-FPGA-MOONCRESTA\82Í\81A1980\94N\91ã\82É\8f\89\82ß\82É\94\95\\82³\82ê\81@\83Q\81[\83\80\83Z\83\93\83^\81[\82È\82Ç\82Å\8a\88\96ô\81H\r
+\81@ \82µ\82Ä\82¢\82½\81@\8aî\94Â\82Æ\89ñ\98H\90}\82ð\8c³\82ÉVerilogHDL\82Å\90Ý\8cv\82µ\81AFPGA\82Å\93®\8dì\82·\82é\82æ\82¤\82É\82µ\82½\82à\82Ì\82Å\82·\81B\r
+\r
+\81y\81@\95Ï\8dX\93_\81Fv2.50\81@\81z\r
+\r
+\81@\81@1.T80_IP\82Å\82Í\81A1.5MHz\93®\8dì\82Å\82µ\82½\82ª\81@V2.50\82©\82ç\81@3.0MHz\82Å\93®\8dì\82µ\82Ä\82¢\82Ü\82·.\r
+\r
+\81@\81@2.V1.xx\82Å\82Í\81A\83f\83o\83C\83X\82âCPU_IP\82É\82æ\82Á\82Ä\95ª\82©\82ê\82Ä\82¢\82½\83t\83@\83C\83\8b\82ð\88ê\82Â\82É\91\8d\8d\87\82µ\82Ü\82µ\82½\81B\r
+\r
+\81@\81@\81@\82½\82¾\82µ\81@\83f\83o\83C\83X\82É\82æ\82è\8d\\92z\95û\96@\82ª\88Ù\82È\82é\82½\82ß\81@\83f\83o\83C\83X\95Ê\82Ì\83e\83L\83X\83g\82ð\8eQ\8fÆ\82µ\82Ä\89º\82³\82¢\81B\r
+\r
+\81y\81@\95K\97v\82ÈHARD\81@\81z\r
+\81@1.\81@XILINX\81@CPLD.FPGA\8aJ\94Tool\81@¢XILINX ISE6.2SP3 Webpack£\81@\82ª\93®\8dì\82·\82éPC\r
+\81@\81@\81@*OS\82Í\81AWINDOWS2000\81@or\81@WINDOWS\81@XP \r
+\r
+\81@2.\81@Xilinx Parallel Port Download Cable\r
+\r
+\81@3.\81@XILINX FPGA DEVICE\r
+\r
+\81y\81@\95K\97v\82ÈSOFT\81@\81z\r
+\81@1.\81@XILINX ISE6.2SP3 Webpack\r
+\81@\81@\81@\89º\8bLURL\82æ\82è\81@\83_\83E\83\93\83\8d\81[\83h\82µ\82Ä\82\82¾\82³\82¢\81B\81@\93o\98^\82ª\95K\97v\81B\r
+ http://www.xilinx.co.jp/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack\r
+\r
+\81y\81@GALAXIAN ROM-\8d\\92z\81@\81z\r
+\81@1.\81@GALAXIAN \8aî\94Â\82ÌROM\83f\81[\83^\82ð\89º\8bLFile\96¼\82Å\83R\83s\81[\82·\82é\81B\r
+\r
+\81@\81@ IC(ROM) \81@ \81@\81@ADDERSS (SIZE)\81@\81@\81@\81@\81@File-Name\r
+ 7H \81@0x0000 - 0x07FF(0x0800) galmidw.u\r
+ 0x0800 - 0x0FFF(0x0800) galmidw.v\r
+ 0x1000 - 0x17FF(0x0800) galmidw.w\r
+ 0x1800 - 0x1FFF(0x0800) galmidw.y\r
+ 7L \81@0x2000 - 0x27FF(0x0800) 7l\r
+ 1K (0x0800) 1k.bin\r
+ 1H (0x0800) 1h.bin\r
+ 6L (0x0020) 6l.bpr\r
+\r
+ \81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@* File\96¼\82Í\81A\83A\81[\83P\81[\83h\83G\83~\83\85\83\8c\81[\83^\81[\82Æ\82µ\82Ä\8dÅ\82à\97L\96¼\82È\r
+\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@\81@M.A.M.E(http://www.mame.net/)\82É\8d\87\82í\82¹\82Ä\82¢\82Ü\82·. \r
+\r
+\81@2.\81@1.\82ÌROM-File\82ð"\make_rom"\83t\83H\83\8b\83_\82É\83R\83s\81[\82·\82é\81B\r
+\81@3.\81@make_rom.bat \82ð\8eÀ\8ds\r
+\r
+ address map\r
+ --------------------------------------------------\r
+ 0x00000 - 0x007FF galmidw.u CPU-ROM\r
+ 0x00800 - 0x00FFF galmidw.v CPU-ROM\r
+ 0x01000 - 0x017FF galmidw.w CPU-ROM\r
+ 0x01800 - 0x01FFF galmidw.y CPU-ROM\r
+ 0x02000 - 0x027FF 7l CPU-ROM\r
+ 0x04000 - 0x047FF 1k.bin VID-ROM\r
+ 0x05000 - 0x057FF 1h.bin VID-ROM \r
+ 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data \r
+\r
+\81@4.\81@galaxian_sf.bin\81@\82ðROM \82É\83_\83E\83\93\83\8d\81[\83h\82·\82é\81B\r
+\81@\81@\81@\81@ROM \82Í\81A\97e\97Ê\82ª\81@2Mbit\81@\88È\8fã\82ÌEP-ROM\81@or\81@EEP-ROM\81@\82ð\8eg\97p\82·\82é\81B\r
+\r
+ 5.\81@mooncrst_prj\83t\83H\83\8b\83_\89º\82É\81@mc_top.ucf & mc_top_pad.ucf\81@\82ª\8fo\97\88\82Ä\82¢\82é\82±\82Æ\82ð\r
+ \8am\94F\82µ\82Ä\82\82¾\82³\82¢\81B\r
+\81@\81@\81@\81@\r
+\81y\81@XILINX-FPGA-DATA(mc_top.bit or mc_top.mcs)\82Ì\8dì\90¬\81\95\83_\83E\83\93\83\8d\81[\83h\81@\81z\r
+\82P\81DFPGA-GALAXIAN \82É\95K\97v\82ÈFile\82ð\89º\8bL\82É\8bL\8dÚ\82µ\82Ü\82·\81B\r
+\r
+ VERILOG_FILE = src\mc_top.v;\81@\81@\r
+ VERILOG_FILE = src\mc_top_pad.v;\r
+ VERILOG_FILE = src\mc_clock.v;\r
+ VERILOG_FILE = src\mc_adec.v;\r
+ VERILOG_FILE = src\mc_inport.v;\r
+ VERILOG_FILE = src\mc_hv_count.v;\r
+ VERILOG_FILE = src\mc_video.v;\r
+ VERILOG_FILE = src\mc_ld_pls.v;\r
+ VERILOG_FILE = src\mc_missile.v;\r
+ VERILOG_FILE = src\mc_stars.v;\r
+ VERILOG_FILE = src\mc_vedio_mix.v;\r
+ VERILOG_FILE = src\mc_col_pal.v;\r
+ VERILOG_FILE = src\mc_sound_a.v;\r
+ VERILOG_FILE = src\mc_sound_b.v;\r
+ VERILOG_FILE = src\mc_vga_if_xlinx.v;\r
+ VERILOG_FILE = src\mc_logic.v;\r
+ VERILOG_FILE = src\mc_bram_if_xlinx.v;\r
+ VERILOG_FILE = src\z80ip_b.v;\r
+ VERILOG_FILE = src\psPAD_conf.v;\r
+ VERILOG_FILE = src\psPAD_top.v;\r
+ VERILOG_FILE = src\fpga_arcade_if.v;\r
+ VERILOG_FILE = src\fpga_arcade_if_x.v;\r
+ VERILOG_FILE = src\dac.v;\r
+ VERILOG_FILE = src\z80ip.v;\r
+ VHDL_FILE = t80_ip\T80_Pack.vhd;\r
+ VHDL_FILE = t80_ip\T80_ALU.VHD;\r
+ VHDL_FILE = t80_ip\T80_MCode.vhd;\r
+ VHDL_FILE = t80_ip\T80_RegX.vhd;\r
+ VHDL_FILE = t80_ip\T80.VHD;\r
+ VHDL_FILE = t80_ip\T80as.vhd;\r
+\r
+\82Q\81DPIN assign\82ð\95Ï\8dX\82·\82é\8fê\8d\87\82Í\81A\81hmc_top.ucf & mc_top_pad.ucf\81h\82ð\95Ò\8fW\82µ\82Ä\82\82¾\82³\82¢.\r
+\r
+\82R\81D\83\82\83j\83^\82Í\81APC\97p\82ÌVGA\83\82\83j\83^\82ð\90\84\8f§\82µ\82Ü\82·.\81@\82µ\82©\82µ16KH\82\9a(H).60Hz(V)\82ÌRGB\83\82\83j\83^\82à\8eg\97p\82·\82é\r
+\81@\81@\82±\82Æ\82ª\8fo\97\88\82Ü\82·.\81@\82±\82Ì\8fê\8d\87\81Amc_top.v \82Ì\81@\81h`define VGA_USE\81h\82ð\83R\83\81\83\93\83g\83A\83E\83g\82µ\82Ä\89º\82³\82¢.\r
+\81@\81@\81@\81@\81@\81@`define VGA_USE\81@\81@\81Ë\81@// `define VGA_USE\r
+\r
+\82S\81Dplaystation\82Ì\83R\83\93\83g\83\8d\81[\83\89\82ð\8eg\97p\82·\82é\8fê\8d\87\82Í\81Amc_conf.v \82Ì\81@\81h`define PSPAD_USE\81h\82Ì\r
+\81@\81@\83R\83\81\83\93\83g\83A\83E\83g\82ð\8aO\82µ\82Ä\89º\82³\82¢.\r
+\81@\81@\81@\81@\81@//\81@`define PSPAD_USE\81@\81@\81Ë\81@`define PSPAD_USE\r
+\r
+\82T\81DZ80_IP\82ÌNGC FILE\82Ì\90¶\90¬\r
+\81@\81y\81@T80\81it80as.ngc\81j\81z\r
+\81@\81@(1)\81@t80_ip.npl\82©\82çProject Navigator\8bN\93®\82·\82é\81B\r
+\81@\81@(2)\81@t80as\82Ìsynthesise \82ð\8eÀ\8ds\82·\82é\81B\r
+\81@\81@(3)\81@prj\83t\83H\83\8b\83_\89º\82Ét80as.ngc\82ª\8fo\97\88\82Ä\82¢\82é\82±\82Æ\82ð\8am\94F\82·\82é\81B\r
+\r
+\82U\81DPSPAD_IP\82ÌNGC FILE\82Ì\90¶\90¬\r
+\81@\81@*PLAYSTATION\83R\83\93\83g\83\8d\81[\83\89\82ð\8eg\97p\82·\82é\8fê\8d\87\82É\95K\97v\82Å\82·.\r
+\81@\81@(1)\81@ps_pad_ip.npl\82©\82çProject Navigator\8bN\93®\82·\82é\81B\r
+\81@\81@(2)\81@fpga_arcade_if\82Ìsynthesise \82ð\8eÀ\8ds\82·\82é\81B\r
+\81@\81@(3)\81@prj\83t\83H\83\8b\83_\89º\82Éfpga_arcade_if.ngc\82ª\8fo\97\88\82Ä\82¢\82é\82±\82Æ\82ð\8am\94F\82·\82é\81B\r
+\r
+\82V\81Dmc_top.bit.mc_top.mcs\82Ì\8dì\90¬\r
+\81@\81@(1)\81@galaxian_prj_v25.npl\82©\82çProject Navigator\8bN\93®\82·\82é\81B\r
+ PLAYSTATION\83R\83\93\83g\83\8d\81[\83\89\82ð\8eg\97p\82·\82é\8fê\8d\87\82Í\81A\r
+\81@\81@\81@\81@ galaxian_prj_v25_p.npl\82©\82çProject Navigator\8bN\93®\82·\82é\81B\r
+\81@\81@(2)\81@Generate Programming File \82ð\8eÀ\8ds\82·\82é\81B\r
+ (3)\81@prj\83t\83H\83\8b\83_\89º\82É mc_top.bit\82ª\8fo\97\88\82Ä\82¢\82é\82±\82Æ\82ð\8am\94F\82·\82é\81B \r
+\81@\81@(4)\81@\83R\83\93\83t\83B\83M\83\85\83\8c\81[\83V\83\87\83\93ROM\82ð\8eg\97p\82·\82é\8fê\8d\87\82ͤGenerate PROM,ACE or JTAG File\r
+\81@\81@\81@\81@ \82ð\8eÀ\8ds\82µ\82Ä\81@mc_top.mcs\81@\83t\83@\83C\83\8b\82ð\8dì\90¬\82µ\82Ä\89º\82³\82¢.\r
+\r
+\82W\81D\90¶\90¬\82³\82ê\82½\81hmc_top.bit\81h\96\94\82ͤ\81hmc_top.mcs\81h\82ð\83_\83E\83\93\83\8d\81[\83h\82µ\82Ä\8a®\97¹\82Å\82·\81B\r
+\r
+\81y\81@FPGA-MoonCresta \83R\83\93\83g\83\8d\81[\83\8b\81@\81z\r
+\81@\81y I_PSW[4:0] \81z\r
+\81@LEFT 1P/2P : LEFT (I_SW[2])\r
+\81@RIGHT 1P/2P : RIGHT (I_SW[3])\r
+\81@UP 1P/2P : UP (I_SW[0]) ... NOT USE\r
+\81@DOWN 1P/2P : DOWN (I_SW[1]) ... NOT USE\r
+\81@FIRE\81@1P/2P : JP (I_SW[4])\r
+\81@START 1P : LEFT + JP \r
+\81@START 2P : RIGHT + JP\r
+\81@COIN1 : LEFT + RIGHT + UP (and DOWN off)\r
+\r
+ \81y PS_PAD \81z\r
+\81@LEFT 1P/2P : LEFT\81@\81iRight Joystick\81j\r
+\81@RIGHT 1P/2P : RIGHT \81iRight Joystick\81j\r
+\81@UP 1P/2P : UP \81iRight Joystick\81j ... NOT USE\r
+\81@DOWN 1P/2P : DOWN \81iRight Joystick\81j ... NOT USE\r
+\81@FIRE\81@1P/2P : \81« \r
+\81@START 1P : START\r
+\81@START 2P : SELCT\r
+\81@COIN1 : \81\9b\r
+\r
+ Enjoy!\r
+\81@\r
+\81y\81@\92\98\8dì\8c \81\95\96Æ\90Ó\81@\81z\r
+\81@fpga-mooncrst\81@\82Ì\92\98\8dì\8c \82Í\81AKatsumi Degawa \82É\91®\82µ\82Ü\82·.\r
+ fpga-galaxian\81@\82Ì\92\98\8dì\8c \82Í\81AKatsumi Degawa \82É\91®\82µ\82Ü\82·.\r
+\81@pspad\81@\81@\81@ \82Ì\92\98\8dì\8c \82Í\81AKatsumi Degawa \82É\91®\82µ\82Ü\82·.\r
+\81@T80(Z80_IP)\81@\81@\82Ì\92\98\8dì\8c \82Í\81ADaniel Wallner\8e\81 \82É\91®\82µ\82Ü\82·.\r
+ binucf.exe \82Ì\92\98\8dì\8c \82Í Tatsuyuki Satoh \8e\81\82É\91®\82µ\82Ü\82·.\r
+\r
+\81@\96{\83\\81[\83X\83t\83@\83C\83\8b\82ð\8eg\97p\82µ\82½\82±\82Æ\82É\82æ\82è\90¶\82¶\82½\82¢\82©\82È\82é\8fá\8aQ\81A\91¹\8aQ\82É\82¨\82¢\82Ä\8dì\8eÒ\82Í\88ê\90Ø\90Ó\94C\82ð\95\89\82í\r
+ \82È\82¢\82à\82Ì\82Æ\82µ\82Ü\82·\81B\r
+\81@\8ae\8e©\82Ì\90Ó\94C\82É\82¨\82¢\82Ä\8eg\97p\82µ\82Ä\82\82¾\82³\82¢\81B\r
+\r
+\81y\81@\98A\97\8d\90æ\81@\81z\r
+\81@\82²\88Ó\8c©\81A\82²\97v\96]\93\99\82 \82è\82Ü\82è\82½\82ç\90¥\94ñ\88È\89º\82Ì\82Ü\82Å\82²\98A\97\8d\82ð\82¨\8aè\82¢\82µ\82Ü\82·\81B\r
+\81@\82½\82¾\82µROM\83C\83\81\81[\83W\93\99\82Ì\82²\8e¿\96â\82Í\81A\82¨\93\9a\82¦\82Å\82«\82Ü\82¹\82ñ\81B\r
+\r
+ E-mail : office_dsan@infoseek.jp\81@\r
+\r
--- /dev/null
+setMode -bs
+setMode -bs
+setCable -port auto
+Identify
+identifyMPM
+assignFile -p 1 -file "build/galaxian.bit"
+Program -p 1
+exit
--- /dev/null
+verilog work "src/dac.v"
+verilog work "src/mc_adec.v"
+verilog work "src/mc_clock.v"
+verilog work "src/mc_col_pal.v"
+verilog work "src/mc_hv_count.v"
+verilog work "src/mc_ld_pls.v"
+verilog work "src/mc_logic.v"
+verilog work "src/mc_missile.v"
+verilog work "src/mc_sound_a.v"
+verilog work "src/mc_sound_b.v"
+verilog work "src/mc_stars.v"
+verilog work "src/mc_top.v"
+verilog work "src/mc_vedio_mix.v"
+verilog work "src/mc_video.v"
+verilog work "src/mc_vga_if.v"
+verilog work "src/mc_bram_if.v"
+verilog work "src/mc_inport.v"
+verilog work "src/mc_conf.v"
+verilog work "src/roms.v"
+verilog work "src/dcm.v"
+#verilog work "src/t80as.v"
+verilog work "src/z80ip.v"
+verilog work "src/fpga_arcade_if_x.v"
+vhdl work "t80_ip/T80.vhd"
+vhdl work "t80_ip/T80_ALU.vhd"
+vhdl work "t80_ip/T80_MCode.vhd"
+vhdl work "t80_ip/T80_Pack.vhd"
+vhdl work "t80_ip/T80_Reg.vhd"
+vhdl work "t80_ip/T80as.vhd"
+vhdl work "galaxian_1h.vhd"
+vhdl work "galaxian_1k.vhd"
+vhdl work "galaxian_6l.vhd"
+vhdl work "galaxian_7l.vhd"
+vhdl work "galaxian_u.vhd"
+vhdl work "galaxian_v.vhd"
+vhdl work "galaxian_w.vhd"
+vhdl work "galaxian_y.vhd"
--- /dev/null
+run\r
+-ifn galaxian.prj\r
+-ifmt mixed\r
+-ofn galaxian.ngc\r
+-ofmt NGC\r
+-p XC3SD1800A-FG676-4\r
+-opt_mode Area\r
+-opt_level 1\r
+-top mc_top\r
+-keep_hierarchy yes\r
--- /dev/null
+### UCF file for FPGA-MOONCRST on XC2S200E
+#
+#---------- MasterClock 18.432MHz ----------
+NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33;
+#-------------------------------------------
+#---------- SW I/F -------------------------
+NET "I_PSW<0>" LOC = "K19" | IOSTANDARD = LVTTL | PULLUP;
+NET "I_PSW<1>" LOC = "F22" | IOSTANDARD = LVTTL | PULLUP;
+NET "I_PSW<2>" LOC = "G22" | IOSTANDARD = LVTTL | PULLUP;
+NET "I_PSW<3>" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP;
+NET "I_PSW<4>" LOC = "F23" | IOSTANDARD = LVTTL | PULLUP;
+#-------------------------------------------
+#--------- EEPROM I/F ----------------------
+#NET "I_ROM_DB<0>" LOC = "P70";
+#NET "I_ROM_DB<1>" LOC = "P68";
+#NET "I_ROM_DB<2>" LOC = "P63";
+#NET "I_ROM_DB<3>" LOC = "P58";
+#NET "I_ROM_DB<4>" LOC = "P60";
+#NET "I_ROM_DB<5>" LOC = "P62";
+#NET "I_ROM_DB<6>" LOC = "P57";
+#NET "I_ROM_DB<7>" LOC = "P59";
+#NET "O_ROM_AB<0>" LOC = "P71";
+#NET "O_ROM_AB<1>" LOC = "P74";
+#NET "O_ROM_AB<2>" LOC = "P73";
+#NET "O_ROM_AB<3>" LOC = "P75";
+#NET "O_ROM_AB<4>" LOC = "P81";
+#NET "O_ROM_AB<5>" LOC = "P82";
+#NET "O_ROM_AB<6>" LOC = "P84";
+#NET "O_ROM_AB<7>" LOC = "P86";
+#NET "O_ROM_AB<8>" LOC = "P89";
+#NET "O_ROM_AB<9>" LOC = "P87";
+#NET "O_ROM_AB<10>" LOC = "P64";
+#NET "O_ROM_AB<11>" LOC = "P83";
+#NET "O_ROM_AB<12>" LOC = "P88";
+#NET "O_ROM_AB<13>" LOC = "P95";
+#NET "O_ROM_AB<14>" LOC = "P97";
+#NET "O_ROM_AB<15>" LOC = "P93";
+#NET "O_ROM_AB<16>" LOC = "P96";
+#NET "O_ROM_AB<17>" LOC = "P98";
+#NET "O_ROM_AB<18>" LOC = "P94";
+#NET "O_ROM_CSn" LOC = "P61";
+#NET "O_ROM_OEn" LOC = "P69";
+#NET "O_ROM_WEn" LOC = "P100";
+#-------------------------------------------
+#--------- SOUND I/F -----------------------
+NET "O_SOUND_OUT_L" LOC = "AA22" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
+NET "O_SOUND_OUT_R" LOC = "V19" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
+#-------------------------------------------
+#--------- VIDEO I/F -----------------------
+NET "O_VGA_R<4>" LOC = "V18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_R<3>" LOC = "F24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_R<2>" LOC = "F25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_R<1>" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_R<0>" LOC = "L20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<4>" LOC = "T17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<3>" LOC = "J22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<2>" LOC = "J23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<1>" LOC = "M18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_G<0>" LOC = "M19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<4>" LOC = "Y25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<3>" LOC = "G24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<2>" LOC = "G23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<1>" LOC = "K21" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_B<0>" LOC = "L22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+
+NET "O_VGA_H_SYNCn" LOC = "K26" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "O_VGA_V_SYNCn" LOC = "K25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+
+
+#-------------------------------------------
+#
+#---------- Build-in ROM -------------------------------------------------------------------------------
+#INST "col_rom00" INIT_00 = c6077600f007f6000700000007a0c00007c4c0003f07d8003fc01600f6000000;
--- /dev/null
+-g DonePin:PULLUP\r
+-g TdoPin:PULLNONE\r
+-g StartUpClk:JTAGCLK\r
+-g DriveDone:Yes\r
--- /dev/null
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string>\r
+#include <math.h>\r
+#include <iostream>\r
+using namespace std;\r
+\r
+#define MAX_ROM_SIZE 0x4000\r
+\r
+int main(int argc, char* argv[])\r
+\r
+{\r
+ cerr << "romgen by MikeJ version 3.00\n";\r
+ // read file\r
+\r
+ string buffer;\r
+ FILE *fin;\r
+\r
+ if(argc < 5)\r
+ {\r
+ cerr << "\nUsage: romgen <input file> <entity name> <number of address bits>\n";\r
+ cerr << " <format> {registered} {enable}\n";\r
+ cerr << "\n";\r
+ cerr << "Now uses bit_vector generics for compatibilty with Xilinx UniSim library\n";\r
+ cerr << "\n";\r
+ cerr << "for the format paramater use :\n";\r
+ cerr << " a - rtl model rom array \n";\r
+ cerr << " c - rtl model case statement \n";\r
+ cerr << " b - Xilinx block ram4 (registered output always)\n";\r
+ cerr << " l - Xilinx block ram16 (registered output always)\n";\r
+ cerr << " d - Xilinx distributed ram [not supported yet]\n";\r
+ cerr << "\n";\r
+ cerr << "for the registered paramater (optional) use :\n";\r
+ cerr << " r - registered output (combinatorial otherwise) \n";\r
+ cerr << "\n";\r
+ cerr << "for the enable paramater (optional) use :\n";\r
+ cerr << " e - clock enable generated \n";\r
+ cerr << "\n";\r
+ cerr << "note, generated roms are always 8 bits wide\n";\r
+ cerr << " max 12 address bits for block ram4s\n";\r
+ cerr << " max 14 address bits for block ram16s\n";\r
+ cerr << "for example romgen fred.bin fred_rom 12 c r\n\n";\r
+ return -1;\r
+ }\r
+\r
+ fin = fopen(argv[1],"rb");\r
+ if (fin == NULL) {\r
+ cerr << "ERROR : Could not open input file " << argv[1] <<"\n";\r
+ return -1;\r
+ }\r
+\r
+ char rom_type = 0;\r
+ char option_1 = 0;\r
+ char option_2 = 0;\r
+ sscanf(argv[4],"%c",&rom_type);\r
+ if (argc > 5) sscanf(argv[5],"%c",&option_1);\r
+ if (argc > 6) sscanf(argv[6],"%c",&option_2);\r
+\r
+ bool format_case = false;\r
+ bool format_array = false;\r
+ bool format_block = false;\r
+ bool format_dist = false;\r
+ bool format_clock = false;\r
+ bool format_ram16 = false;\r
+ bool format_ena = false;\r
+\r
+ cerr << "INFO : creating entity : " << argv[2] << "\n";\r
+\r
+ if (option_1 != 0) {\r
+ if ((option_1 == 'r') || (option_1 == 'R')) \r
+ format_clock = true;\r
+ else if ((option_1 == 'e') || (option_1 == 'E'))\r
+ format_ena = true;\r
+ else {\r
+ cerr << "ERROR : output option not supported\n";\r
+ return -1;\r
+ }\r
+ }\r
+\r
+ // lazy ...\r
+ if (option_2 != 0) {\r
+ if ((option_2 == 'r') || (option_2 == 'R'))\r
+ format_clock = true;\r
+ else if ((option_2 == 'e') || (option_2 == 'E'))\r
+ format_ena = true;\r
+ else {\r
+ cerr << "ERROR : output option not supported\n";\r
+ return -1;\r
+ }\r
+ }\r
+\r
+ if ((rom_type == 'c') || (rom_type == 'C')) {\r
+ cerr << "INFO : rtl model, case statement \n"; format_case = true; }\r
+ else if ((rom_type == 'a') || (rom_type == 'A')) {\r
+ cerr << "INFO : rtl model, rom array \n"; format_array = true; }\r
+ else if ((rom_type == 'b') || (rom_type == 'B')) {\r
+ cerr << "INFO : block4 ram, registered \n"; format_block = true; format_clock = true; }\r
+ else if ((rom_type == 'l') || (rom_type == 'L')) {\r
+ cerr << "INFO : block16 ram, registered \n"; format_block = true; format_clock = true; format_ram16 = true; }\r
+ //else if ((rom_type == 'd') || (rom_type == 'D')) {\r
+ // cerr << "INFO : distributed ram, combinatorial; \n"; format_dist = true; }\r
+ else {\r
+ cerr << "ERROR : format not supported\n";\r
+ return -1;\r
+ }\r
+ if (format_clock == true)\r
+ cerr << "INFO : registered output\n\n";\r
+ else\r
+ cerr << "INFO : combinatorial output\n\n";\r
+\r
+\r
+ // calc number of address bits required\r
+ int addr_bits;\r
+ int max_addr_bits = 16;\r
+ int rom_inits = 16;\r
+\r
+ if (format_block == true) {\r
+ if (format_ram16 == true) {\r
+ max_addr_bits = 14;\r
+ rom_inits = 64;\r
+ }\r
+ else\r
+ max_addr_bits = 12;\r
+ }\r
+\r
+ sscanf(argv[3],"%d",&addr_bits);\r
+ if (addr_bits < 1 || addr_bits > max_addr_bits) {\r
+ cerr << "ERROR : illegal rom size, number of address bits must be between 1 and " << max_addr_bits << "\n";\r
+ return -1;\r
+ }\r
+ // ram b16s\r
+ // for 14 bits use ram_b16_s1 x data_width\r
+ // for 13 bits use ram_b16_s2 x data_width/2\r
+ // for 12 bits use ram_b16_s4 x data_width/4\r
+ // for<=11 bits use ram_b16_s8 x data_width/8\r
+\r
+ // ram b4s\r
+ // for 12 bits use ram_b4_s1 x data_width\r
+ // for 11 bits use ram_b4_s2 x data_width/2\r
+ // for 10 bits use ram_b4_s4 x data_width/4\r
+ // for <=9 bits use ram_b4_s8 x data_width/8\r
+ int rom_size = (int) pow(2,addr_bits);\r
+\r
+ int number_of_block_rams = 1;\r
+ int block_ram_width = 8;\r
+ int block_ram_pwidth = 0;\r
+ int block_ram_abits = 9;\r
+\r
+ if (format_ram16 == true) {\r
+ block_ram_abits = 11; // default\r
+ block_ram_pwidth = 1;\r
+ // ram16s\r
+ switch (addr_bits) {\r
+ case 14 : number_of_block_rams = 8; block_ram_width = 1; block_ram_pwidth = 0; block_ram_abits = 14; break;\r
+ case 13 : number_of_block_rams = 4; block_ram_width = 2; block_ram_pwidth = 0; block_ram_abits = 13; break;\r
+ case 12 : number_of_block_rams = 2; block_ram_width = 4; block_ram_pwidth = 0; block_ram_abits = 12; break;\r
+ default : ;\r
+ }\r
+ }\r
+ else {\r
+ // ram4s\r
+ switch (addr_bits) {\r
+ case 12 : number_of_block_rams = 8; block_ram_width = 1; block_ram_abits = 12; break;\r
+ case 11 : number_of_block_rams = 4; block_ram_width = 2; block_ram_abits = 11; break;\r
+ case 10 : number_of_block_rams = 2; block_ram_width = 4; block_ram_abits = 10; break;\r
+ default : ;\r
+ }\r
+ }\r
+\r
+ //printf("block ram w : %d ",block_ram_width);\r
+ //printf("block ram n : %d ",number_of_block_rams);\r
+\r
+\r
+ // process\r
+ int mem[MAX_ROM_SIZE];\r
+ string line;\r
+\r
+ int i,j,k;\r
+\r
+\r
+ int addr = 0;\r
+ int offset = 0;\r
+ int mask = 0;\r
+ unsigned int data = 0;\r
+\r
+ // clear mem\r
+ for (i = 0; i < MAX_ROM_SIZE; i++) mem[i] = 0;\r
+\r
+ // process file\r
+ data = getc(fin);\r
+ while (!feof(fin) && (addr < rom_size)) {\r
+ if (addr >= MAX_ROM_SIZE) {\r
+ cerr << "ERROR : file too large\n";\r
+ return -1;\r
+ }\r
+\r
+ mem[addr] = data;\r
+ // debug\r
+ //if (addr % 16 == 0) printf("%04x : ",addr);\r
+ //printf("%02x ",data);\r
+ //if (addr % 16 == 15) printf("\n");\r
+ // end debug\r
+ addr ++;\r
+ data = getc(fin);\r
+ }\r
+ fclose(fin);\r
+\r
+\r
+ printf("-- generated with romgen v3.0 by MikeJ\n");\r
+ printf("library ieee;\n");\r
+ printf(" use ieee.std_logic_1164.all;\n");\r
+ printf(" use ieee.std_logic_unsigned.all;\n");\r
+ printf(" use ieee.numeric_std.all;\n");\r
+ printf("\n");\r
+ printf("library UNISIM;\n");\r
+ printf(" use UNISIM.Vcomponents.all;\n");\r
+ printf("\n");\r
+ printf("entity %s is\n",argv[2]);\r
+ printf(" port (\n");\r
+ if (format_clock == true) printf(" CLK : in std_logic;\n");\r
+ if (format_ena == true) printf(" ENA : in std_logic;\n");\r
+ printf(" ADDR : in std_logic_vector(%d downto 0);\n",addr_bits - 1);\r
+ printf(" DATA : out std_logic_vector(7 downto 0)\n");\r
+ printf(" );\n");\r
+ printf("end;\n");\r
+ printf("\n");\r
+ printf("architecture RTL of %s is\n",argv[2]);\r
+ printf("\n");\r
+\r
+ // if blockram\r
+ //{{{\r
+ if (format_block == true) {\r
+ printf(" function romgen_str2bv (str : string) return bit_vector is\n");\r
+ printf(" variable result : bit_vector (str'length*4-1 downto 0);\n");\r
+ printf(" begin\n");\r
+ printf(" for i in 0 to str'length-1 loop\n");\r
+ printf(" case str(str'high-i) is\n");\r
+ for (i = 0; i<16; i++)\r
+ printf(" when '%01X' => result(i*4+3 downto i*4) := x\042%01X\042;\n",i,i);\r
+ printf(" when others => null;\n");\r
+ printf(" end case;\n");\r
+ printf(" end loop;\n");\r
+ printf(" return result;\n");\r
+ printf(" end romgen_str2bv;\n");\r
+ printf("\n");\r
+\r
+ // xilinx block ram component\r
+ if (block_ram_pwidth != 0) {\r
+ for (i = 0; i< 8; i++)\r
+ printf(" attribute INITP_%02X : string;\n",i);\r
+ printf("\n");\r
+ }\r
+\r
+ for (i = 0; i< rom_inits; i++)\r
+ printf(" attribute INIT_%02X : string;\n",i);\r
+ printf("\n");\r
+\r
+ if (format_ram16 == true)\r
+ printf(" component RAMB16_S%d\n",block_ram_width + block_ram_pwidth);\r
+ else\r
+ printf(" component RAMB4_S%d\n",block_ram_width);\r
+\r
+ printf(" --pragma translate_off\n");\r
+ printf(" generic (\n");\r
+ if (block_ram_pwidth != 0) {\r
+ for (i = 0; i< 8; i++) {\r
+ printf(" INITP_%02X : bit_vector (255 downto 0) := x\0420000000000000000000000000000000000000000000000000000000000000000\042",i);\r
+ printf(";\n");\r
+ }\r
+ printf("\n");\r
+ }\r
+\r
+ for (i = 0; i< rom_inits; i++) {\r
+ printf(" INIT_%02X : bit_vector (255 downto 0) := x\0420000000000000000000000000000000000000000000000000000000000000000\042",i);\r
+ if (i< (rom_inits - 1)) printf(";");\r
+ printf("\n");\r
+ }\r
+ printf(" );\n");\r
+ printf(" --pragma translate_on\n");\r
+ printf(" port (\n");\r
+ printf(" DO : out std_logic_vector (%d downto 0);\n",block_ram_width -1);\r
+ if (block_ram_pwidth != 0)\r
+ printf(" DOP : out std_logic_vector (%d downto 0);\n",block_ram_pwidth -1);\r
+ printf(" ADDR : in std_logic_vector (%d downto 0);\n",block_ram_abits -1);\r
+ printf(" CLK : in std_logic;\n");\r
+ printf(" DI : in std_logic_vector (%d downto 0);\n",block_ram_width -1);\r
+ if (block_ram_pwidth != 0)\r
+ printf(" DIP : in std_logic_vector (%d downto 0);\n",block_ram_pwidth -1);\r
+ printf(" EN : in std_logic;\n");\r
+ if (format_ram16 == true)\r
+ printf(" SSR : in std_logic;\n");\r
+ else\r
+ printf(" RST : in std_logic;\n");\r
+ printf(" WE : in std_logic \n");\r
+ printf(" );\n");\r
+ printf(" end component;\n");\r
+ printf("\n");\r
+ printf(" signal rom_addr : std_logic_vector(%d downto 0);\n",block_ram_abits - 1);\r
+ printf("\n");\r
+ }\r
+ //}}}\r
+ //{{{\r
+ if (format_array == true) {\r
+ printf("\n");\r
+ printf(" type ROM_ARRAY is array(0 to %d) of std_logic_vector(7 downto 0);\n",rom_size - 1);\r
+ printf(" constant ROM : ROM_ARRAY := (\n");\r
+ for (i = 0; i < rom_size; i ++ ) {\r
+ if (i % 8 == 0) printf(" ");\r
+ printf("x\042%02X\042",mem[i]);\r
+ if (i < (rom_size - 1)) printf(",");\r
+ if (i == (rom_size - 1)) printf(" ");\r
+ if (i % 8 == 7) printf(" -- 0x%04X\n",i - 7);\r
+ }\r
+ printf(" );\n");\r
+ printf("\n");\r
+ } // end array\r
+ //}}}\r
+ //{{{\r
+ if (format_case == true) {\r
+ printf(" signal rom_addr : std_logic_vector(11 downto 0);\n");\r
+ printf("\n");\r
+ }\r
+ //}}}\r
+\r
+ printf("begin\n");\r
+ printf("\n");\r
+ //\r
+ if ((format_block == true) || (format_case == true)) {\r
+ printf(" p_addr : process(ADDR)\n");\r
+ printf(" begin\n");\r
+ printf(" rom_addr <= (others => '0');\n");\r
+ printf(" rom_addr(%d downto 0) <= ADDR;\n",addr_bits - 1);\r
+ printf(" end process;\n");\r
+ printf("\n");\r
+ }\r
+ //\r
+ //{{{\r
+ if (format_block == true) {\r
+ for (k = 0; k < number_of_block_rams; k ++){\r
+ printf(" rom%d : if true generate\n",k);\r
+\r
+ for (j = 0; j < rom_inits; j++) {\r
+ printf(" attribute INIT_%02X of inst : label is \042",j);\r
+ switch (block_ram_width) {\r
+\r
+ case 1 : // width 1\r
+ mask = 0x1 << (k);\r
+ for (i = 0; i < 256; i+=8) {\r
+ data = ((mem[(j*256) + (255 - i)] & mask) >> k);\r
+ data <<= 1;\r
+ data += ((mem[(j*256) + (254 - i)] & mask) >> k);\r
+ data <<= 1;\r
+ data += ((mem[(j*256) + (253 - i)] & mask) >> k);\r
+ data <<= 1;\r
+ data += ((mem[(j*256) + (252 - i)] & mask) >> k);\r
+ data <<= 1;\r
+ data += ((mem[(j*256) + (251 - i)] & mask) >> k);\r
+ data <<= 1;\r
+ data += ((mem[(j*256) + (250 - i)] & mask) >> k);\r
+ data <<= 1;\r
+ data += ((mem[(j*256) + (249 - i)] & mask) >> k);\r
+ data <<= 1;\r
+ data += ((mem[(j*256) + (248 - i)] & mask) >> k);\r
+ printf("%02X",data);\r
+ }\r
+ break;\r
+\r
+ case 2 : // width 2\r
+ mask = 0x3 << (k * 2);\r
+ for (i = 0; i < 128; i+=4) {\r
+ data = ((mem[(j*128) + (127 - i)] & mask) >> k * 2);\r
+ data <<= 2;\r
+ data += ((mem[(j*128) + (126 - i)] & mask) >> k * 2);\r
+ data <<= 2;\r
+ data += ((mem[(j*128) + (125 - i)] & mask) >> k * 2);\r
+ data <<= 2;\r
+ data += ((mem[(j*128) + (124 - i)] & mask) >> k * 2);\r
+ printf("%02X",data);\r
+ }\r
+ break;\r
+\r
+ case 4 : // width 4\r
+ mask = 0xF << (k * 4);\r
+ for (i = 0; i < 64; i+=2) {\r
+ data = ((mem[(j*64) + (63 - i)] & mask) >> k * 4);\r
+ data <<= 4;\r
+ data += ((mem[(j*64) + (62 - i)] & mask) >> k * 4);\r
+\r
+ printf("%02X",data);\r
+ }\r
+ break;\r
+\r
+\r
+ case 8 : // width 8\r
+ for (i = 0; i < 32; i++) {\r
+ data = ((mem[(j*32) + (31 - i)]));\r
+ printf("%02X",data);\r
+ }\r
+ break;\r
+ } // end switch\r
+\r
+ printf("\042;\n");\r
+ }\r
+\r
+ printf(" begin\n");\r
+ if (format_ram16 == true)\r
+ printf(" inst : RAMB16_S%d\n",block_ram_width + block_ram_pwidth);\r
+ else\r
+ printf(" inst : RAMB4_S%d\n",block_ram_width);\r
+\r
+ printf(" --pragma translate_off\n");\r
+ printf(" generic map (\n");\r
+\r
+ if (block_ram_pwidth != 0) {\r
+ for (i = 0; i< 8; i++) {\r
+ printf(" INITP_%02X => x\0420000000000000000000000000000000000000000000000000000000000000000\042",i);\r
+ printf(",\n");\r
+ }\r
+ printf("\n");\r
+ }\r
+\r
+ for (i = 0; i< rom_inits; i++) {\r
+ printf(" INIT_%02X => romgen_str2bv(inst'INIT_%02X)",i,i);\r
+ if (i< (rom_inits - 1)) printf(",");\r
+ printf("\n");\r
+ }\r
+ printf(" )\n");\r
+ printf(" --pragma translate_on\n");\r
+ printf(" port map (\n");\r
+ printf(" DO => DATA(%d downto %d),\n",((k+1) * block_ram_width)-1,k*block_ram_width);\r
+ if (block_ram_pwidth != 0)\r
+ printf(" DOP => open,\n");\r
+ printf(" ADDR => rom_addr,\n");\r
+ printf(" CLK => CLK,\n");\r
+ printf(" DI => \042");\r
+ for (i = 0; i < block_ram_width -1; i++) printf("0");\r
+ printf("0\042,\n");\r
+ if (block_ram_pwidth != 0) {\r
+ printf(" DIP => \042");\r
+ for (i = 0; i < block_ram_pwidth -1; i++) printf("0");\r
+ printf("0\042,\n");\r
+ }\r
+ if (format_ena == true)\r
+ printf(" EN => ENA,\n");\r
+ else\r
+ printf(" EN => '1',\n");\r
+ //\r
+ if (format_ram16 == true)\r
+ printf(" SSR => '0',\n");\r
+ else\r
+ printf(" RST => '0',\n");\r
+ printf(" WE => '0'\n");\r
+ printf(" );\n");\r
+ printf(" end generate;\n");\r
+ }\r
+ } // end block ram\r
+ //}}}\r
+\r
+ //{{{\r
+ if (format_array == true) {\r
+ if (format_clock == true)\r
+ printf(" p_rom : process\n");\r
+ else\r
+ printf(" p_rom : process(ADDR)\n");\r
+ printf(" begin\n");\r
+ if (format_clock == true)\r
+ printf(" wait until rising_edge(CLK);\n");\r
+ if (format_ena == true)\r
+ printf(" if (ENA = '1') then\n ");\r
+ printf(" DATA <= ROM(to_integer(unsigned(ADDR)));\n");\r
+ if (format_ena == true)\r
+ printf(" end if;\n");\r
+ printf(" end process;\n");\r
+ //}}}\r
+ } // end array\r
+\r
+ //{{{\r
+ if (format_case == true) {\r
+ if (format_clock == true)\r
+ printf(" p_rom : process\n");\r
+ else\r
+ printf(" p_rom : process(rom_addr)\n");\r
+ printf(" begin\n");\r
+ if (format_clock == true)\r
+ printf(" wait until rising_edge(CLK);\n");\r
+ if (format_ena == true)\r
+ printf(" if (ENA = '1') then\n");\r
+\r
+ printf(" DATA <= (others => '0');\n");\r
+ printf(" case rom_addr is\n");\r
+ for (i = 0; i < rom_size; i ++ ) {\r
+ printf(" when x\042%03X\042 => DATA <= x\042%02X\042;\n",i,mem[i]);\r
+ }\r
+ printf(" when others => DATA <= (others => '0');\n");\r
+ printf(" end case;\n");\r
+ if (format_ena == true)\r
+ printf(" end if;\n");\r
+ printf(" end process;\n");\r
+ //}}}\r
+ } // end case\r
+ printf("end RTL;\n");\r
+\r
+ return 0;\r
+}\r
--- /dev/null
+// megafunction wizard: %RAM: 1-PORT%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: altsyncram \r
+\r
+// ============================================================\r
+// File Name: alt_ram_1024_8.v\r
+// Megafunction Name(s):\r
+// altsyncram\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2003 Altera Corporation\r
+//Any megafunction design, and related netlist (encrypted or decrypted),\r
+//support information, device programming or simulation file, and any other\r
+//associated documentation or information provided by Altera or a partner\r
+//under Altera's Megafunction Partnership Program may be used only\r
+//to program PLD devices (but not masked PLD devices) from Altera. Any\r
+//other use of such megafunction design, netlist, support information,\r
+//device programming or simulation file, or any other related documentation\r
+//or information is prohibited for any other purpose, including, but not\r
+//limited to modification, reverse engineering, de-compiling, or use with\r
+//any other silicon devices, unless such use is explicitly licensed under\r
+//a separate agreement with Altera or a megafunction partner. Title to the\r
+//intellectual property, including patents, copyrights, trademarks, trade\r
+//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+//support information, device programming or simulation file, or any other\r
+//related documentation or information provided by Altera or a megafunction\r
+//partner, remains with Altera, the megafunction partner, or their respective\r
+//licensors. No other licenses, including any licenses needed under any third\r
+//party's intellectual property, are provided herein.\r
+\r
+\r
+module alt_ram_1024_8 (\r
+ address,\r
+ clock,\r
+ data,\r
+ wren,\r
+ q);\r
+\r
+ input [9:0] address;\r
+ input clock;\r
+ input [7:0] data;\r
+ input wren;\r
+ output [7:0] q;\r
+\r
+ wire [7:0] sub_wire0;\r
+ wire [7:0] q = sub_wire0[7:0];\r
+\r
+ altsyncram altsyncram_component (\r
+ .wren_a (wren),\r
+ .clock0 (clock),\r
+ .address_a (address),\r
+ .data_a (data),\r
+ .q_a (sub_wire0));\r
+ defparam\r
+ altsyncram_component.intended_device_family = "Cyclone",\r
+ altsyncram_component.width_a = 8,\r
+ altsyncram_component.widthad_a = 10,\r
+ altsyncram_component.numwords_a = 1024,\r
+ altsyncram_component.operation_mode = "SINGLE_PORT",\r
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
+ altsyncram_component.indata_aclr_a = "NONE",\r
+ altsyncram_component.wrcontrol_aclr_a = "NONE",\r
+ altsyncram_component.address_aclr_a = "NONE",\r
+ altsyncram_component.outdata_aclr_a = "NONE",\r
+ altsyncram_component.width_byteena_a = 1,\r
+ altsyncram_component.ram_block_type = "AUTO",\r
+ altsyncram_component.lpm_type = "altsyncram";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"\r
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"\r
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegData NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegOutput NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrData NUMERIC "0"\r
+// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clken NUMERIC "0"\r
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
+// Retrieval info: PRIVATE: MIFfilename STRING ""\r
+// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
+// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"\r
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"\r
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
+// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
+// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]\r
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]\r
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren\r
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0\r
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0\r
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0\r
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
--- /dev/null
+// megafunction wizard: %RAM: 2-PORT%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: altsyncram \r
+\r
+// ============================================================\r
+// File Name: alt_ram_1024_8_8.v\r
+// Megafunction Name(s):\r
+// altsyncram\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2004 Altera Corporation\r
+//Any megafunction design, and related netlist (encrypted or decrypted),\r
+//support information, device programming or simulation file, and any other\r
+//associated documentation or information provided by Altera or a partner\r
+//under Altera's Megafunction Partnership Program may be used only\r
+//to program PLD devices (but not masked PLD devices) from Altera. Any\r
+//other use of such megafunction design, netlist, support information,\r
+//device programming or simulation file, or any other related documentation\r
+//or information is prohibited for any other purpose, including, but not\r
+//limited to modification, reverse engineering, de-compiling, or use with\r
+//any other silicon devices, unless such use is explicitly licensed under\r
+//a separate agreement with Altera or a megafunction partner. Title to the\r
+//intellectual property, including patents, copyrights, trademarks, trade\r
+//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+//support information, device programming or simulation file, or any other\r
+//related documentation or information provided by Altera or a megafunction\r
+//partner, remains with Altera, the megafunction partner, or their respective\r
+//licensors. No other licenses, including any licenses needed under any third\r
+//party's intellectual property, are provided herein.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module alt_ram_1024_8_8 (\r
+ data_a,\r
+ wren_a,\r
+ address_a,\r
+ data_b,\r
+ address_b,\r
+ wren_b,\r
+ clock_a,\r
+ enable_a,\r
+ clock_b,\r
+ enable_b,\r
+ q_a,\r
+ q_b);\r
+\r
+ input [7:0] data_a;\r
+ input wren_a;\r
+ input [9:0] address_a;\r
+ input [7:0] data_b;\r
+ input [9:0] address_b;\r
+ input wren_b;\r
+ input clock_a;\r
+ input enable_a;\r
+ input clock_b;\r
+ input enable_b;\r
+ output [7:0] q_a;\r
+ output [7:0] q_b;\r
+\r
+ wire [7:0] sub_wire0;\r
+ wire [7:0] sub_wire1;\r
+ wire [7:0] q_a = sub_wire0[7:0];\r
+ wire [7:0] q_b = sub_wire1[7:0];\r
+\r
+ altsyncram altsyncram_component (\r
+ .clocken0 (enable_a),\r
+ .clocken1 (enable_b),\r
+ .wren_a (wren_a),\r
+ .clock0 (clock_a),\r
+ .wren_b (wren_b),\r
+ .clock1 (clock_b),\r
+ .address_a (address_a),\r
+ .address_b (address_b),\r
+ .data_a (data_a),\r
+ .data_b (data_b),\r
+ .q_a (sub_wire0),\r
+ .q_b (sub_wire1)\r
+ // synopsys translate_off\r
+,\r
+ .rden_b (),\r
+ .aclr0 (),\r
+ .aclr1 (),\r
+ .byteena_a (),\r
+ .byteena_b (),\r
+ .addressstall_a (),\r
+ .addressstall_b ()\r
+ // synopsys translate_on\r
+\r
+);\r
+ defparam\r
+ altsyncram_component.intended_device_family = "Cyclone",\r
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",\r
+ altsyncram_component.width_a = 8,\r
+ altsyncram_component.widthad_a = 10,\r
+ altsyncram_component.numwords_a = 1024,\r
+ altsyncram_component.width_b = 8,\r
+ altsyncram_component.widthad_b = 10,\r
+ altsyncram_component.numwords_b = 1024,\r
+ altsyncram_component.lpm_type = "altsyncram",\r
+ altsyncram_component.width_byteena_a = 1,\r
+ altsyncram_component.width_byteena_b = 1,\r
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
+ altsyncram_component.outdata_aclr_a = "NONE",\r
+ altsyncram_component.outdata_reg_b = "UNREGISTERED",\r
+ altsyncram_component.indata_aclr_a = "NONE",\r
+ altsyncram_component.wrcontrol_aclr_a = "NONE",\r
+ altsyncram_component.address_aclr_a = "NONE",\r
+ altsyncram_component.indata_reg_b = "CLOCK1",\r
+ altsyncram_component.address_reg_b = "CLOCK1",\r
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",\r
+ altsyncram_component.indata_aclr_b = "NONE",\r
+ altsyncram_component.wrcontrol_aclr_b = "NONE",\r
+ altsyncram_component.address_aclr_b = "NONE",\r
+ altsyncram_component.outdata_aclr_b = "NONE",\r
+ altsyncram_component.ram_block_type = "AUTO";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"\r
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"\r
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"\r
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"\r
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"\r
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"\r
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"\r
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"\r
+// Retrieval info: PRIVATE: Clock NUMERIC "5"\r
+// Retrieval info: PRIVATE: rden NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"\r
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"\r
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"\r
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"\r
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"\r
+// Retrieval info: PRIVATE: REGq NUMERIC "0"\r
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"\r
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"\r
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: enable NUMERIC "1"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"\r
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
+// Retrieval info: PRIVATE: MIFfilename STRING ""\r
+// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "wren_a;wren_b;rden_b;data_a;data_b"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "address_a;address_b;clock0;clock1;clocken0"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "clocken1;aclr0;aclr1;byteena_a;byteena_b"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "addressstall_a;addressstall_b;q_a;q_b"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"\r
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"\r
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"\r
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"\r
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"\r
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"\r
+// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"\r
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"\r
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"\r
+// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
+// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]\r
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a\r
+// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]\r
+// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]\r
+// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL address_a[9..0]\r
+// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]\r
+// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL address_b[9..0]\r
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b\r
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a\r
+// Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC enable_a\r
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b\r
+// Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC enable_b\r
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0\r
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0\r
+// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0\r
+// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0\r
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0\r
+// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0\r
+// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0\r
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0\r
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0\r
+// Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0\r
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0\r
+// Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.inc FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.cmp FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.bsf FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_inst.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_bb.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_wave*.jpg FALSE\r
--- /dev/null
+// megafunction wizard: %RAM: 1-PORT%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: altsyncram \r
+\r
+// ============================================================\r
+// File Name: alt_ram_256_5.v\r
+// Megafunction Name(s):\r
+// altsyncram\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2003 Altera Corporation\r
+//Any megafunction design, and related netlist (encrypted or decrypted),\r
+//support information, device programming or simulation file, and any other\r
+//associated documentation or information provided by Altera or a partner\r
+//under Altera's Megafunction Partnership Program may be used only\r
+//to program PLD devices (but not masked PLD devices) from Altera. Any\r
+//other use of such megafunction design, netlist, support information,\r
+//device programming or simulation file, or any other related documentation\r
+//or information is prohibited for any other purpose, including, but not\r
+//limited to modification, reverse engineering, de-compiling, or use with\r
+//any other silicon devices, unless such use is explicitly licensed under\r
+//a separate agreement with Altera or a megafunction partner. Title to the\r
+//intellectual property, including patents, copyrights, trademarks, trade\r
+//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+//support information, device programming or simulation file, or any other\r
+//related documentation or information provided by Altera or a megafunction\r
+//partner, remains with Altera, the megafunction partner, or their respective\r
+//licensors. No other licenses, including any licenses needed under any third\r
+//party's intellectual property, are provided herein.\r
+\r
+\r
+module alt_ram_256_5 (\r
+ address,\r
+ inclock,\r
+ outclock,\r
+ data,\r
+ wren,\r
+ q);\r
+\r
+ input [7:0] address;\r
+ input inclock;\r
+ input outclock;\r
+ input [4:0] data;\r
+ input wren;\r
+ output [4:0] q;\r
+\r
+ wire [4:0] sub_wire0;\r
+ wire [4:0] q = sub_wire0[4:0];\r
+\r
+ altsyncram altsyncram_component (\r
+ .wren_a (wren),\r
+ .clock0 (inclock),\r
+ .clock1 (outclock),\r
+ .address_a (address),\r
+ .data_a (data),\r
+ .q_a (sub_wire0));\r
+ defparam\r
+ altsyncram_component.intended_device_family = "Cyclone",\r
+ altsyncram_component.width_a = 5,\r
+ altsyncram_component.widthad_a = 8,\r
+ altsyncram_component.numwords_a = 256,\r
+ altsyncram_component.operation_mode = "SINGLE_PORT",\r
+ altsyncram_component.outdata_reg_a = "CLOCK1",\r
+ altsyncram_component.indata_aclr_a = "NONE",\r
+ altsyncram_component.wrcontrol_aclr_a = "NONE",\r
+ altsyncram_component.address_aclr_a = "NONE",\r
+ altsyncram_component.outdata_aclr_a = "NONE",\r
+ altsyncram_component.width_byteena_a = 1,\r
+ altsyncram_component.ram_block_type = "AUTO",\r
+ altsyncram_component.use_eab = "ON",\r
+ altsyncram_component.lpm_type = "altsyncram";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: WidthData NUMERIC "5"\r
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: SingleClock NUMERIC "0"\r
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegData NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrData NUMERIC "0"\r
+// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clken NUMERIC "0"\r
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
+// Retrieval info: PRIVATE: MIFfilename STRING ""\r
+// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
+// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "5"\r
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"\r
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"\r
+// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]\r
+// Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]\r
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock\r
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock\r
+// Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]\r
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren\r
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0\r
+// Retrieval info: CONNECT: q 0 0 5 0 @q_a 0 0 5 0\r
+// Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0\r
+// Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0\r
+// Retrieval info: CONNECT: @data_a 0 0 5 0 data 0 0 5 0\r
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
--- /dev/null
+// megafunction wizard: %RAM: 1-PORT%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: altsyncram \r
+\r
+// ============================================================\r
+// File Name: alt_ram_256_8.v\r
+// Megafunction Name(s):\r
+// altsyncram\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2003 Altera Corporation\r
+//Any megafunction design, and related netlist (encrypted or decrypted),\r
+//support information, device programming or simulation file, and any other\r
+//associated documentation or information provided by Altera or a partner\r
+//under Altera's Megafunction Partnership Program may be used only\r
+//to program PLD devices (but not masked PLD devices) from Altera. Any\r
+//other use of such megafunction design, netlist, support information,\r
+//device programming or simulation file, or any other related documentation\r
+//or information is prohibited for any other purpose, including, but not\r
+//limited to modification, reverse engineering, de-compiling, or use with\r
+//any other silicon devices, unless such use is explicitly licensed under\r
+//a separate agreement with Altera or a megafunction partner. Title to the\r
+//intellectual property, including patents, copyrights, trademarks, trade\r
+//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+//support information, device programming or simulation file, or any other\r
+//related documentation or information provided by Altera or a megafunction\r
+//partner, remains with Altera, the megafunction partner, or their respective\r
+//licensors. No other licenses, including any licenses needed under any third\r
+//party's intellectual property, are provided herein.\r
+\r
+\r
+module alt_ram_256_8 (\r
+ address,\r
+ clock,\r
+ data,\r
+ wren,\r
+ q);\r
+\r
+ input [7:0] address;\r
+ input clock;\r
+ input [7:0] data;\r
+ input wren;\r
+ output [7:0] q;\r
+\r
+ wire [7:0] sub_wire0;\r
+ wire [7:0] q = sub_wire0[7:0];\r
+\r
+ altsyncram altsyncram_component (\r
+ .wren_a (wren),\r
+ .clock0 (clock),\r
+ .address_a (address),\r
+ .data_a (data),\r
+ .q_a (sub_wire0));\r
+ defparam\r
+ altsyncram_component.intended_device_family = "Cyclone",\r
+ altsyncram_component.width_a = 8,\r
+ altsyncram_component.widthad_a = 8,\r
+ altsyncram_component.numwords_a = 256,\r
+ altsyncram_component.operation_mode = "SINGLE_PORT",\r
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
+ altsyncram_component.indata_aclr_a = "NONE",\r
+ altsyncram_component.wrcontrol_aclr_a = "NONE",\r
+ altsyncram_component.address_aclr_a = "NONE",\r
+ altsyncram_component.outdata_aclr_a = "NONE",\r
+ altsyncram_component.width_byteena_a = 1,\r
+ altsyncram_component.ram_block_type = "AUTO",\r
+ altsyncram_component.lpm_type = "altsyncram";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"\r
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"\r
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegData NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegOutput NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrData NUMERIC "0"\r
+// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clken NUMERIC "0"\r
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
+// Retrieval info: PRIVATE: MIFfilename STRING ""\r
+// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
+// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"\r
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
+// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]\r
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]\r
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren\r
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0\r
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0\r
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0\r
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
--- /dev/null
+// megafunction wizard: %RAM: 2-PORT%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: altsyncram \r
+\r
+// ============================================================\r
+// File Name: alt_ram_256_8_8.v\r
+// Megafunction Name(s):\r
+// altsyncram\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2004 Altera Corporation\r
+//Any megafunction design, and related netlist (encrypted or decrypted),\r
+//support information, device programming or simulation file, and any other\r
+//associated documentation or information provided by Altera or a partner\r
+//under Altera's Megafunction Partnership Program may be used only\r
+//to program PLD devices (but not masked PLD devices) from Altera. Any\r
+//other use of such megafunction design, netlist, support information,\r
+//device programming or simulation file, or any other related documentation\r
+//or information is prohibited for any other purpose, including, but not\r
+//limited to modification, reverse engineering, de-compiling, or use with\r
+//any other silicon devices, unless such use is explicitly licensed under\r
+//a separate agreement with Altera or a megafunction partner. Title to the\r
+//intellectual property, including patents, copyrights, trademarks, trade\r
+//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+//support information, device programming or simulation file, or any other\r
+//related documentation or information provided by Altera or a megafunction\r
+//partner, remains with Altera, the megafunction partner, or their respective\r
+//licensors. No other licenses, including any licenses needed under any third\r
+//party's intellectual property, are provided herein.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module alt_ram_256_8_8 (\r
+ data_a,\r
+ wren_a,\r
+ address_a,\r
+ data_b,\r
+ address_b,\r
+ wren_b,\r
+ clock_a,\r
+ enable_a,\r
+ clock_b,\r
+ enable_b,\r
+ q_a,\r
+ q_b);\r
+\r
+ input [7:0] data_a;\r
+ input wren_a;\r
+ input [7:0] address_a;\r
+ input [7:0] data_b;\r
+ input [7:0] address_b;\r
+ input wren_b;\r
+ input clock_a;\r
+ input enable_a;\r
+ input clock_b;\r
+ input enable_b;\r
+ output [7:0] q_a;\r
+ output [7:0] q_b;\r
+\r
+ wire [7:0] sub_wire0;\r
+ wire [7:0] sub_wire1;\r
+ wire [7:0] q_a = sub_wire0[7:0];\r
+ wire [7:0] q_b = sub_wire1[7:0];\r
+\r
+ altsyncram altsyncram_component (\r
+ .clocken0 (enable_a),\r
+ .clocken1 (enable_b),\r
+ .wren_a (wren_a),\r
+ .clock0 (clock_a),\r
+ .wren_b (wren_b),\r
+ .clock1 (clock_b),\r
+ .address_a (address_a),\r
+ .address_b (address_b),\r
+ .data_a (data_a),\r
+ .data_b (data_b),\r
+ .q_a (sub_wire0),\r
+ .q_b (sub_wire1)\r
+ // synopsys translate_off\r
+,\r
+ .rden_b (),\r
+ .aclr0 (),\r
+ .aclr1 (),\r
+ .byteena_a (),\r
+ .byteena_b (),\r
+ .addressstall_a (),\r
+ .addressstall_b ()\r
+ // synopsys translate_on\r
+\r
+);\r
+ defparam\r
+ altsyncram_component.intended_device_family = "Cyclone",\r
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",\r
+ altsyncram_component.width_a = 8,\r
+ altsyncram_component.widthad_a = 8,\r
+ altsyncram_component.numwords_a = 256,\r
+ altsyncram_component.width_b = 8,\r
+ altsyncram_component.widthad_b = 8,\r
+ altsyncram_component.numwords_b = 256,\r
+ altsyncram_component.lpm_type = "altsyncram",\r
+ altsyncram_component.width_byteena_a = 1,\r
+ altsyncram_component.width_byteena_b = 1,\r
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
+ altsyncram_component.outdata_aclr_a = "NONE",\r
+ altsyncram_component.outdata_reg_b = "UNREGISTERED",\r
+ altsyncram_component.indata_aclr_a = "NONE",\r
+ altsyncram_component.wrcontrol_aclr_a = "NONE",\r
+ altsyncram_component.address_aclr_a = "NONE",\r
+ altsyncram_component.indata_reg_b = "CLOCK1",\r
+ altsyncram_component.address_reg_b = "CLOCK1",\r
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",\r
+ altsyncram_component.indata_aclr_b = "NONE",\r
+ altsyncram_component.wrcontrol_aclr_b = "NONE",\r
+ altsyncram_component.address_aclr_b = "NONE",\r
+ altsyncram_component.outdata_aclr_b = "NONE",\r
+ altsyncram_component.ram_block_type = "AUTO";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"\r
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"\r
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"\r
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"\r
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"\r
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"\r
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"\r
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"\r
+// Retrieval info: PRIVATE: Clock NUMERIC "5"\r
+// Retrieval info: PRIVATE: rden NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"\r
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"\r
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"\r
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"\r
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"\r
+// Retrieval info: PRIVATE: REGq NUMERIC "0"\r
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"\r
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"\r
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: enable NUMERIC "1"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"\r
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"\r
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"\r
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
+// Retrieval info: PRIVATE: MIFfilename STRING ""\r
+// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "wren_a;wren_b;rden_b;data_a;data_b"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "address_a;address_b;clock0;clock1;clocken0"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "clocken1;aclr0;aclr1;byteena_a;byteena_b"\r
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "addressstall_a;addressstall_b;q_a;q_b"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"\r
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"\r
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"\r
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"\r
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"\r
+// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"\r
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"\r
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"\r
+// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"\r
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
+// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]\r
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a\r
+// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]\r
+// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]\r
+// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]\r
+// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]\r
+// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]\r
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b\r
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a\r
+// Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC enable_a\r
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b\r
+// Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC enable_b\r
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0\r
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0\r
+// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0\r
+// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0\r
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0\r
+// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0\r
+// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0\r
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0\r
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0\r
+// Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0\r
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0\r
+// Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8.v TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8.inc FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8.cmp FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8.bsf FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8_inst.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8_bb.v FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8_waveforms.html FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_256_8_8_wave*.jpg FALSE\r
--- /dev/null
+// megafunction wizard: %ROM: 1-PORT%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: altsyncram \r
+\r
+// ============================================================\r
+// File Name: alt_rom_6l.v\r
+// Megafunction Name(s):\r
+// altsyncram\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2003 Altera Corporation\r
+//Any megafunction design, and related netlist (encrypted or decrypted),\r
+//support information, device programming or simulation file, and any other\r
+//associated documentation or information provided by Altera or a partner\r
+//under Altera's Megafunction Partnership Program may be used only\r
+//to program PLD devices (but not masked PLD devices) from Altera. Any\r
+//other use of such megafunction design, netlist, support information,\r
+//device programming or simulation file, or any other related documentation\r
+//or information is prohibited for any other purpose, including, but not\r
+//limited to modification, reverse engineering, de-compiling, or use with\r
+//any other silicon devices, unless such use is explicitly licensed under\r
+//a separate agreement with Altera or a megafunction partner. Title to the\r
+//intellectual property, including patents, copyrights, trademarks, trade\r
+//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
+//support information, device programming or simulation file, or any other\r
+//related documentation or information provided by Altera or a megafunction\r
+//partner, remains with Altera, the megafunction partner, or their respective\r
+//licensors. No other licenses, including any licenses needed under any third\r
+//party's intellectual property, are provided herein.\r
+\r
+\r
+module alt_rom_6l (\r
+ address,\r
+ clock,\r
+ q);\r
+\r
+ input [4:0] address;\r
+ input clock;\r
+ output [7:0] q;\r
+\r
+ wire [7:0] sub_wire0;\r
+ wire [7:0] q = sub_wire0[7:0];\r
+\r
+ altsyncram altsyncram_component (\r
+ .clock0 (clock),\r
+ .address_a (address),\r
+ .q_a (sub_wire0));\r
+ defparam\r
+ altsyncram_component.intended_device_family = "Cyclone",\r
+ altsyncram_component.width_a = 8,\r
+ altsyncram_component.widthad_a = 5,\r
+ altsyncram_component.numwords_a = 32,\r
+ altsyncram_component.operation_mode = "ROM",\r
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
+ altsyncram_component.address_aclr_a = "NONE",\r
+ altsyncram_component.outdata_aclr_a = "NONE",\r
+ altsyncram_component.width_byteena_a = 1,\r
+ altsyncram_component.init_file = "6l.hex",\r
+ altsyncram_component.lpm_type = "altsyncram";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"\r
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"\r
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"\r
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"\r
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"\r
+// Retrieval info: PRIVATE: RegOutput NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"\r
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"\r
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"\r
+// Retrieval info: PRIVATE: Clken NUMERIC "0"\r
+// Retrieval info: PRIVATE: MIFfilename STRING "6l.hex"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"\r
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"\r
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"\r
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
+// Retrieval info: CONSTANT: INIT_FILE STRING "6l.hex"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
+// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0]\r
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]\r
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
+// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0\r
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0\r
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
--- /dev/null
+//\r
+// XAPP154 based SigmaDeltaPCM Module\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk. \r
+//\r
+// See the xapp154.pdf on Xilinx application note.\r
+//\r
+//\r
+\r
+`timescale 100 ps / 10 ps\r
+`define MSBI 7 // Most significant Bit of DAC input\r
+//This is a Delta-Sigma Digital to Analog Converter\r
+\r
+module dac(DACout, DACin, Clk, Reset);\r
+output DACout; // This is the average output that feeds low pass filter\r
+reg DACout; // for optimum performance, ensure that this ff is in IOB\r
+input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)\r
+input Clk;\r
+input Reset;\r
+reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder\r
+reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder\r
+reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder\r
+reg [`MSBI+2:0] DeltaB; // B input of Delta adder\r
+\r
+always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);\r
+\r
+always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;\r
+\r
+always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;\r
+\r
+always @(posedge Clk or posedge Reset)\r
+begin\r
+ if(Reset)\r
+ begin\r
+ SigmaLatch <= #1 1'b1 << (`MSBI+1);\r
+ DACout <= #1 1'b0;\r
+ end\r
+ else\r
+ begin\r
+// SigmaLatch <== #1 SigmaAdder;\r
+ SigmaLatch <= #1 SigmaAdder;\r
+ DACout <= #1 SigmaLatch[`MSBI+2];\r
+ end\r
+end\r
+endmodule\r
+\r
--- /dev/null
+// Module dcm
+// Generated by Xilinx Architecture Wizard
+// Written for synthesis tool: XST
+// Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
+// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
+`timescale 1ns / 1ps
+
+module dcm(CLKIN_IN,
+ RST_IN,
+ CLKFX_OUT,
+ CLKIN_IBUFG_OUT,
+ CLK0_OUT,
+ LOCKED_OUT);
+
+ input CLKIN_IN;
+ input RST_IN;
+ output CLKFX_OUT;
+ output CLKIN_IBUFG_OUT;
+ output CLK0_OUT;
+ output LOCKED_OUT;
+
+ wire CLKFB_IN;
+ wire CLKFX_BUF;
+ wire CLKIN_IBUFG;
+ wire CLK0_BUF;
+ wire GND_BIT;
+
+ assign GND_BIT = 0;
+ assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
+ assign CLK0_OUT = CLKFB_IN;
+ BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
+ .O(CLKFX_OUT));
+ IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
+ .O(CLKIN_IBUFG));
+ BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
+ .O(CLKFB_IN));
+ DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
+ .CLKIN(CLKIN_IBUFG),
+ .DSSEN(GND_BIT),
+ .PSCLK(GND_BIT),
+ .PSEN(GND_BIT),
+ .PSINCDEC(GND_BIT),
+ .RST(RST_IN),
+ .CLKDV(),
+ .CLKFX(CLKFX_BUF),
+ .CLKFX180(),
+ .CLK0(CLK0_BUF),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
+ defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_SP_INST.CLKFX_DIVIDE = 27;
+ defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_SP_INST.CLKIN_PERIOD = 8.000;
+ defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
+ defparam DCM_SP_INST.PHASE_SHIFT = 0;
+ defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
+endmodule
--- /dev/null
+//-------------------------------------------------------------------\r
+// \r
+// PLAYSTATION CONTROLLER-FPGA ARCADE GAME INTERFACE TOP \r
+// \r
+// Version : 2.01 \r
+// \r
+// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved \r
+// \r
+// Important ! \r
+// \r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program. \r
+// You can use this under your own risk. \r
+//\r
+// 2004-4-29 fpga mooncrst use k .degawa \r
+//-------------------------------------------------------------------\r
+\r
+`timescale 100ps/10ps\r
+`include "src/mc_conf.v"\r
+\r
+module fpga_arcade_if(\r
+\r
+CLK_18M432,\r
+I_RSTn,\r
+psCLK,\r
+psSEL,\r
+psTXD,\r
+psRXD,\r
+ps_PSW,\r
+I_VIB_SW\r
+\r
+);\r
+\r
+input CLK_18M432,I_RSTn;\r
+input I_VIB_SW;\r
+input psRXD;\r
+output psCLK,psSEL,psTXD;\r
+output [8:0]ps_PSW;\r
+\r
+reg [5:0]clk_reg;\r
+wire CLK_288K;\r
+\r
+assign CLK_288K = clk_reg[5];\r
+always@(posedge CLK_18M432) clk_reg <= clk_reg+1;\r
+\r
+wire [7:0]RX_DATA_1,RX_DATA_2;\r
+wire [7:0]RX_DATA_3,RX_DATA_4;\r
+//wire [7:0]RX_DATA_5,RX_DATA_6;\r
+\r
+reg [1:0]XY_pos;\r
+\r
+assign ps_PSW[0] = 1'b1; // UP\r
+assign ps_PSW[1] = 1'b1; // DOWN\r
+assign ps_PSW[2] = XY_pos[0]; // LEFT\r
+assign ps_PSW[3] = XY_pos[1]; // RIGHT\r
+assign ps_PSW[4] = RX_DATA_2[5]; // CREDIT1 (MARU-BOTAN) \r
+assign ps_PSW[5] = RX_DATA_2[4]; // CREDIT2 (SANKAKU-BOTAN)\r
+assign ps_PSW[6] = RX_DATA_1[3]; // START 1P (START-BOTAN)\r
+assign ps_PSW[7] = RX_DATA_1[0]; // START 2P (SELCT-BOTAN)\r
+assign ps_PSW[8] = RX_DATA_1[6];\r
+\r
+always@(posedge CLK_288K)\r
+begin\r
+ if(RX_DATA_3<=8'h5F&&RX_DATA_3>=8'h00)\r
+ XY_pos <= 2'b10;\r
+ else if(RX_DATA_3<=8'hFF&&RX_DATA_3>=8'hA0)\r
+ XY_pos <= 2'b01;\r
+ else\r
+ XY_pos <= 2'b11; \r
+end\r
+\r
+// Dualshock\r
+`ifdef Dualshock\r
+psPAD_top pspad(\r
+\r
+.I_CLK250K(CLK_288K),\r
+.I_RSTn(I_RSTn),\r
+.I_VIB_SW({I_VIB_SW,1'b0}),\r
+.O_psCLK(psCLK),\r
+.O_psSEL(psSEL),\r
+.O_psTXD(psTXD),\r
+.I_psRXD(psRXD),\r
+.O_RXD_1(RX_DATA_1),\r
+.O_RXD_2(RX_DATA_2),\r
+.O_RXD_3(RX_DATA_3),\r
+.O_RXD_4(RX_DATA_4),\r
+.O_RXD_5(),\r
+.O_RXD_6(),\r
+.I_CONF_SW(),\r
+.I_MODE_SW(),\r
+.I_MODE_EN(),\r
+.I_VIB_DAT(8'hFF)\r
+);\r
+`else\r
+psPAD_top pspad(\r
+\r
+.I_CLK250K(CLK_288K),\r
+.I_RSTn(I_RSTn),\r
+.I_VIB_SW(I_VIB_SW),\r
+.O_psCLK(psCLK),\r
+.O_psSEL(psSEL),\r
+.O_psTXD(psTXD),\r
+.I_psRXD(psRXD),\r
+.O_RXD_1(RX_DATA_1),\r
+.O_RXD_2(RX_DATA_2),\r
+.O_RXD_3(RX_DATA_3),\r
+.O_RXD_4(RX_DATA_4),\r
+.O_RXD_5(),\r
+.O_RXD_6(),\r
+.I_CONF_SW(),\r
+.I_MODE_SW(),\r
+.I_MODE_EN(),\r
+.I_VIB_DAT()\r
+);\r
+`endif\r
+\r
+endmodule\r
+\r
+\r
+\r
+\r
--- /dev/null
+//-------------------------------------------------------------------\r
+// \r
+// PLAYSTATION CONTROLLER-FPGA ARCADE GAME INTERFACE TOP \r
+// \r
+// Version : 2.02 \r
+// \r
+// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved \r
+// \r
+// Important ! \r
+// \r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program. \r
+// You can use this under your own risk. \r
+//\r
+// Xilinx Net I/F \r
+//-------------------------------------------------------------------\r
+\r
+module fpga_arcade_if(\r
+\r
+CLK_18M432,\r
+I_RSTn,\r
+psCLK,\r
+psSEL,\r
+psTXD,\r
+psRXD,\r
+ps_PSW,\r
+I_VIB_SW \r
+\r
+);\r
+\r
+input CLK_18M432,I_RSTn;\r
+input I_VIB_SW;\r
+input psRXD;\r
+output psCLK,psSEL,psTXD;\r
+output [8:0]ps_PSW;\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//---------------------------------------------------------------------\r
+// FPGA GALAXIAN ADDRESS DECDER\r
+//\r
+// Version : 2.01\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 4-30 galaxian modify by K.DEGAWA\r
+// 2004- 5- 6 first release.\r
+// 2004- 8-23 Improvement with T80-IP. \r
+//---------------------------------------------------------------------\r
+//\r
+//GALAXIAN Address Map\r
+//\r
+// Address Item(R..read-mode W..wight-mode) Parts \r
+//0000 - 1FFF CPU-ROM..R ( 7H or 7K ) \r
+//2000 - 3FFF CPU-ROM..R ( 7L )\r
+//4000 - 47FF CPU-RAM..RW ( 7N & 7P ) \r
+//5000 - 57FF VID-RAM..RW \r
+//5800 - 5FFF OBJ-RAM..RW\r
+//6000 - SW0..R LAMP......W\r
+//6800 - SW1..R SOUND.....W\r
+//7000 - DIP..R \r
+//7001 NMI_ON....W\r
+//7004 STARS_ON..W\r
+//7006 H_FLIP....W\r
+//7007 V-FLIP....W\r
+//7800 WDR..R PITCH.....W\r
+//\r
+//W MODE\r
+//6000 - 6002 \r
+//6003 COIN CNTR \r
+//6004 - 6007 SOUND CONTROL(OSC)\r
+//\r
+//6800 SOUND CONTROL(FS1)\r
+//6801 SOUND CONTROL(FS2)\r
+//6802 SOUND CONTROL(FS3)\r
+//6803 SOUND CONTROL(HIT)\r
+//6805 SOUND CONTROL(SHOT)\r
+//6806 SOUND CONTROL(VOL1)\r
+//6807 SOUND CONTROL(VOL2)\r
+//\r
+\r
+module mc_adec(\r
+\r
+I_CLK_12M,\r
+I_CLK_6M,\r
+I_CPU_CLK,\r
+I_RSTn,\r
+\r
+I_CPU_A,\r
+I_CPU_D,\r
+I_MREQn,\r
+I_RFSHn,\r
+I_RDn,\r
+I_WRn,\r
+I_H_BL,\r
+I_V_BLn,\r
+\r
+O_WAITn,\r
+O_NMIn,\r
+O_CPU_ROM_CSn,\r
+O_CPU_RAM_RDn,\r
+O_CPU_RAM_WRn,\r
+O_CPU_RAM_CSn,\r
+O_OBJ_RAM_RDn,\r
+O_OBJ_RAM_WRn,\r
+O_OBJ_RAM_RQn,\r
+O_VID_RAM_RDn,\r
+O_VID_RAM_WRn,\r
+O_SW0_OEn,\r
+O_SW1_OEn,\r
+O_DIP_OEn,\r
+O_WDR_OEn,\r
+O_LAMP_WEn,\r
+O_SOUND_WEn,\r
+O_PITCHn,\r
+O_H_FLIP,\r
+O_V_FLIP,\r
+O_BD_G,\r
+O_STARS_ON\r
+\r
+);\r
+\r
+\r
+input I_CLK_12M;\r
+input I_CLK_6M;\r
+input I_CPU_CLK;\r
+input I_RSTn;\r
+\r
+input [15:0]I_CPU_A;\r
+input I_CPU_D;\r
+input I_MREQn;\r
+input I_RFSHn;\r
+input I_RDn;\r
+input I_WRn;\r
+input I_H_BL;\r
+input I_V_BLn;\r
+\r
+output O_WAITn;\r
+output O_NMIn;\r
+output O_CPU_ROM_CSn;\r
+output O_CPU_RAM_RDn;\r
+output O_CPU_RAM_WRn;\r
+output O_CPU_RAM_CSn;\r
+output O_OBJ_RAM_RDn;\r
+output O_OBJ_RAM_WRn;\r
+output O_OBJ_RAM_RQn;\r
+output O_VID_RAM_RDn;\r
+output O_VID_RAM_WRn;\r
+output O_SW0_OEn;\r
+output O_SW1_OEn;\r
+output O_DIP_OEn;\r
+output O_WDR_OEn;\r
+output O_LAMP_WEn;\r
+output O_SOUND_WEn;\r
+output O_PITCHn;\r
+output O_H_FLIP;\r
+output O_V_FLIP;\r
+output O_BD_G;\r
+output O_STARS_ON;\r
+\r
+\r
+wire [3:0]W_8E1_Q;\r
+wire [3:0]W_8E2_Q;\r
+wire [7:0]W_8P_Q,W_8N_Q,W_8M_Q;\r
+reg [7:0]W_9N_Q;\r
+wire W_NMI_ONn = W_9N_Q[1]; // galaxian\r
+//------ CPU WAITn ---------------------------------------------- \r
+\r
+reg W_6S1_Q,W_6S1_Qn;\r
+reg W_6S2_Qn;\r
+\r
+//assign O_WAITn = W_6S1_Qn;\r
+assign O_WAITn = 1'b1 ; // No Wait\r
+\r
+always@(posedge I_CPU_CLK or negedge I_V_BLn)\r
+begin\r
+ if(I_V_BLn == 1'b0)begin\r
+ W_6S1_Q <= 1'b0;\r
+ W_6S1_Qn <= 1'b1;\r
+ end\r
+ else begin\r
+ W_6S1_Q <= ~(I_H_BL | W_8P_Q[2]);\r
+ W_6S1_Qn <= I_H_BL | W_8P_Q[2];\r
+ end\r
+end\r
+\r
+always@(negedge I_CPU_CLK)\r
+begin\r
+ W_6S2_Qn <= ~W_6S1_Q;\r
+end\r
+//------ CPU NMIn ----------------------------------------------- \r
+wire W_V_BL = ~I_V_BLn;\r
+reg O_NMIn;\r
+always@(posedge W_V_BL or negedge W_NMI_ONn)\r
+begin\r
+ if(~W_NMI_ONn)\r
+ O_NMIn <= 1'b1;\r
+ else\r
+ O_NMIn <= 1'b0;\r
+end\r
+//----------------------------------------------------------------- \r
+logic_74xx139 U_8E1(\r
+\r
+.I_G(I_MREQn),\r
+.I_Sel(I_CPU_A[15:14]),\r
+.O_Q(W_8E1_Q)\r
+\r
+);\r
+\r
+//-------- CPU_ROM CS 0000 - 3FFF --------------------------- \r
+logic_74xx139 U_8E2(\r
+\r
+.I_G(I_RDn),\r
+.I_Sel({W_8E1_Q[0],I_CPU_A[13]}),\r
+.O_Q(W_8E2_Q)\r
+\r
+);\r
+\r
+assign O_CPU_ROM_CSn = W_8E2_Q[0]&W_8E2_Q[1] ; // 0000 - 3FFF\r
+//-----------------------------------------------------------------\r
+// ADDRESS\r
+// W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE \r
+// W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1\r
+// W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE \r
+// W_8E1_Q[3] = C000 - FFFF\r
+\r
+logic_74xx138 U_8P(\r
+\r
+.I_G1(I_RFSHn),\r
+.I_G2a(W_8E1_Q[1]), // <= *1\r
+.I_G2b(W_8E1_Q[1]), // <= *1\r
+.I_Sel(I_CPU_A[13:11]),\r
+.O_Q(W_8P_Q)\r
+\r
+);\r
+\r
+logic_74xx138 U_8N(\r
+\r
+.I_G1(1'b1),\r
+.I_G2a(I_RDn),\r
+.I_G2b(W_8E1_Q[1]), // <= *1\r
+.I_Sel(I_CPU_A[13:11]),\r
+.O_Q(W_8N_Q)\r
+\r
+);\r
+\r
+logic_74xx138 U_8M(\r
+\r
+//.I_G1(W_6S2_Qn),\r
+.I_G1(1'b1), // No Wait\r
+.I_G2a(I_WRn),\r
+.I_G2b(W_8E1_Q[1]), // <= *1\r
+.I_Sel(I_CPU_A[13:11]),\r
+.O_Q(W_8M_Q)\r
+\r
+);\r
+\r
+assign O_BD_G = ~(W_8E1_Q[0]&W_8P_Q[0]); //\r
+assign O_OBJ_RAM_RQn = W_8P_Q[3]; //\r
+\r
+assign O_CPU_RAM_CSn = W_8N_Q[0]&W_8M_Q[0]; //\r
+assign O_CPU_RAM_RDn = W_8N_Q[0]; //\r
+assign O_CPU_RAM_WRn = W_8M_Q[0]; //\r
+assign O_VID_RAM_RDn = W_8N_Q[2]; //\r
+assign O_OBJ_RAM_RDn = W_8N_Q[3]; //\r
+assign O_SW0_OEn = W_8N_Q[4]; // \r
+assign O_SW1_OEn = W_8N_Q[5]; // \r
+assign O_DIP_OEn = W_8N_Q[6]; // \r
+assign O_WDR_OEn = W_8N_Q[7]; // \r
+\r
+assign O_VID_RAM_WRn = W_8M_Q[2]; // \r
+assign O_OBJ_RAM_WRn = W_8M_Q[3]; // \r
+assign O_LAMP_WEn = W_8M_Q[4]; // \r
+assign O_SOUND_WEn = W_8M_Q[5]; // \r
+\r
+assign O_PITCHn = W_8M_Q[7]; // \r
+\r
+//--- Parts 9N ---------\r
+\r
+always@(posedge I_CLK_12M or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)begin\r
+ W_9N_Q <= 0;\r
+ end \r
+ else begin\r
+ if(W_8M_Q[6] == 1'b0)begin\r
+ case(I_CPU_A[2:0])\r
+ 3'h0 : W_9N_Q[0] <= I_CPU_D;\r
+ 3'h1 : W_9N_Q[1] <= I_CPU_D;\r
+ 3'h2 : W_9N_Q[2] <= I_CPU_D;\r
+ 3'h3 : W_9N_Q[3] <= I_CPU_D;\r
+ 3'h4 : W_9N_Q[4] <= I_CPU_D;\r
+ 3'h5 : W_9N_Q[5] <= I_CPU_D;\r
+ 3'h6 : W_9N_Q[6] <= I_CPU_D;\r
+ 3'h7 : W_9N_Q[7] <= I_CPU_D;\r
+ endcase\r
+ end\r
+ end\r
+end\r
+\r
+assign O_STARS_ON = W_9N_Q[4]; // \r
+assign O_H_FLIP = W_9N_Q[6]; // \r
+assign O_V_FLIP = W_9N_Q[7]; // \r
+\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA & GALAXIAN \r
+// FPGA BLOCK RAM I/F (ALTERA-CYCLONE & XILINX SPARTAN2E)\r
+//\r
+// Version : 2.50\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// mc_col_rom(6L) added by k.Degawa\r
+//\r
+// 2004- 5- 6 first release.\r
+// 2004- 8-23 Improvement with T80-IP. K.Degawa\r
+// 2004- 9-18 added Xilinx Device K.Degawa\r
+//================================================================================\r
+`include "src/mc_conf.v"\r
+\r
+// mc_top.v use\r
+module mc_cpu_ram (\r
+\r
+I_CLK,\r
+I_ADDR,\r
+I_D,\r
+I_WE,\r
+I_OE,\r
+O_D\r
+\r
+);\r
+\r
+input I_CLK;\r
+input [9:0]I_ADDR;\r
+input [7:0]I_D;\r
+input I_WE;\r
+input I_OE;\r
+output [7:0]O_D;\r
+\r
+wire [7:0]W_D;\r
+assign O_D = I_OE ? W_D : 8'h00 ;\r
+\r
+`ifdef DEVICE_CYCLONE\r
+alt_ram_1024_8 CPURAM_ALT(\r
+\r
+.clock(I_CLK),\r
+.address(I_ADDR),\r
+.data(I_D),\r
+.wren(I_WE),\r
+.q(W_D)\r
+\r
+);\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E \r
+RAMB4_S4 CPURAM_X1(\r
+\r
+.CLK(I_CLK),\r
+.ADDR(I_ADDR[9:0]),\r
+.DI(I_D[7:4]),\r
+.DO(W_D[7:4]),\r
+.EN(1'b1),\r
+.WE(I_WE),\r
+.RST(1'b0)\r
+\r
+);\r
+\r
+RAMB4_S4 CPURAM_X0(\r
+\r
+.CLK(I_CLK),\r
+.ADDR(I_ADDR[9:0]),\r
+.DI(I_D[3:0]),\r
+.DO(W_D[3:0]),\r
+.EN(1'b1),\r
+.WE(I_WE),\r
+.RST(1'b0)\r
+\r
+);\r
+`endif\r
+\r
+endmodule\r
+\r
+// mc_video.v use\r
+module mc_obj_ram(\r
+\r
+I_CLKA,\r
+I_ADDRA,\r
+I_WEA,\r
+I_CEA,\r
+I_DA,\r
+O_DA,\r
+\r
+I_CLKB,\r
+I_ADDRB,\r
+I_WEB,\r
+I_CEB,\r
+I_DB,\r
+O_DB\r
+\r
+);\r
+\r
+input I_CLKA,I_CLKB;\r
+input [7:0]I_ADDRA,I_ADDRB;\r
+input I_WEA,I_WEB;\r
+input I_CEA,I_CEB;\r
+input [7:0]I_DA,I_DB;\r
+output [7:0]O_DA,O_DB;\r
+\r
+`ifdef DEVICE_CYCLONE\r
+alt_ram_256_8_8 OBJRAM(\r
+\r
+.clock_a(I_CLKA),\r
+.address_a(I_ADDRA),\r
+.wren_a(I_WEA),\r
+.enable_a(I_CEA),\r
+.data_a(I_DA),\r
+.q_a(O_DA),\r
+\r
+.clock_b(I_CLKB),\r
+.address_b(I_ADDRB),\r
+.wren_b(I_WEB),\r
+.enable_b(I_CEB),\r
+.data_b(I_DB),\r
+.q_b(O_DB)\r
+\r
+);\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E \r
+RAMB4_S8_S8 OBJRAM(\r
+\r
+.CLKA(I_CLKA),\r
+.ADDRA({1'b0,I_ADDRA[7:0]}),\r
+.DIA(I_DA),\r
+.DOA(O_DA),\r
+.ENA(I_CEA),\r
+.WEA(I_WEA),\r
+.RSTA(1'b0),\r
+\r
+.CLKB(I_CLKB),\r
+.ADDRB({1'b0,I_ADDRB[7:0]}),\r
+.DIB(I_DB),\r
+.DOB(O_DB),\r
+.ENB(I_CEB),\r
+.WEB(I_WEB),\r
+.RSTB(1'b0)\r
+);\r
+`endif\r
+\r
+endmodule\r
+\r
+\r
+// mc_video.v use\r
+module mc_vid_ram (\r
+\r
+I_CLKA,\r
+I_ADDRA,\r
+I_DA,\r
+I_WEA,\r
+I_CEA,\r
+O_DA,\r
+\r
+I_CLKB,\r
+I_ADDRB,\r
+I_DB,\r
+I_WEB,\r
+I_CEB,\r
+O_DB\r
+\r
+);\r
+\r
+input I_CLKA,I_CLKB;\r
+input [9:0]I_ADDRA,I_ADDRB;\r
+input [7:0]I_DA,I_DB;\r
+input I_WEA,I_WEB;\r
+input I_CEA,I_CEB;\r
+output [7:0]O_DA,O_DB;\r
+\r
+`ifdef DEVICE_CYCLONE\r
+alt_ram_1024_8_8 VIDRAM(\r
+\r
+.clock_a(I_CLKA),\r
+.address_a(I_ADDRA),\r
+.data_a(I_DA),\r
+.wren_a(I_WEA),\r
+.enable_a(I_CEA),\r
+.q_a(O_DA),\r
+\r
+.clock_b(I_CLKB),\r
+.address_b(I_ADDRB),\r
+.data_b(I_DB),\r
+.wren_b(I_WEB),\r
+.enable_b(I_CEB),\r
+.q_b(O_DB)\r
+\r
+);\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E \r
+RAMB4_S4_S4 VIDRAM_X1(\r
+\r
+.CLKA(I_CLKA),\r
+.ADDRA(I_ADDRA[9:0]),\r
+.DIA(I_DA[7:4]),\r
+.DOA(O_DA[7:4]),\r
+.ENA(I_CEA),\r
+.WEA(I_WEA),\r
+.RSTA(1'b0),\r
+\r
+.CLKB(I_CLKB),\r
+.ADDRB(I_ADDRB[9:0]),\r
+.DIB(I_DB[7:4]),\r
+.DOB(O_DB[7:4]),\r
+.ENB(I_CEB),\r
+.WEB(I_WEB),\r
+.RSTB(1'b0)\r
+\r
+);\r
+\r
+RAMB4_S4_S4 VIDRAM_X0(\r
+\r
+.CLKA(I_CLKA),\r
+.ADDRA(I_ADDRA[9:0]),\r
+.DIA(I_DA[3:0]),\r
+.DOA(O_DA[3:0]),\r
+.ENA(I_CEA),\r
+.WEA(I_WEA),\r
+.RSTA(1'b0),\r
+\r
+.CLKB(I_CLKB),\r
+.ADDRB(I_ADDRB[9:0]),\r
+.DIB(I_DB[3:0]),\r
+.DOB(O_DB[3:0]),\r
+.ENB(I_CEB),\r
+.WEB(I_WEB),\r
+.RSTB(1'b0)\r
+\r
+);\r
+`endif\r
+\r
+endmodule\r
+\r
+// mc_video.v use\r
+module mc_lram(\r
+\r
+I_CLK,\r
+I_ADDR,\r
+I_WE,\r
+I_D,\r
+O_Dn\r
+\r
+);\r
+\r
+input I_CLK;\r
+input [7:0]I_ADDR;\r
+input [4:0]I_D;\r
+input I_WE;\r
+output [4:0]O_Dn;\r
+wire [4:0]W_D;\r
+\r
+`ifdef DEVICE_CYCLONE\r
+assign O_Dn = ~W_D;\r
+\r
+alt_ram_256_5 LRAM(\r
+\r
+.inclock(I_CLK),\r
+.outclock(~I_CLK),\r
+.address(I_ADDR),\r
+.data(I_D),\r
+.wren(I_WE),\r
+.q(W_D)\r
+\r
+);\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E\r
+reg [4:0]O_Dn;\r
+always@(negedge I_CLK) O_Dn <= ~W_D[4:0] ;\r
+\r
+RAMB4_S8 LRAM(\r
+\r
+.CLK(I_CLK),\r
+.ADDR({1'b0,I_ADDR[7:0]}),\r
+.DI({3'b000,I_D}),\r
+.DO(W_D),\r
+.EN(1'b1),\r
+.WE(I_WE),\r
+.RST(1'b0)\r
+\r
+);\r
+`endif\r
+\r
+endmodule\r
+\r
+// mc_col_pal.v use\r
+`ifdef DEVICE_CYCLONE\r
+module mc_col_rom(\r
+\r
+I_CLK,\r
+I_ADDR,\r
+I_OEn,\r
+O_DO\r
+\r
+);\r
+\r
+input I_CLK;\r
+input [4:0]I_ADDR;\r
+input I_OEn;\r
+output [7:0]O_DO;\r
+wire [7:0]W_DO;\r
+\r
+assign O_DO = I_OEn ? 8'h00 : W_DO ;\r
+alt_rom_6l U_6L(\r
+\r
+.clock(I_CLK),\r
+.address(I_ADDR),\r
+.q(W_DO)\r
+\r
+);\r
+\r
+\r
+endmodule\r
+`endif\r
--- /dev/null
+//---------------------------------------------------------------------\r
+// FPGA MOONCRESTA CLOCK GEN \r
+//\r
+// Version : 1.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+//---------------------------------------------------------------------\r
+\r
+\r
+\r
+module mc_clock(\r
+\r
+I_CLK_18M,\r
+O_CLK_12M,\r
+O_CLK_06M,\r
+O_CLK_06Mn\r
+\r
+);\r
+\r
+input I_CLK_18M;\r
+output O_CLK_12M;\r
+output O_CLK_06M;\r
+output O_CLK_06Mn;\r
+\r
+// 2/3 clock divider(duty 33%)\r
+reg [1:0] clk_ff1,clk_ff2;\r
+//I_CLK 1010101010101010101\r
+//c_ff10 0011110011110011110\r
+//c_ff11 0011000011000011000\r
+//c_ff20 0000110000110000110\r
+//c_ff21 0110000110000110000\r
+//O_12M 0000110110110110110\r
+always @(posedge I_CLK_18M)\r
+begin\r
+ clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1];\r
+ clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
+ clk_ff2[0] <= clk_ff1[0] & clk_ff1[1];\r
+end\r
+always @(negedge I_CLK_18M)\r
+ clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
+\r
+// 2/3 clock (duty 66%)\r
+assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];\r
+ \r
+// 1/3 clock divider (duty 50%)\r
+reg CLK_6M , CLK_6Mn;\r
+always @(posedge O_CLK_12M)\r
+begin\r
+ CLK_6Mn <= CLK_6M;\r
+ CLK_6M <= ~CLK_6M;\r
+end\r
+assign O_CLK_06M = CLK_6M;\r
+assign O_CLK_06Mn = CLK_6Mn;\r
+\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA COLOR-PALETTE\r
+//\r
+// Version : 2.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 9-18 added Xilinx Device. K.Degawa\r
+//================================================================================\r
+`include "src/mc_conf.v"\r
+\r
+module mc_col_pal(\r
+\r
+I_CLK_12M,\r
+I_CLK_6M,\r
+I_VID,\r
+I_COL,\r
+I_C_BLnX,\r
+\r
+O_C_BLX,\r
+O_STARS_OFFn,\r
+O_R,\r
+O_G,\r
+O_B\r
+\r
+);\r
+\r
+input I_CLK_12M;\r
+input I_CLK_6M;\r
+input [1:0]I_VID;\r
+input [2:0]I_COL;\r
+input I_C_BLnX;\r
+\r
+output O_C_BLX;\r
+output O_STARS_OFFn;\r
+output [2:0]O_R;\r
+output [2:0]O_G;\r
+output [1:0]O_B;\r
+\r
+//--- Parts 6M --------------------------------------------------------\r
+wire [6:0]W_6M_DI = {I_COL[2:0],I_VID[1:0],~(I_VID[0]|I_VID[1]),I_C_BLnX};\r
+reg [6:0]W_6M_DO;\r
+\r
+wire W_6M_CLR = W_6M_DI[0]|W_6M_DO[0];\r
+assign O_C_BLX = ~(W_6M_DI[0]|W_6M_DO[0]);\r
+assign O_STARS_OFFn = W_6M_DO[1];\r
+\r
+always@(posedge I_CLK_6M or negedge W_6M_CLR)\r
+begin\r
+ if(W_6M_CLR==1'b0)\r
+ W_6M_DO <= 7'h00;\r
+ else\r
+ W_6M_DO <= W_6M_DI;\r
+end\r
+//--- COL ROM --------------------------------------------------------\r
+wire [4:0]W_COL_ROM_A = W_6M_DO[6:2];\r
+wire [7:0]W_COL_ROM_DO;\r
+wire W_COL_ROM_OEn = W_6M_DO[1];\r
+\r
+`ifdef DEVICE_CYCLONE\r
+mc_col_rom COL_ROM(\r
+\r
+.I_CLK(I_CLK_12M),\r
+.I_ADDR(W_COL_ROM_A),\r
+.O_DO(W_COL_ROM_DO),\r
+.I_OEn(W_COL_ROM_OEn)\r
+\r
+);\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E\r
+GALAXIAN_6L COL_ROM(\r
+.CLK(I_CLK_12M),\r
+.ADDR(W_COL_ROM_A),\r
+.DATA(W_COL_ROM_DO),\r
+.ENA(1'b1)\r
+);\r
+//RAMB4_S8 col_rom00(\r
+//\r
+//.CLK(I_CLK_12M),\r
+//.ADDR({4'b0000,W_COL_ROM_A[4:0]}),\r
+//.DI(8'h00),\r
+//.DO(W_COL_ROM_DO),\r
+//.EN(1'b1),\r
+//.WE(1'b0),\r
+//.RST(1'b0)\r
+//\r
+//);\r
+`endif\r
+//--- VID OUT --------------------------------------------------------\r
+assign O_R[0] = W_COL_ROM_DO[2];\r
+assign O_R[1] = W_COL_ROM_DO[1];\r
+assign O_R[2] = W_COL_ROM_DO[0];\r
+\r
+assign O_G[0] = W_COL_ROM_DO[5];\r
+assign O_G[1] = W_COL_ROM_DO[4];\r
+assign O_G[2] = W_COL_ROM_DO[3];\r
+\r
+assign O_B[0] = W_COL_ROM_DO[7];\r
+assign O_B[1] = W_COL_ROM_DO[6];\r
+\r
+\r
+endmodule\r
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA CONFIG FILE\r
+//\r
+// Version : 1.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+// \r
+//================================================================================\r
+//- Device selct ----------------------------------------------------------------\r
+// `define DEVICE_CYCLONE // ALTERA DEVICE\r
+`define DEVICE_SPARTAN2E // XILINX DEVICE\r
+//--------------------------------------------------------------------------------\r
+//- Video out Format ------------------------------------------------------------\r
+ `define VGA_USE\r
+\r
+//--------------------------------------------------------------------------------\r
+//- include the playstation control(DUALSHOCK) interface module -----------------\r
+//`define PSPAD_USE\r
+ `define Dualshock // default\r
+//--------------------------------------------------------------------------------\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+//---------------------------------------------------------------------\r
+// FPGA MOONCRESTA H & V COUNTER \r
+//\r
+// Version : 2.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 9-22 \r
+//---------------------------------------------------------------------\r
+// MoonCrest hv_count\r
+// H_CNT 0 - 255 , 384 - 511 Total 384 count\r
+// V_CNT 0 - 255 , 504 - 511 Total 264 count\r
+//-----------------------------------------------------------------------------------------\r
+// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8], \r
+// 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H\r
+//-----------------------------------------------------------------------------------------\r
+// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] \r
+// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V \r
+//-----------------------------------------------------------------------------------------\r
+\r
+module mc_hv_count(\r
+\r
+I_CLK, // 6MHz\r
+I_RSTn,\r
+\r
+O_H_CNT,\r
+O_H_SYNC,\r
+O_H_BL,\r
+O_V_CNT,\r
+O_V_SYNC,\r
+O_V_BLn,\r
+O_V_BL2n,\r
+O_C_BLn\r
+\r
+);\r
+\r
+input I_CLK,I_RSTn;\r
+output [8:0]O_H_CNT;\r
+output O_H_SYNC;\r
+output O_H_BL;\r
+output O_V_BL2n;\r
+output [7:0]O_V_CNT;\r
+output O_V_SYNC;\r
+output O_V_BLn;\r
+\r
+output O_C_BLn;\r
+\r
+//------- H_COUNT ---------------------------------------- \r
+reg [8:0]H_CNT;\r
+always@(posedge I_CLK)\r
+begin\r
+ H_CNT <= H_CNT==255 ? 384 : H_CNT +1 ;\r
+end\r
+assign O_H_CNT = H_CNT[8:0];\r
+\r
+//------- H_SYNC ----------------------------------------\r
+\r
+reg H_SYNCn;\r
+wire H_SYNC = ~H_SYNCn;\r
+always@(posedge H_CNT[4] or negedge H_CNT[8]) \r
+begin\r
+ if(H_CNT[8]==1'b0) H_SYNCn <= 1'b1;\r
+ else H_SYNCn <= ~(~H_CNT[6]& H_CNT[5]);\r
+end\r
+\r
+assign O_H_SYNC = H_SYNC;\r
+//------- H_BL ------------------------------------------\r
+\r
+reg H_BL;\r
+\r
+always@(posedge I_CLK)\r
+begin\r
+ case(H_CNT[8:0])\r
+ 387:H_BL<=1'b1;\r
+ 503:H_BL<=1'b0;\r
+ default:;\r
+ endcase\r
+end\r
+\r
+assign O_H_BL = H_BL;\r
+//------- V_COUNT ---------------------------------------- \r
+reg [8:0]V_CNT;\r
+always@(posedge H_SYNC or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn==1'b0)\r
+ V_CNT <= 0;\r
+ else\r
+ V_CNT <= V_CNT==255 ? 504 : V_CNT +1 ;\r
+end\r
+assign O_V_CNT = V_CNT[7:0];\r
+assign O_V_SYNC = V_CNT[8];\r
+\r
+//------- V_BLn ------------------------------------------\r
+\r
+reg V_BLn;\r
+always@(posedge H_SYNC)\r
+begin\r
+ case(V_CNT[7:0])\r
+ 239: V_BLn <= 0;\r
+ 15: V_BLn <= 1;\r
+ default:;\r
+ endcase\r
+end\r
+\r
+reg V_BL2n;\r
+always@(posedge H_SYNC)\r
+begin\r
+ case(V_CNT[7:0])\r
+ 239: V_BL2n <= 0;\r
+ 16: V_BL2n <= 1;\r
+ default:;\r
+ endcase\r
+end\r
+\r
+assign O_V_BLn = V_BLn;\r
+assign O_V_BL2n = V_BL2n;\r
+//------- C_BLn ------------------------------------------\r
+\r
+assign O_C_BLn = ~(~V_BLn | H_CNT[8]);\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//---------------------------------------------------------------------\r
+// FPGA MOONCRESTA INPORT \r
+//\r
+// Version : 1.01\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004-4-30 galaxian modify by K.DEGAWA\r
+//---------------------------------------------------------------------\r
+\r
+// DIP SW 0 1 2 3 4 5 \r
+//---------------------------------------------------------------\r
+// COIN CHUTE \r
+// 1 COIN/1 PLAY 1'b0 1'b0 \r
+// 2 COIN/1 PLAY 1'b1 1'b0 \r
+// 1 COIN/2 PLAY 1'b0 1'b1 \r
+// FREE PLAY 1'b1 1'b1 \r
+// BOUNS\r
+// 1'b0 1'b0 \r
+// 1'b1 1'b0 \r
+// 1'b0 1'b1 \r
+// 1'b1 1'b1\r
+// LIVES \r
+// 2 1'b0\r
+// 3 1'b1\r
+\r
+module mc_inport(\r
+\r
+I_COIN1, // ACTIVE HI\r
+I_COIN2, // ACTIVE HI\r
+I_1P_LE, // ACTIVE HI\r
+I_1P_RI, // ACTIVE HI\r
+I_1P_SH, // ACTIVE HI\r
+I_2P_LE,\r
+I_2P_RI,\r
+I_2P_SH,\r
+I_1P_START, // ACTIVE HI\r
+I_2P_START, // ACTIVE HI\r
+\r
+I_SW0_OEn,\r
+I_SW1_OEn,\r
+I_DIP_OEn,\r
+\r
+O_D\r
+\r
+);\r
+\r
+input I_COIN1;\r
+input I_COIN2;\r
+input I_1P_LE;\r
+input I_1P_RI;\r
+input I_1P_SH;\r
+input I_2P_LE;\r
+input I_2P_RI;\r
+input I_2P_SH;\r
+input I_1P_START;\r
+input I_2P_START;\r
+\r
+input I_SW0_OEn;\r
+input I_SW1_OEn;\r
+input I_DIP_OEn;\r
+\r
+output [7:0]O_D;\r
+\r
+wire W_TABLE = 0; // UP TYPE = 0;\r
+\r
+wire [5:0]W_DIP_D = {1'b0,1'b1,1'b0,1'b0,1'b0,1'b0};\r
+wire [7:0]W_SW0_DI = { 1'b0, 1'b0, W_TABLE, I_1P_SH, I_1P_RI, I_1P_LE, I_COIN2, I_COIN1};\r
+wire [7:0]W_SW1_DI = {W_DIP_D[1],W_DIP_D[0], 1'b0, I_2P_SH, I_2P_RI, I_2P_LE,I_2P_START,I_1P_START};\r
+wire [7:0]W_DIP_DI = { 1'b0, 1'b0, 1'b0, 1'b0,W_DIP_D[5],W_DIP_D[4],W_DIP_D[3],W_DIP_D[2]};\r
+\r
+wire [7:0]W_SW0_DO = I_SW0_OEn ? 8'h00 : W_SW0_DI;\r
+wire [7:0]W_SW1_DO = I_SW1_OEn ? 8'h00 : W_SW1_DI;\r
+wire [7:0]W_DIP_DO = I_DIP_OEn ? 8'h00 : W_DIP_DI;\r
+\r
+assign O_D = W_SW0_DO | W_SW1_DO | W_DIP_DO ;\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA VIDEO-LD_PLS_GEN\r
+//\r
+// Version : 2.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
+//================================================================================\r
+\r
+\r
+module mc_ld_pls(\r
+\r
+I_CLK_6M,\r
+I_H_CNT,\r
+I_3D_DI,\r
+\r
+O_LDn,\r
+O_CNTRLDn,\r
+O_CNTRCLRn,\r
+O_COLLn,\r
+O_VPLn,\r
+O_OBJDATALn,\r
+O_MLDn,\r
+O_SLDn\r
+\r
+);\r
+\r
+input I_CLK_6M;\r
+input [8:0]I_H_CNT;\r
+input I_3D_DI;\r
+\r
+output O_LDn;\r
+output O_CNTRLDn;\r
+output O_CNTRCLRn;\r
+output O_COLLn;\r
+output O_VPLn;\r
+output O_OBJDATALn;\r
+output O_MLDn;\r
+output O_SLDn;\r
+\r
+reg W_5C_Q;\r
+always@(posedge I_CLK_6M)\r
+ W_5C_Q <= I_H_CNT[0];\r
+\r
+// Parts 4D\r
+wire W_4D1_G = ~(I_H_CNT[0]&I_H_CNT[1]&I_H_CNT[2]);\r
+wire [3:0]W_4D1_Q;\r
+wire [3:0]W_4D2_Q;\r
+\r
+logic_74xx139 U_4D1(\r
+\r
+.I_G(W_4D1_G),\r
+.I_Sel({I_H_CNT[8],I_H_CNT[3]}),\r
+.O_Q(W_4D1_Q)\r
+\r
+);\r
+\r
+logic_74xx139 U_4D2(\r
+\r
+.I_G(W_5C_Q),\r
+.I_Sel(I_H_CNT[2:1]),\r
+.O_Q(W_4D2_Q)\r
+\r
+);\r
+\r
+// Parts 4C\r
+wire [3:0]W_4C1_Q;\r
+wire [3:0]W_4C2_Q;\r
+\r
+logic_74xx139 U_4C1(\r
+\r
+.I_G(W_4D2_Q[1]),\r
+.I_Sel({I_H_CNT[8],I_H_CNT[3]}),\r
+.O_Q(W_4C1_Q)\r
+\r
+);\r
+\r
+reg W_4C1_Q3;\r
+always@(negedge I_CLK_6M) // 2004-9-22 added\r
+ W_4C1_Q3 <= W_4C1_Q[3];\r
+\r
+reg W_4C2_B;\r
+always@(posedge W_4C1_Q3) \r
+ W_4C2_B <= I_3D_DI;\r
+\r
+logic_74xx139 U_4C2(\r
+\r
+.I_G(W_4D1_Q[3]),\r
+.I_Sel({W_4C2_B,~(I_H_CNT[6]&I_H_CNT[5]&I_H_CNT[4]&I_H_CNT[3])}),\r
+.O_Q(W_4C2_Q)\r
+\r
+);\r
+\r
+assign O_LDn = W_4D1_G;\r
+assign O_CNTRLDn = W_4D1_Q[2];\r
+assign O_CNTRCLRn = W_4D1_Q[0];\r
+assign O_COLLn = W_4D2_Q[2];\r
+assign O_VPLn = W_4D2_Q[0];\r
+assign O_OBJDATALn = W_4C1_Q[2];\r
+assign O_MLDn = W_4C2_Q[0];\r
+assign O_SLDn = W_4C2_Q[1];\r
+\r
+\r
+endmodule\r
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA LOGIC IP MODULE\r
+//\r
+// Version : 1.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+//================================================================================\r
+\r
+\r
+//================================================\r
+// 74xx138\r
+// 3-to-8 line decoder\r
+//================================================\r
+module logic_74xx138(\r
+\r
+I_G1,\r
+I_G2a,\r
+I_G2b,\r
+I_Sel,\r
+O_Q\r
+\r
+);\r
+\r
+input I_G1,I_G2a,I_G2b;\r
+input [2:0]I_Sel;\r
+output [7:0]O_Q;\r
+\r
+reg [7:0]O_Q;\r
+wire [2:0]I_G = {I_G1,I_G2a,I_G2b};\r
+always@(I_G or I_Sel or O_Q)\r
+begin\r
+ if(I_G == 3'b100 )begin\r
+ case(I_Sel)\r
+ 3'b000: O_Q = 8'b11111110;\r
+ 3'b001: O_Q = 8'b11111101;\r
+ 3'b010: O_Q = 8'b11111011;\r
+ 3'b011: O_Q = 8'b11110111;\r
+ 3'b100: O_Q = 8'b11101111;\r
+ 3'b101: O_Q = 8'b11011111;\r
+ 3'b110: O_Q = 8'b10111111;\r
+ 3'b111: O_Q = 8'b01111111;\r
+ endcase\r
+ end\r
+ else begin\r
+ O_Q = 8'b11111111;\r
+ end\r
+end\r
+\r
+endmodule\r
+\r
+//================================================\r
+// 74xx139\r
+// 2-to-4 line decoder\r
+//================================================\r
+module logic_74xx139(\r
+\r
+I_G,\r
+I_Sel,\r
+O_Q\r
+\r
+);\r
+\r
+input I_G;\r
+input [1:0]I_Sel;\r
+output [3:0]O_Q;\r
+\r
+reg [3:0]O_Q;\r
+always@(I_G or I_Sel or O_Q)\r
+begin\r
+ if(I_G == 1'b0 )begin\r
+ case(I_Sel)\r
+ 2'b00: O_Q = 4'b1110;\r
+ 2'b01: O_Q = 4'b1101;\r
+ 2'b10: O_Q = 4'b1011;\r
+ 2'b11: O_Q = 4'b0111;\r
+ endcase\r
+ end\r
+ else begin\r
+ O_Q = 4'b1111;\r
+ end\r
+end\r
+\r
+endmodule\r
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA VIDEO-MISSILE\r
+//\r
+// Version : 2.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
+//================================================================================\r
+\r
+\r
+module mc_missile(\r
+\r
+I_CLK_18M,\r
+I_CLK_6M,\r
+I_C_BLn_X,\r
+I_MLDn,\r
+I_SLDn,\r
+I_HPOS,\r
+\r
+O_MISSILEn,\r
+O_SHELLn\r
+\r
+);\r
+\r
+input I_CLK_6M,I_CLK_18M;\r
+input I_C_BLn_X;\r
+input I_MLDn;\r
+input I_SLDn;\r
+input [7:0]I_HPOS;\r
+\r
+output O_MISSILEn;\r
+output O_SHELLn;\r
+\r
+reg [7:0]W_45R_Q;\r
+\r
+always@(posedge I_CLK_6M)\r
+begin\r
+ if(I_MLDn==1'b0)\r
+ W_45R_Q <= I_HPOS;\r
+ else begin\r
+ if(I_C_BLn_X)\r
+ W_45R_Q <= W_45R_Q +1;\r
+ else\r
+ W_45R_Q <= W_45R_Q ;\r
+ end\r
+end\r
+\r
+reg W_5P1_Q;\r
+reg W_5P1_CLK; \r
+\r
+always@(posedge I_CLK_18M)\r
+ W_5P1_CLK <= ~((&W_45R_Q[7:2])&W_5P1_Q);\r
+\r
+always@(posedge W_5P1_CLK or negedge I_MLDn)\r
+begin\r
+ if(I_MLDn==1'b0)\r
+ W_5P1_Q <= 1'b1;\r
+ else\r
+ W_5P1_Q <= 1'b0;\r
+end\r
+\r
+assign O_MISSILEn = W_5P1_CLK;\r
+\r
+reg [7:0]W_45S_Q;\r
+always@(posedge I_CLK_6M)\r
+begin\r
+ if(I_SLDn==1'b0)\r
+ W_45S_Q <= I_HPOS;\r
+ else begin\r
+ if(I_C_BLn_X)\r
+ W_45S_Q <= W_45S_Q +1;\r
+ else\r
+ W_45S_Q <= W_45S_Q ;\r
+ end\r
+end\r
+\r
+reg W_5P2_Q;\r
+reg W_5P2_CLK;\r
+\r
+always@(posedge I_CLK_18M)\r
+ W_5P2_CLK <= ~((&W_45S_Q[7:2])&W_5P2_Q);\r
+\r
+always@(posedge W_5P2_CLK or negedge I_SLDn)\r
+begin\r
+ if(I_SLDn==1'b0)\r
+ W_5P2_Q <= 1'b1;\r
+ else\r
+ W_5P2_Q <= 1'b0;\r
+end\r
+\r
+assign O_SHELLn = W_5P2_CLK;\r
+\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA SOUND I/F\r
+//\r
+// Version : 1.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+//================================================================================\r
+\r
+\r
+module mc_sound_a(\r
+\r
+I_CLK_12M,\r
+I_CLK_6M,\r
+I_H_CNT1,\r
+I_BD,\r
+I_PITCHn,\r
+I_VOL1,\r
+I_VOL2,\r
+\r
+O_SDAT,\r
+O_DO\r
+\r
+);\r
+\r
+input I_CLK_12M;\r
+input I_CLK_6M;\r
+input I_H_CNT1;\r
+input [7:0]I_BD;\r
+input I_PITCHn;\r
+input I_VOL1;\r
+input I_VOL2;\r
+\r
+output [3:0]O_DO;\r
+output [7:0]O_SDAT;\r
+\r
+reg W_PITCHn;\r
+reg W_89K_LDn;\r
+reg [7:0]W_89K_Q;\r
+reg [7:0]W_89K_LDATA;\r
+reg [3:0]W_6T_Q;\r
+\r
+always@(posedge I_CLK_12M) \r
+begin\r
+ W_PITCHn <= I_PITCHn;\r
+ W_89K_LDn <= ~(&W_89K_Q[7:0]);\r
+end\r
+\r
+// Parts 9J\r
+always@(posedge W_PITCHn) W_89K_LDATA <= I_BD;\r
+\r
+always@(posedge I_H_CNT1)\r
+begin\r
+ if(~W_89K_LDn)\r
+ W_89K_Q <= W_89K_LDATA;\r
+ else\r
+ W_89K_Q <= W_89K_Q + 1; \r
+end\r
+\r
+always@(negedge W_89K_LDn) W_6T_Q <= W_6T_Q + 1;\r
+assign O_DO = W_6T_Q;\r
+\r
+reg [7:0]W_SDAT0;\r
+reg [7:0]W_SDAT2;\r
+reg [7:0]W_SDAT3;\r
+always@(posedge I_CLK_6M)\r
+begin\r
+ W_SDAT0 <= W_6T_Q[0]==1'b0 ? 8'd0 : 8'd42 ;\r
+ W_SDAT2 <= W_6T_Q[2]==1'b0 ? 8'd0 : I_VOL1 ? 8'd105 : 8'd57 ;\r
+ W_SDAT3 <= W_6T_Q[3]==1'b0 ? 8'd0 : I_VOL2 ? 8'd72 : 8'd0 ;\r
+end\r
+\r
+assign O_SDAT = W_SDAT0 + W_SDAT2 + W_SDAT3 + 8'd20 ;\r
+\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA WAVE SOUND\r
+//\r
+// Version : 1.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+//================================================================================\r
+\r
+\r
+module mc_sound_b(\r
+\r
+I_CLK1,\r
+I_CLK2,\r
+I_RSTn,\r
+I_SW,\r
+\r
+O_WAV_A0,\r
+O_WAV_A1,\r
+O_WAV_A2,\r
+I_WAV_D0,\r
+I_WAV_D1,\r
+I_WAV_D2,\r
+\r
+O_SDAT\r
+\r
+);\r
+\r
+input I_CLK1; // 18MHz\r
+input I_CLK2; // 6MHz\r
+input I_RSTn;\r
+input [2:0]I_SW;\r
+output [7:0]O_SDAT;\r
+output [18:0]O_WAV_A0;\r
+output [18:0]O_WAV_A1;\r
+output [18:0]O_WAV_A2;\r
+input [7:0]I_WAV_D0;\r
+input [7:0]I_WAV_D1;\r
+input [7:0]I_WAV_D2;\r
+\r
+parameter sample_time = 1670/2; // sample time 22050Hz\r
+//parameter sample_time = 1670; // sample time 11025Hz\r
+parameter fire_cnt = 14'h3FF0;\r
+parameter hit_cnt = 16'hA830;\r
+parameter effect_cnt = 16'hBFC0;\r
+\r
+reg [9:0]sample;\r
+reg sample_pls;\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)begin\r
+ sample <= 0;\r
+ sample_pls <= 0;\r
+ end\r
+ else begin\r
+ sample <= (sample == sample_time-1)? 0 : sample+1;\r
+ sample_pls <= (sample == sample_time-1)? 1 : 0 ;\r
+ end\r
+end\r
+\r
+//----------- FIRE SOUND ------------------------------------------\r
+reg [13:0]fire_ad;\r
+reg [1:0]s0_trg_ff;\r
+reg s0_trg;\r
+reg s0_play;\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)begin\r
+ s0_trg_ff <= 0;\r
+ s0_trg <= 0;\r
+ end\r
+ else begin\r
+ s0_trg_ff[0] <= I_SW[0];\r
+ s0_trg_ff[1] <= s0_trg_ff[0];\r
+ s0_trg <= ~s0_trg_ff[1]&s0_trg_ff[0]&~s0_play;\r
+ end\r
+end\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)\r
+ s0_play <= 0;\r
+ else begin\r
+ if(fire_ad <= fire_cnt-1)\r
+ s0_play <= 1;\r
+ else\r
+ s0_play <= 0;\r
+ end\r
+end\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)\r
+ fire_ad <= fire_cnt;\r
+ else begin\r
+ if(s0_trg) fire_ad <= 0;\r
+ else begin\r
+ if(sample_pls)begin \r
+ if(fire_ad <= fire_cnt)\r
+ fire_ad <= fire_ad +1 ;\r
+ else\r
+ fire_ad <= fire_ad ;\r
+ end\r
+ end\r
+ end\r
+end\r
+//----------- HIT SOUND ------------------------------------------\r
+reg [15:0]hit_ad;\r
+reg [1:0]s1_trg_ff;\r
+reg s1_trg;\r
+reg s1_play;\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)begin\r
+ s1_trg_ff <= 0;\r
+ s1_trg <= 0;\r
+ end\r
+ else begin\r
+ s1_trg_ff[0] <= I_SW[1];\r
+ s1_trg_ff[1] <= s1_trg_ff[0];\r
+ s1_trg <= ~s1_trg_ff[1]&s1_trg_ff[0]&~s1_play;\r
+ end\r
+end\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)\r
+ s1_play <= 0;\r
+ else begin\r
+ if(hit_ad <= hit_cnt-1)\r
+ s1_play <= 1;\r
+ else\r
+ s1_play <= 0;\r
+ end\r
+end\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)\r
+ hit_ad <= hit_cnt;\r
+ else begin\r
+ if(s1_trg) hit_ad <= 0;\r
+ else begin\r
+ if(sample_pls)begin \r
+ if(hit_ad <= hit_cnt)\r
+ hit_ad <= hit_ad +1 ;\r
+ else\r
+ hit_ad <= hit_ad ;\r
+ end\r
+ end\r
+ end\r
+end\r
+//----------- EFFICT SOUND ---------------------------------------\r
+reg [15:0]effect_ad;\r
+\r
+always@(posedge I_CLK1 or negedge I_RSTn)\r
+begin\r
+ if(I_RSTn == 1'b0)\r
+ effect_ad <= effect_cnt;\r
+ else begin\r
+ if(I_SW[2])begin\r
+ if(sample_pls)begin\r
+ if(effect_ad >= effect_cnt)\r
+ effect_ad <= 0;\r
+ else\r
+ effect_ad <= effect_ad + 1;\r
+ end\r
+ end\r
+ else begin\r
+ effect_ad <= effect_cnt;\r
+ end \r
+ end\r
+end\r
+\r
+assign O_WAV_A0 = {3'h1,2'h0,fire_ad};\r
+assign O_WAV_A1 = {3'h1,4'h4+hit_ad[15:12],hit_ad[11:0]};\r
+assign O_WAV_A2 = {3'h2,effect_ad};\r
+\r
+wire [7:0]W_WAV_D0 = I_WAV_D0;\r
+wire [7:0]W_WAV_D1 = I_WAV_D1;\r
+wire [7:0]W_WAV_D2 = I_WAV_D2;\r
+\r
+// sound mix\r
+wire [8:0]mix0 = W_WAV_D0 + W_WAV_D1 ; \r
+reg [8:0]mix_0;\r
+always@(posedge I_CLK1)\r
+begin\r
+ if(mix0 >= 9'h17F) // POS Limiter\r
+ mix_0 <= 9'h0FF;\r
+ else if(mix0 <= 9'h080)// NEG Limiter\r
+ mix_0 <= 9'h000;\r
+ else\r
+ mix_0 <= mix0 - 9'h080; \r
+end\r
+\r
+wire [8:0]mix1 = mix0[7:0] + W_WAV_D2 ; \r
+reg [8:0]mix_1;\r
+always@(posedge I_CLK1)\r
+begin\r
+ if(mix1 >= 9'h17F) // POS Limiter\r
+ mix_1 <= 9'h0FF;\r
+ else if(mix1 <= 9'h080)// NEG Limiter\r
+ mix_1 <= 9'h000;\r
+ else\r
+ mix_1 <= mix1 - 9'h080; \r
+end\r
+\r
+assign O_SDAT = mix_1[7:0];\r
+\r
+\r
+endmodule\r
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA STARS\r
+//\r
+// Version : 2.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 9-22 \r
+//================================================================================\r
+\r
+\r
+module mc_stars(\r
+\r
+I_CLK_18M,\r
+I_CLK_6M,\r
+I_H_FLIP,\r
+I_V_SYNC,\r
+I_8HF,\r
+I_256HnX,\r
+I_1VF,\r
+I_2V,\r
+I_STARS_ON,\r
+I_STARS_OFFn,\r
+\r
+O_R,\r
+O_G,\r
+O_B,\r
+O_NOISE\r
+\r
+);\r
+\r
+input I_CLK_18M;\r
+input I_CLK_6M;\r
+input I_H_FLIP;\r
+input I_V_SYNC;\r
+input I_8HF;\r
+input I_256HnX;\r
+input I_1VF;\r
+input I_2V;\r
+input I_STARS_ON;\r
+input I_STARS_OFFn;\r
+\r
+output [2:0]O_R;\r
+output [2:0]O_G;\r
+output [1:0]O_B;\r
+output O_NOISE;\r
+\r
+wire W_V_SYNCn = ~I_V_SYNC;\r
+\r
+wire CLK_1C = ~(I_CLK_18M & I_CLK_6M & W_V_SYNCn & I_256HnX);\r
+\r
+reg W_1C_Q1,W_1C_Q2;\r
+always@(posedge CLK_1C or negedge W_V_SYNCn)\r
+begin\r
+ if(W_V_SYNCn==1'b0)begin\r
+ W_1C_Q1 <= 1'b0;\r
+ W_1C_Q2 <= 1'b0;\r
+ end\r
+ else begin\r
+ W_1C_Q1 <= 1'b1;\r
+ W_1C_Q2 <= W_1C_Q1;\r
+ end\r
+end\r
+\r
+wire CLK_1AB = ~(CLK_1C |(~(I_H_FLIP|W_1C_Q2))) ;\r
+\r
+reg [15:0]W_1AB_Q;\r
+reg W_2D_Qn;\r
+wire W_3B = W_2D_Qn^W_1AB_Q[4];\r
+\r
+always@(posedge CLK_1AB or negedge I_STARS_ON)\r
+begin\r
+ if(I_STARS_ON==1'b0)begin\r
+ W_1AB_Q <= 0;\r
+ W_2D_Qn <= 1'b1;\r
+ end\r
+ else begin\r
+ W_1AB_Q <= {W_1AB_Q[14:0],W_3B};\r
+ W_2D_Qn <= ~W_1AB_Q[15];\r
+ end\r
+end\r
+\r
+wire W_2A = ~(& W_1AB_Q[7:0]);\r
+wire W_4P = ~(( I_8HF ^ I_1VF ) & W_2D_Qn & I_STARS_OFFn);\r
+\r
+assign O_R[2] = 1'b0 ; \r
+assign O_R[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[8] ; \r
+assign O_R[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[9] ; \r
+\r
+assign O_G[2] = 1'b0 ; \r
+assign O_G[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[10] ; \r
+assign O_G[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[11] ; \r
+\r
+assign O_B[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[12] ; \r
+assign O_B[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[13] ; \r
+\r
+reg noise;\r
+always@(posedge I_2V) noise <= W_2D_Qn ;\r
+assign O_NOISE = noise ;\r
+\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//===============================================================================\r
+// FPGA GALAXIAN TOP\r
+//\r
+// Version : 2.50\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 4-30 galaxian modify by K.DEGAWA\r
+// 2004- 5- 6 first release.\r
+// 2004- 8-23 Improvement with T80-IP.\r
+// 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.\r
+// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
+//================================================================================\r
+\r
+`include "src/mc_conf.v" \r
+ \r
+module mc_top(\r
+\r
+// FPGA_USE\r
+I_CLK_125M,\r
+\r
+`ifdef PSPAD_USE\r
+// PS_PAD interface\r
+psCLK,\r
+psSEL,\r
+psTXD,\r
+psRXD,\r
+`endif\r
+\r
+// ROM IF\r
+//O_ROM_AB,\r
+//I_ROM_DB,\r
+//O_ROM_OEn,\r
+//O_ROM_CSn,\r
+//O_ROM_WEn,\r
+\r
+// INPORT SW IF\r
+I_PSW,\r
+\r
+// SOUND OUT\r
+O_SOUND_OUT_L,\r
+O_SOUND_OUT_R,\r
+\r
+// VGA (VIDEO) IF\r
+O_VGA_R,\r
+O_VGA_G,\r
+O_VGA_B,\r
+O_VGA_H_SYNCn,\r
+O_VGA_V_SYNCn\r
+\r
+);\r
+\r
+// FPGA_USE\r
+input I_CLK_125M;\r
+\r
+// CPU ADDRESS BUS\r
+wire [15:0]W_A;\r
+// CPU IF\r
+wire W_CPU_RDn;\r
+wire W_CPU_WRn;\r
+wire W_CPU_MREQn;\r
+wire W_CPU_RFSHn;\r
+wire W_CPU_BUSAKn;\r
+wire W_CPU_IORQn;\r
+wire W_CPU_M1n;\r
+wire W_CPU_CLK;\r
+wire W_CPU_HRDWR_RESETn;\r
+wire W_CPU_WAITn;\r
+wire W_CPU_NMIn;\r
+\r
+`ifdef PSPAD_USE\r
+// PS_PAD interface\r
+input psRXD;\r
+output psTXD,psCLK,psSEL;\r
+`endif\r
+\r
+// ROM IF\r
+//output [18:0]O_ROM_AB;\r
+//input [7:0]I_ROM_DB;\r
+//output O_ROM_OEn;\r
+//output O_ROM_CSn;\r
+//output O_ROM_WEn;\r
+\r
+// INPORT SW IF\r
+input [4:0]I_PSW;\r
+\r
+// SOUND OUT \r
+output O_SOUND_OUT_L;\r
+output O_SOUND_OUT_R;\r
+\r
+// VGA (VIDEO) IF\r
+output [4:0]O_VGA_R;\r
+output [4:0]O_VGA_G;\r
+output [4:0]O_VGA_B;\r
+output O_VGA_H_SYNCn;\r
+output O_VGA_V_SYNCn;\r
+\r
+wire W_RESETn = |I_PSW[3:0];\r
+//------ CLOCK GEN ---------------------------\r
+wire I_CLK_18432M;\r
+wire W_CLK_12M,WB_CLK_12M;\r
+wire W_CLK_6M,WB_CLK_6M;\r
+wire W_STARS_CLK;\r
+\r
+dcm clockgen(\r
+.CLKIN_IN(I_CLK_125M),\r
+.RST_IN(W_RESETn),\r
+.CLKFX_OUT(I_CLK_18432M)\r
+);\r
+\r
+//------ H&V COUNTER -------------------------\r
+wire [8:0]W_H_CNT;\r
+wire [7:0]W_V_CNT;\r
+wire W_H_BL;\r
+wire W_V_BLn;\r
+wire W_C_BLn;\r
+wire W_H_SYNC;\r
+wire W_V_SYNC;\r
+\r
+//------ CPU RAM ----------------------------\r
+wire [7:0]W_CPU_RAM_DO;\r
+\r
+//------ ADDRESS DECDER ----------------------\r
+wire W_CPU_ROM_CSn;\r
+wire W_CPU_RAM_RDn;\r
+wire W_CPU_RAM_WRn;\r
+wire W_CPU_RAM_CSn;\r
+wire W_OBJ_RAM_RDn;\r
+wire W_OBJ_RAM_WRn;\r
+wire W_OBJ_RAM_RQn;\r
+wire W_VID_RAM_RDn;\r
+wire W_VID_RAM_WRn;\r
+wire W_SW0_OEn;\r
+wire W_SW1_OEn;\r
+wire W_DIP_OEn;\r
+wire W_WDR_OEn;\r
+wire W_LAMP_WEn;\r
+wire W_SOUND_WEn;\r
+wire W_PITCHn;\r
+wire W_H_FLIP;\r
+wire W_V_FLIP;\r
+wire W_BD_G;\r
+wire W_STARS_ON;\r
+\r
+wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;\r
+wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;\r
+//------- INPORT -----------------------------\r
+wire [7:0]W_SW_DO;\r
+//------- VIDEO -----------------------------\r
+wire [7:0]W_VID_DO;\r
+//--------------------------------------------\r
+\r
+mc_clock MC_CLK(\r
+\r
+.I_CLK_18M(I_CLK_18432M),\r
+.O_CLK_12M(WB_CLK_12M),\r
+.O_CLK_06M(WB_CLK_6M)\r
+\r
+);\r
+\r
+`ifdef DEVICE_CYCLONE\r
+assign W_CLK_12M = WB_CLK_12M;\r
+assign W_CLK_6M = WB_CLK_6M;\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E\r
+BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
+BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
+`endif\r
+//--- DATA I/F -------------------------------------\r
+reg [7:0]W_CPU_ROM_DO;\r
+wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
+\r
+wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;\r
+wire [7:0]W_BDI;\r
+\r
+//--- CPU I/F -------------------------------------\r
+reg [3:0]rst_count;\r
+always@(posedge W_H_CNT[0] or negedge W_RESETn)\r
+begin\r
+ if(! W_RESETn) rst_count <= 0;\r
+ else begin\r
+ if( rst_count == 15) \r
+ rst_count <= rst_count;\r
+ else\r
+ rst_count <= rst_count+1;\r
+ end\r
+end\r
+\r
+assign W_CPU_RESETn = W_RESETn;\r
+assign W_CPU_CLK = W_H_CNT[0];\r
+\r
+Z80IP CPU(\r
+ \r
+.CLK(W_CPU_CLK),\r
+.RESET_N(W_CPU_RESETn),\r
+.INT_N(1'b1),\r
+.NMI_N(W_CPU_NMIn),\r
+.ADRS(W_A),\r
+.DOUT(W_BDI),\r
+.DINP(W_BDO),\r
+.M1_N(),\r
+.MREQ_N(W_CPU_MREQn),\r
+.IORQ_N(),\r
+.RD_N(W_CPU_RDn ),\r
+.WR_N(W_CPU_WRn ),\r
+.WAIT_N(W_CPU_WAITn),\r
+.BUSWO(),\r
+.RFSH_N(W_CPU_RFSHn),\r
+.HALT_N()\r
+\r
+);\r
+\r
+wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;\r
+\r
+mc_cpu_ram MC_CPU_RAM(\r
+\r
+.I_CLK(W_CPU_RAM_CLK),\r
+.I_ADDR(W_A[9:0]),\r
+.I_D(W_BDI),\r
+.I_WE(~W_CPU_WRn),\r
+.I_OE(~W_CPU_RAM_RDn ),\r
+.O_D(W_CPU_RAM_DO)\r
+\r
+);\r
+\r
+\r
+mc_adec MC_ADEC(\r
+\r
+.I_CLK_12M(W_CLK_12M),\r
+.I_CLK_6M(W_CLK_6M),\r
+.I_CPU_CLK(W_H_CNT[0]),\r
+.I_RSTn(W_RESETn),\r
+\r
+.I_CPU_A(W_A),\r
+.I_CPU_D(W_BDI[0]),\r
+.I_MREQn(W_CPU_MREQn),\r
+.I_RFSHn(W_CPU_RFSHn),\r
+.I_RDn(W_CPU_RDn),\r
+.I_WRn(W_CPU_WRn),\r
+.I_H_BL(W_H_BL),\r
+.I_V_BLn(W_V_BLn),\r
+\r
+.O_WAITn(W_CPU_WAITn),\r
+.O_NMIn(W_CPU_NMIn),\r
+.O_CPU_ROM_CSn(W_CPU_ROM_CSn),\r
+.O_CPU_RAM_RDn(W_CPU_RAM_RDn),\r
+.O_CPU_RAM_WRn(W_CPU_RAM_WRn),\r
+.O_CPU_RAM_CSn(W_CPU_RAM_CSn),\r
+.O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
+.O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
+.O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
+.O_VID_RAM_RDn(W_VID_RAM_RDn),\r
+.O_VID_RAM_WRn(W_VID_RAM_WRn),\r
+.O_SW0_OEn(W_SW0_OEn),\r
+.O_SW1_OEn(W_SW1_OEn),\r
+.O_DIP_OEn(W_DIP_OEn),\r
+.O_WDR_OEn(W_WDR_OEn),\r
+.O_LAMP_WEn(W_LAMP_WEn),\r
+.O_SOUND_WEn(W_SOUND_WEn),\r
+.O_PITCHn(W_PITCHn),\r
+.O_H_FLIP(W_H_FLIP),\r
+.O_V_FLIP(W_V_FLIP),\r
+.O_BD_G(W_BD_G),\r
+.O_STARS_ON(W_STARS_ON)\r
+\r
+);\r
+\r
+//-------- SOUND I/F -----------------------------\r
+//--- Parts 9L ---------\r
+reg [7:0]W_9L_Q;\r
+always@(posedge W_CLK_12M or negedge W_RESETn)\r
+begin\r
+ if(W_RESETn == 1'b0)begin\r
+ W_9L_Q <= 0;\r
+ end \r
+ else begin\r
+ if(W_SOUND_WEn == 1'b0)begin\r
+ case(W_A[2:0])\r
+ 3'h0 : W_9L_Q[0] <= W_BDI[0];\r
+ 3'h1 : W_9L_Q[1] <= W_BDI[0];\r
+ 3'h2 : W_9L_Q[2] <= W_BDI[0];\r
+ 3'h3 : W_9L_Q[3] <= W_BDI[0];\r
+ 3'h4 : W_9L_Q[4] <= W_BDI[0];\r
+ 3'h5 : W_9L_Q[5] <= W_BDI[0];\r
+ 3'h6 : W_9L_Q[6] <= W_BDI[0];\r
+ 3'h7 : W_9L_Q[7] <= W_BDI[0];\r
+ endcase\r
+ end\r
+ end\r
+end\r
+wire W_VOL1 = W_9L_Q[6];\r
+wire W_VOL2 = W_9L_Q[7];\r
+wire W_FIRE = W_9L_Q[5];\r
+wire W_HIT = W_9L_Q[3];\r
+wire W_FS3 = W_9L_Q[2];\r
+wire W_FS2 = W_9L_Q[1];\r
+wire W_FS1 = W_9L_Q[0];\r
+//---------------------------------------------------\r
+//---- CPU DATA WATCH -------------------------------\r
+wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;\r
+\r
+reg [1:0]on_game;\r
+always @(posedge W_CPU_CLK)\r
+begin\r
+ if(~ZMWR)begin\r
+ if(W_A == 16'h4007)begin\r
+ if(W_BDI == 8'h00) \r
+ on_game[0] <= 1;\r
+ else\r
+ on_game[0] <= 0;\r
+ end\r
+ if(W_A == 16'h4005)begin\r
+ if(W_BDI == 8'h03 || W_BDI == 8'h04 ) \r
+ on_game[1] <= 1;\r
+ else\r
+ on_game[1] <= 0;\r
+ end\r
+ end \r
+end\r
+\r
+`ifdef PSPAD_USE\r
+reg died;\r
+always @(posedge W_CPU_CLK)\r
+begin\r
+ if(~ZMWR)begin\r
+ if(W_A == 16'h4206)begin\r
+ if(W_BDI == 8'h00) \r
+ died <= 0;\r
+ else\r
+ died <= 1;\r
+ end\r
+ end\r
+end\r
+//---- PS_PAD Interface -----------------------------\r
+wire [8:0]ps_PSW;\r
+wire VIB_SW = died & (&on_game[1:0]);\r
+\r
+fpga_arcade_if pspad(\r
+\r
+.CLK_18M432(I_CLK_18432M),\r
+.I_RSTn(W_RESETn),\r
+.psCLK(psCLK),\r
+.psSEL(psSEL),\r
+.psTXD(psTXD),\r
+.psRXD(psRXD),\r
+.ps_PSW(ps_PSW),\r
+.I_VIB_SW(VIB_SW)\r
+\r
+);\r
+`endif\r
+//---- SW Interface ---------------------------------\r
+`ifdef PSPAD_USE\r
+wire L1 = I_PSW[2] & ps_PSW[2];\r
+wire R1 = I_PSW[3] & ps_PSW[3];\r
+wire U1 = I_PSW[0];\r
+wire D1 = I_PSW[1];\r
+wire J1 = I_PSW[4] & ps_PSW[8];\r
+\r
+wire S1 = (U1|J1) & ps_PSW[6];\r
+wire S2 = (D1|J1) & ps_PSW[7];\r
+\r
+wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];\r
+`else\r
+wire L1 = I_PSW[2];\r
+wire R1 = I_PSW[3];\r
+wire U1 = I_PSW[0];\r
+wire D1 = I_PSW[1];\r
+wire J1 = I_PSW[4];\r
+\r
+wire S1 = U1|J1;\r
+wire S2 = D1|J1;\r
+\r
+wire C1 = L1|R1|U1|~D1;\r
+`endif\r
+wire C2 = L1|R1|~U1|D1;\r
+\r
+wire L2 = L1;\r
+wire R2 = R1;\r
+wire U2 = U1;\r
+wire D2 = D1;\r
+wire J2 = J1;\r
+\r
+mc_inport MC_INPORT(\r
+\r
+.I_COIN1(~C1), // ACTIVE HI\r
+.I_COIN2(~C2), // ACTIVE HI\r
+.I_1P_LE(~L1), // ACTIVE HI\r
+.I_1P_RI(~R1), // ACTIVE HI\r
+.I_1P_SH(~J1), // ACTIVE HI\r
+.I_2P_LE(~L2), // ACTIVE HI\r
+.I_2P_RI(~R2), // ACTIVE HI\r
+.I_2P_SH(~J2), // ACTIVE HI\r
+.I_1P_START(~S1), // ACTIVE HI\r
+.I_2P_START(~S2), // ACTIVE HI\r
+\r
+.I_SW0_OEn(W_SW0_OEn),\r
+.I_SW1_OEn(W_SW1_OEn),\r
+.I_DIP_OEn(W_DIP_OEn),\r
+\r
+.O_D(W_SW_DO)\r
+\r
+);\r
+\r
+//-----------------------------------------------------------------------------\r
+//------- ROM -------------------------------------------------------\r
+reg [18:0]ROM_A;\r
+wire [10:0]W_OBJ_ROM_A;\r
+reg [7:0]W_OBJ_ROM_A_D;\r
+reg [7:0]W_OBJ_ROM_B_D;\r
+\r
+wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
+reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
+\r
+wire [7:0]ROM_D; // = I_ROM_DB;\r
+//assign O_ROM_AB = ROM_A;\r
+\r
+//assign O_ROM_OEn = 1'b0;\r
+//assign O_ROM_CSn = 1'b0;\r
+//assign O_ROM_WEn = 1'b1;\r
+\r
+galaxian_roms ROMS(\r
+.I_CLK_18432M(I_CLK_18432M),\r
+.I_CLK_12M(WB_CLK_12M),\r
+.I_ADDR(ROM_A),\r
+.O_DATA(ROM_D)\r
+);\r
+\r
+\r
+reg [1:0]clk_d;\r
+reg [4:0]seq;\r
+always @(posedge I_CLK_18432M)\r
+begin\r
+ // 24 phase generator\r
+ clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];\r
+ clk_d[1] <= clk_d[0];\r
+ seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;\r
+ case(seq)\r
+ 0:begin\r
+ //sound\r
+ ROM_A <= W_WAV_A0;\r
+ W_CPU_ROM_DO <= ROM_D;\r
+ end\r
+ 2:begin\r
+ //sound\r
+ ROM_A <= W_WAV_A1;\r
+ W_WAV_D0 <= ROM_D;\r
+ end\r
+ 4:begin\r
+ //sound\r
+ ROM_A <= {3'h0,W_A[15:0]};\r
+ W_WAV_D1 <= ROM_D;\r
+ end\r
+ 6:begin\r
+ //sound\r
+ ROM_A <= W_WAV_A2;\r
+ W_CPU_ROM_DO <= ROM_D;\r
+ end\r
+ 8:W_WAV_D2 <= ROM_D; //sound\r
+ 10:ROM_A <= {3'h0,W_A[15:0]};\r
+ 12:W_CPU_ROM_DO <= ROM_D;\r
+ 16:ROM_A <= {3'h0,W_A[15:0]};\r
+ 18:begin\r
+ ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};\r
+ W_CPU_ROM_DO <= ROM_D;\r
+ end\r
+ 20:begin\r
+ ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};\r
+ W_OBJ_ROM_A_D <= ROM_D;\r
+ end\r
+ 22:begin\r
+ ROM_A <= {3'h0,W_A[15:0]};\r
+ W_OBJ_ROM_B_D <= ROM_D;\r
+ end\r
+ default:;\r
+ endcase\r
+end\r
+//-----------------------------------------------------------------------------\r
+\r
+wire W_V_BL2n;\r
+\r
+mc_hv_count MC_HV(\r
+\r
+.I_CLK(WB_CLK_6M),\r
+.I_RSTn(W_RESETn),\r
+\r
+.O_H_CNT(W_H_CNT),\r
+.O_H_SYNC(W_H_SYNC),\r
+.O_H_BL(W_H_BL),\r
+.O_V_CNT(W_V_CNT),\r
+.O_V_SYNC(W_V_SYNC),\r
+.O_V_BL2n(W_V_BL2n),\r
+.O_V_BLn(W_V_BLn),\r
+.O_C_BLn(W_C_BLn)\r
+\r
+);\r
+\r
+//------ VIDEO -----------------------------\r
+wire W_8HF;\r
+wire W_1VF;\r
+wire W_C_BLnX;\r
+wire W_256HnX;\r
+wire W_MISSILEn;\r
+wire W_SHELLn;\r
+wire [1:0]W_VID;\r
+wire [2:0]W_COL;\r
+\r
+mc_video MC_VID(\r
+.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_12M(W_CLK_12M),\r
+.I_CLK_6M(W_CLK_6M),\r
+.I_H_CNT(W_H_CNT),\r
+.I_V_CNT(W_V_CNT),\r
+.I_H_FLIP(W_H_FLIP),\r
+.I_V_FLIP(W_V_FLIP),\r
+.I_V_BLn(W_V_BLn),\r
+.I_C_BLn(W_C_BLn),\r
+\r
+.I_A(W_A[9:0]),\r
+.I_OBJ_SUB_A(3'b000),\r
+.I_BD(W_BDI),\r
+.I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
+.I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
+.I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
+.I_VID_RAM_RDn(W_VID_RAM_RDn),\r
+.I_VID_RAM_WRn(W_VID_RAM_WRn),\r
+\r
+.O_OBJ_ROM_A(W_OBJ_ROM_A),\r
+.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),\r
+.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),\r
+\r
+.O_C_BLnX(W_C_BLnX),\r
+.O_8HF(W_8HF),\r
+.O_256HnX(W_256HnX),\r
+.O_1VF(W_1VF),\r
+.O_MISSILEn(W_MISSILEn),\r
+.O_SHELLn(W_SHELLn),\r
+.O_BD(W_VID_DO),\r
+.O_VID(W_VID),\r
+.O_COL(W_COL)\r
+\r
+);\r
+\r
+wire W_C_BLX;\r
+wire W_STARS_OFFn;\r
+wire [2:0]W_VIDEO_R;\r
+wire [2:0]W_VIDEO_G;\r
+wire [1:0]W_VIDEO_B;\r
+\r
+mc_col_pal MC_COL_PAL(\r
+\r
+.I_CLK_12M(W_CLK_12M),\r
+.I_CLK_6M(W_CLK_6M),\r
+.I_VID(W_VID),\r
+.I_COL(W_COL),\r
+.I_C_BLnX(W_C_BLnX),\r
+\r
+.O_C_BLX(W_C_BLX),\r
+.O_STARS_OFFn(W_STARS_OFFn),\r
+.O_R(W_VIDEO_R),\r
+.O_G(W_VIDEO_G),\r
+.O_B(W_VIDEO_B)\r
+\r
+);\r
+\r
+wire [2:0]W_STARS_R;\r
+wire [2:0]W_STARS_G;\r
+wire [1:0]W_STARS_B;\r
+\r
+mc_stars MC_STARS( \r
+\r
+.I_CLK_18M(I_CLK_18432M),\r
+`ifdef DEVICE_CYCLONE\r
+.I_CLK_6M(~WB_CLK_6M),\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E \r
+.I_CLK_6M(WB_CLK_6M), \r
+`endif\r
+.I_H_FLIP(W_H_FLIP),\r
+.I_V_SYNC(W_V_SYNC),\r
+.I_8HF(W_8HF),\r
+.I_256HnX(W_256HnX),\r
+.I_1VF(W_1VF),\r
+.I_2V(W_V_CNT[1]),\r
+.I_STARS_ON(W_STARS_ON),\r
+.I_STARS_OFFn(W_STARS_OFFn),\r
+\r
+.O_R(W_STARS_R),\r
+.O_G(W_STARS_G),\r
+.O_B(W_STARS_B),\r
+.O_NOISE()\r
+\r
+);\r
+\r
+wire [2:0]W_R;\r
+wire [2:0]W_G;\r
+wire [1:0]W_B;\r
+\r
+mc_vedio_mix MIX(\r
+\r
+.I_VID_R(W_VIDEO_R),\r
+.I_VID_G(W_VIDEO_G),\r
+.I_VID_B(W_VIDEO_B),\r
+.I_STR_R(W_STARS_R),\r
+.I_STR_G(W_STARS_G),\r
+.I_STR_B(W_STARS_B),\r
+\r
+.I_C_BLnXX(~W_C_BLX),\r
+.I_C_BLX(W_C_BLX | ~W_V_BL2n),\r
+.I_MISSILEn(W_MISSILEn),\r
+.I_SHELLn(W_SHELLn),\r
+\r
+.O_R(W_R),\r
+.O_G(W_G),\r
+.O_B(W_B)\r
+\r
+);\r
+\r
+`ifdef VGA_USE\r
+mc_vga_if VGA(\r
+\r
+// input\r
+.I_CLK_1(W_CLK_6M),\r
+.I_CLK_2(W_CLK_12M),\r
+.I_R(W_R),\r
+.I_G(W_G),\r
+.I_B(W_B),\r
+.I_H_SYNC(W_H_SYNC),\r
+.I_V_SYNC(W_V_SYNC),\r
+// output\r
+.O_R(O_VGA_R),\r
+.O_G(O_VGA_G),\r
+.O_B(O_VGA_B),\r
+.O_H_SYNCn(O_VGA_H_SYNCn),\r
+.O_V_SYNCn(O_VGA_V_SYNCn)\r
+\r
+);\r
+\r
+`else\r
+\r
+assign O_VGA_R[2:0] = W_R;\r
+assign O_VGA_R[4:3] = 1'b0;\r
+\r
+assign O_VGA_G[2:0] = W_G;\r
+assign O_VGA_G[4:3] = 1'b0;\r
+\r
+assign O_VGA_B[1:0] = W_B;\r
+assign O_VGA_B[4:2] = 1'b0;\r
+\r
+//assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED\r
+assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
+assign O_VGA_V_SYNCn = ~W_V_SYNC ;\r
+\r
+`endif\r
+\r
+wire [7:0]W_SDAT_A;\r
+\r
+mc_sound_a MC_SOUND_A(\r
+\r
+.I_CLK_12M(W_CLK_12M),\r
+.I_CLK_6M(W_CLK_6M),\r
+.I_H_CNT1(W_H_CNT[1]),\r
+.I_BD(W_BDI),\r
+.I_PITCHn(W_PITCHn),\r
+.I_VOL1(W_VOL1),\r
+.I_VOL2(W_VOL2),\r
+\r
+.O_SDAT(W_SDAT_A),\r
+.O_DO()\r
+\r
+);\r
+\r
+wire [7:0]W_SDAT_B;\r
+\r
+mc_sound_b MC_SOUND_B(\r
+\r
+.I_CLK1(I_CLK_18432M),\r
+.I_CLK2(W_CLK_6M),\r
+.I_RSTn(rst_count[3]),\r
+.I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
+\r
+.O_WAV_A0(W_WAV_A0),\r
+.O_WAV_A1(W_WAV_A1),\r
+.O_WAV_A2(W_WAV_A2),\r
+.I_WAV_D0(W_WAV_D0),\r
+.I_WAV_D1(W_WAV_D1),\r
+.I_WAV_D2(W_WAV_D2),\r
+\r
+.O_SDAT(W_SDAT_B)\r
+\r
+);\r
+\r
+wire W_DAC_A;\r
+wire W_DAC_B;\r
+\r
+assign O_SOUND_OUT_L = W_DAC_A;\r
+assign O_SOUND_OUT_R = W_DAC_B;\r
+\r
+dac wav_dac_a(\r
+\r
+.Clk(I_CLK_18432M), \r
+.Reset(~W_RESETn),\r
+.DACin(W_SDAT_A),\r
+.DACout(W_DAC_A)\r
+\r
+);\r
+\r
+dac wav_dac_b(\r
+\r
+.Clk(I_CLK_18432M), \r
+.Reset(~W_RESETn),\r
+.DACin(W_SDAT_B),\r
+.DACout(W_DAC_B)\r
+\r
+);\r
+\r
+\r
+endmodule\r
+\r
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA VIDO-MIX\r
+//\r
+// Version : 1.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+//================================================================================\r
+\r
+\r
+module mc_vedio_mix(\r
+\r
+I_VID_R,\r
+I_VID_G,\r
+I_VID_B,\r
+I_STR_R,\r
+I_STR_G,\r
+I_STR_B,\r
+\r
+I_C_BLnXX,\r
+I_C_BLX,\r
+I_MISSILEn,\r
+I_SHELLn,\r
+\r
+O_R,\r
+O_G,\r
+O_B\r
+\r
+);\r
+\r
+input [2:0]I_VID_R;\r
+input [2:0]I_VID_G;\r
+input [1:0]I_VID_B;\r
+input [2:0]I_STR_R;\r
+input [2:0]I_STR_G;\r
+input [1:0]I_STR_B;\r
+\r
+input I_C_BLnXX;\r
+input I_C_BLX;\r
+input I_MISSILEn;\r
+input I_SHELLn;\r
+\r
+output [2:0]O_R;\r
+output [2:0]O_G;\r
+output [1:0]O_B;\r
+\r
+// MISSILE => Yellow ;\r
+// SHELL => White ;\r
+wire W_MS_D = ~(I_MISSILEn & I_SHELLn);\r
+wire W_MS_R = ~I_C_BLX & W_MS_D;\r
+wire W_MS_G = ~I_C_BLX & W_MS_D;\r
+wire W_MS_B = ~I_C_BLX & W_MS_D & ~I_SHELLn ;\r
+\r
+assign O_R = I_C_BLnXX ? I_VID_R | I_STR_R | {1'b0,W_MS_R,W_MS_R}: 3'b000 ;\r
+assign O_G = I_C_BLnXX ? I_VID_G | I_STR_G | {1'b0,W_MS_G,W_MS_G}: 3'b000 ;\r
+assign O_B = I_C_BLnXX ? I_VID_B | I_STR_B | { W_MS_B,W_MS_B}: 2'b00 ;\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+//===============================================================================\r
+// FPGA VGA INTERFACE FOR ALTERA CYCLONE & XILINX SPARTAN2E\r
+//\r
+// Version : 2.00\r
+//\r
+// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// based on a design by Tatsuyuki Satoh\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 9-18 added SPARTAN2E DEVIDE . K.DEGAWA\r
+//================================================================================\r
+`include "src/mc_conf.v"\r
+\r
+module mc_vga_if(\r
+\r
+I_CLK_1,\r
+I_CLK_2,\r
+I_R,\r
+I_G,\r
+I_B,\r
+I_H_SYNC,\r
+I_V_SYNC,\r
+\r
+O_R,\r
+O_G,\r
+O_B,\r
+O_H_SYNCn,\r
+O_V_SYNCn\r
+\r
+);\r
+\r
+// input signals\r
+input I_CLK_1; // 6.144MHz input pixel clock\r
+input I_CLK_2; // 12.288Mhz output pixel clock\r
+input [2:0]I_R; // R in\r
+input [2:0]I_G; // G in\r
+input [1:0]I_B; // B in\r
+input I_H_SYNC; // HSYNC input (16KHz)\r
+input I_V_SYNC; // VSYNC input (60Hz)\r
+\r
+// output signals\r
+output [4:0]O_R; // R out\r
+output [4:0]O_G; // G out\r
+output [4:0]O_B; // B out\r
+output O_H_SYNCn; // HSYNC output\r
+output O_V_SYNCn; // VSYNC output\r
+\r
+//---------------------------------------------------------------------------\r
+// setup parameter\r
+//---------------------------------------------------------------------------\r
+\r
+parameter H_COUNT = 384; // number of pixels in H-SCAN\r
+parameter HS_POS = 16; // HSYNC position \r
+parameter HS_WIDTH = HS_POS+8; // HSYNC width / pixel\r
+parameter VS_WIDTH = 8; // VSYNC width / HSYNC_OUT\r
+\r
+//---------------------------------------------------------------------------\r
+// input timming\r
+//---------------------------------------------------------------------------\r
+reg [8:0]Hpos_in; // input capture postion\r
+reg L_Hsync_i;\r
+wire HP_in = ~L_Hsync_i & I_H_SYNC;\r
+always@(posedge I_CLK_1)\r
+begin\r
+ Hpos_in <= HP_in ? 0: Hpos_in + 1;\r
+ L_Hsync_i <= I_H_SYNC;\r
+end\r
+\r
+//---------------------------------------------------------------------------\r
+//output timming\r
+//---------------------------------------------------------------------------\r
+reg [8:0]Hpos_out;\r
+reg L_Hsync_o;\r
+wire HP_out = ~L_Hsync_o & I_H_SYNC;\r
+wire HP_ret = HP_out | (Hpos_out == H_COUNT-1);\r
+\r
+always@(posedge I_CLK_2)\r
+begin\r
+ Hpos_out <= HP_ret ? 0:Hpos_out + 1;\r
+ L_Hsync_o <= I_H_SYNC;\r
+end\r
+\r
+reg O_Hsync;\r
+always@(posedge I_CLK_2)\r
+begin\r
+ case(Hpos_out)\r
+ HS_POS :O_Hsync <= 1'b1;\r
+ HS_WIDTH:O_Hsync <= 1'b0;\r
+ default :;\r
+ endcase\r
+end\r
+\r
+//---------------------------------------------------------------------------\r
+// RGB capture(portA) & output(portB)\r
+//---------------------------------------------------------------------------\r
+wire [7:0]rgb_in = {I_R,I_G,I_B}; // RGB input\r
+wire [7:0]rgb_out; // RGB output\r
+\r
+`ifdef DEVICE_CYCLONE\r
+alt_ram_512_8_d double_scan_ram(\r
+\r
+.clock_a(I_CLK_1),\r
+.address_a(Hpos_in),\r
+.q_a(),\r
+.data_a(rgb_in),\r
+.wren_a(1'b1),\r
+.enable_a(1'b1),\r
+.aclr_a(1'b0),\r
+\r
+.clock_b(I_CLK_2),\r
+.address_b(Hpos_out),\r
+.q_b(rgb_out),\r
+.data_b(4'h0),\r
+.wren_b(1'b0),\r
+.enable_b(1'b1),\r
+.aclr_b(1'b0)\r
+\r
+);\r
+`endif\r
+`ifdef DEVICE_SPARTAN2E\r
+RAMB4_S8_S8 double_scan_ram (\r
+\r
+.CLKA(I_CLK_1),\r
+.ADDRA(Hpos_in),\r
+.DOA(),\r
+.DIA(rgb_in),\r
+.WEA(1'b1),\r
+.ENA(1'b1),\r
+.RSTA(1'b0),\r
+\r
+.CLKB(I_CLK_2),\r
+.ADDRB(Hpos_out),\r
+.DOB(rgb_out),\r
+.DIB(4'h0),\r
+.WEB(1'b0),\r
+.ENB(1'b1),\r
+.RSTB(1'b0)\r
+\r
+);\r
+`endif\r
+//---------------------------------------------------------------------------\r
+// vsync remake\r
+//\r
+// 1 HSYNC_IN delay & HSYNC pulse width = 4xHSYNC(in)\r
+//---------------------------------------------------------------------------\r
+\r
+reg [2:0]vs_cnt;\r
+reg O_Vsync;\r
+\r
+always @(posedge O_Hsync)\r
+begin\r
+ if(~I_V_SYNC)begin\r
+ vs_cnt <= VS_WIDTH-1;\r
+ end\r
+ else begin\r
+ if(vs_cnt==0) vs_cnt <= vs_cnt;\r
+ else vs_cnt <= vs_cnt-1;\r
+ end\r
+end\r
+always @(posedge O_Hsync)\r
+begin\r
+ case(vs_cnt)\r
+ VS_WIDTH-2 :O_Vsync <= 1;\r
+ 0 :O_Vsync <= 0;\r
+ endcase\r
+end\r
+//---------------------------------------------------------------------------\r
+// output\r
+//---------------------------------------------------------------------------\r
+\r
+assign O_R = {2'b00,rgb_out[7:5]}; \r
+assign O_G = {2'b00,rgb_out[4:2]};\r
+assign O_B = {3'b000,rgb_out[1:0]}; \r
+\r
+// converted H V SYNC\r
+assign O_H_SYNCn = ~O_Hsync;\r
+assign O_V_SYNCn = ~O_Vsync;\r
+\r
+endmodule\r
+\r
+`ifdef DEVICE_CYCLONE\r
+module alt_ram_512_8_d (\r
+ data_a,\r
+ wren_a,\r
+ address_a,\r
+ data_b,\r
+ address_b,\r
+ wren_b,\r
+ clock_a,\r
+ enable_a,\r
+ clock_b,\r
+ enable_b,\r
+ aclr_a,\r
+ aclr_b,\r
+ q_a,\r
+ q_b);\r
+\r
+ input [7:0] data_a;\r
+ input wren_a;\r
+ input [8:0] address_a;\r
+ input [7:0] data_b;\r
+ input [8:0] address_b;\r
+ input wren_b;\r
+ input clock_a;\r
+ input enable_a;\r
+ input clock_b;\r
+ input enable_b;\r
+ input aclr_a;\r
+ input aclr_b;\r
+ output [7:0] q_a;\r
+ output [7:0] q_b;\r
+\r
+ wire [7:0] sub_wire0;\r
+ wire [7:0] sub_wire1;\r
+ wire [7:0] q_a = sub_wire0[7:0];\r
+ wire [7:0] q_b = sub_wire1[7:0];\r
+\r
+ altsyncram altsyncram_component (\r
+ .clocken0 (enable_a),\r
+ .clocken1 (enable_b),\r
+ .wren_a (wren_a),\r
+ .aclr0 (aclr_a),\r
+ .clock0 (clock_a),\r
+ .wren_b (wren_b),\r
+ .aclr1 (aclr_b),\r
+ .clock1 (clock_b),\r
+ .address_a (address_a),\r
+ .address_b (address_b),\r
+ .data_a (data_a),\r
+ .data_b (data_b),\r
+ .q_a (sub_wire0),\r
+ .q_b (sub_wire1));\r
+ defparam\r
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",\r
+ altsyncram_component.width_a = 8,\r
+ altsyncram_component.widthad_a = 9,\r
+ altsyncram_component.numwords_a = 512,\r
+ altsyncram_component.width_b = 8,\r
+ altsyncram_component.widthad_b = 9,\r
+ altsyncram_component.numwords_b = 512,\r
+ altsyncram_component.lpm_type = "altsyncram",\r
+ altsyncram_component.width_byteena_a = 1,\r
+ altsyncram_component.width_byteena_b = 1,\r
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
+ altsyncram_component.outdata_aclr_a = "NONE",\r
+ altsyncram_component.outdata_reg_b = "UNREGISTERED",\r
+ altsyncram_component.indata_aclr_a = "CLEAR0",\r
+ altsyncram_component.wrcontrol_aclr_a = "CLEAR0",\r
+ altsyncram_component.address_aclr_a = "CLEAR0",\r
+ altsyncram_component.indata_reg_b = "CLOCK1",\r
+ altsyncram_component.address_reg_b = "CLOCK1",\r
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",\r
+ altsyncram_component.indata_aclr_b = "CLEAR1",\r
+ altsyncram_component.wrcontrol_aclr_b = "CLEAR1",\r
+ altsyncram_component.address_aclr_b = "CLEAR1",\r
+ altsyncram_component.outdata_aclr_b = "NONE",\r
+ altsyncram_component.ram_block_type = "M4K",\r
+ altsyncram_component.intended_device_family = "Stratix";\r
+\r
+\r
+endmodule\r
+`endif\r
--- /dev/null
+//===============================================================================\r
+// FPGA GALAXIAN VIDEO\r
+//\r
+// Version : 2.50\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+//\r
+// 2004- 4-30 galaxian modify by K.DEGAWA\r
+// 2004- 5- 6 first release.\r
+// 2004- 8-23 Improvement with T80-IP.\r
+// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
+//================================================================================\r
+//-----------------------------------------------------------------------------------------\r
+// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8], \r
+// 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H\r
+//-----------------------------------------------------------------------------------------\r
+// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] \r
+// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V \r
+//-----------------------------------------------------------------------------------------\r
+\r
+module mc_video(\r
+\r
+I_CLK_18M,\r
+I_CLK_12M,\r
+I_CLK_6M,\r
+I_H_CNT,\r
+I_V_CNT,\r
+I_H_FLIP,\r
+I_V_FLIP,\r
+I_V_BLn,\r
+I_C_BLn,\r
+\r
+I_A,\r
+I_OBJ_SUB_A,\r
+I_BD,\r
+I_OBJ_RAM_RQn,\r
+I_OBJ_RAM_RDn,\r
+I_OBJ_RAM_WRn,\r
+I_VID_RAM_RDn,\r
+I_VID_RAM_WRn,\r
+\r
+O_OBJ_ROM_A,\r
+I_OBJ_ROM_A_D,\r
+I_OBJ_ROM_B_D,\r
+\r
+O_C_BLnX,\r
+O_8HF,\r
+O_256HnX,\r
+O_1VF,\r
+O_MISSILEn,\r
+O_SHELLn,\r
+O_BD,\r
+O_VID,\r
+O_COL\r
+\r
+);\r
+\r
+input I_CLK_18M;\r
+input I_CLK_12M;\r
+input I_CLK_6M;\r
+input [8:0]I_H_CNT;\r
+input [7:0]I_V_CNT;\r
+input I_H_FLIP;\r
+input I_V_FLIP;\r
+input I_V_BLn;\r
+input I_C_BLn;\r
+\r
+input [9:0]I_A;\r
+input [7:0]I_BD;\r
+input [2:0]I_OBJ_SUB_A;\r
+input I_OBJ_RAM_RQn;\r
+input I_OBJ_RAM_RDn;\r
+input I_OBJ_RAM_WRn;\r
+input I_VID_RAM_RDn;\r
+input I_VID_RAM_WRn;\r
+\r
+output [10:0]O_OBJ_ROM_A;\r
+input [7:0]I_OBJ_ROM_A_D;\r
+input [7:0]I_OBJ_ROM_B_D;\r
+\r
+output O_C_BLnX;\r
+output O_8HF;\r
+output O_256HnX;\r
+output O_1VF;\r
+output O_MISSILEn;\r
+output O_SHELLn;\r
+\r
+output [7:0]O_BD;\r
+output [1:0]O_VID;\r
+output [2:0]O_COL;\r
+\r
+wire WB_LDn;\r
+wire WB_CNTRLDn;\r
+wire WB_CNTRCLRn;\r
+wire WB_COLLn;\r
+wire WB_VPLn;\r
+wire WB_OBJDATALn;\r
+wire WB_MLDn;\r
+wire WB_SLDn;\r
+wire W_3D;\r
+reg W_LDn;\r
+reg W_CNTRLDn;\r
+reg W_CNTRCLRn;\r
+reg W_COLLn;\r
+reg W_VPLn;\r
+reg W_OBJDATALn;\r
+reg W_MLDn;\r
+reg W_SLDn;\r
+\r
+always@(negedge I_CLK_12M)\r
+begin\r
+ W_LDn <= WB_LDn;\r
+ W_CNTRLDn <= WB_CNTRLDn;\r
+ W_CNTRCLRn <= WB_CNTRCLRn;\r
+ W_COLLn <= WB_COLLn;\r
+ W_VPLn <= WB_VPLn;\r
+ W_OBJDATALn <= WB_OBJDATALn;\r
+ W_MLDn <= WB_MLDn;\r
+ W_SLDn <= WB_SLDn;\r
+end\r
+\r
+mc_ld_pls LD_PLS(\r
+\r
+.I_CLK_6M(~I_CLK_6M),\r
+.I_H_CNT(I_H_CNT),\r
+.I_3D_DI(W_3D),\r
+\r
+.O_LDn(WB_LDn),\r
+.O_CNTRLDn(WB_CNTRLDn),\r
+.O_CNTRCLRn(WB_CNTRCLRn),\r
+.O_COLLn(WB_COLLn),\r
+.O_VPLn(WB_VPLn),\r
+.O_OBJDATALn(WB_OBJDATALn),\r
+.O_MLDn(WB_MLDn),\r
+.O_SLDn(WB_SLDn)\r
+\r
+);\r
+\r
+wire W_H_FLIP1 = ~I_H_CNT[8]&I_H_FLIP;\r
+\r
+wire [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};\r
+wire [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
+\r
+assign O_8HF = W_HF_CNT[3];\r
+assign O_1VF = W_VF_CNT[0];\r
+\r
+reg [7:0]W_OBJ_D;\r
+wire [3:0]W_6J_DA = {I_H_FLIP , W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
+wire [3:0]W_6J_DB = {W_OBJ_D[6],W_HF_CNT[3]&I_H_CNT[1], I_H_CNT[2],I_H_CNT[1]};\r
+wire [3:0]W_6J_Q = I_H_CNT[8] ? W_6J_DB:W_6J_DA;\r
+\r
+wire W_H_FLIP2 = W_6J_Q[3];\r
+// Prats 4F,5F\r
+wire [7:0]W_OBJ_RAM_AB = {1'b0,I_H_CNT[8],W_6J_Q[2],W_HF_CNT[6:4],W_6J_Q[1:0]};\r
+wire [7:0]W_OBJ_RAM_A = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;\r
+\r
+wire [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
+\r
+reg [7:0]W_H_POSI;\r
+always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;\r
+\r
+mc_obj_ram OBJ_RAM(\r
+\r
+.I_CLKA(I_CLK_12M),\r
+.I_ADDRA(I_A[7:0]),\r
+.I_WEA(~I_OBJ_RAM_WRn),\r
+.I_CEA(~I_OBJ_RAM_RQn),\r
+.I_DA(I_BD),\r
+.O_DA(W_OBJ_RAM_DOA),\r
+\r
+.I_CLKB(I_CLK_12M),\r
+.I_ADDRB(W_OBJ_RAM_AB),\r
+.I_WEB(1'b0),\r
+.I_CEB(1'b1),\r
+.I_DB(8'h00),\r
+.O_DB(W_OBJ_RAM_DOB)\r
+\r
+);\r
+\r
+wire [7:0]W_OBJ_RAM_D = I_OBJ_RAM_RDn ? 8'h00: W_OBJ_RAM_DOA;\r
+// Prats 4L\r
+always@(posedge W_OBJDATALn) W_OBJ_D <= W_H_POSI; \r
+// Prats 4,5N\r
+\r
+wire [8:0]W_45N_Q = W_VF_CNT[7:0] + W_H_POSI ;\r
+assign W_3D = ~(&W_45N_Q[7:0]); \r
+\r
+reg [7:0]W_2M_Q;\r
+always@(posedge W_VPLn or negedge I_V_BLn)\r
+begin\r
+ if(I_V_BLn==1'b0)\r
+ W_2M_Q <= 0;\r
+ else\r
+ W_2M_Q <= W_45N_Q[7:0];\r
+end\r
+\r
+wire W_2N = I_H_CNT[8]&W_OBJ_D[7];\r
+wire [3:0]W_1M = W_2M_Q[3:0]^{W_2N,W_2N,W_2N,W_2N};\r
+\r
+wire W_VID_RAM_CSn = I_VID_RAM_RDn & I_VID_RAM_WRn;\r
+\r
+wire [7:0]W_VID_RAM_DI = I_VID_RAM_WRn ? 8'h00 : I_BD ;\r
+wire [7:0]W_VID_RAM_DOA;\r
+\r
+wire [11:0]W_VID_RAM_AA = {~(&W_2M_Q[7:4]),W_VID_RAM_CSn, 10'h00 /*I_A[9:0]*/};\r
+wire [11:0]W_VID_RAM_AB = { 1'b0, 1'b0,W_2M_Q[7:4],W_1M[3],W_HF_CNT[7:3]};\r
+\r
+wire [11:0]W_VID_RAM_A = I_C_BLn ? W_VID_RAM_AB:W_VID_RAM_AA;\r
+\r
+wire [7:0]W_VID_RAM_D = I_VID_RAM_RDn ? 8'h00 :W_VID_RAM_DOA;\r
+\r
+wire [7:0]W_VID_RAM_DOB;\r
+\r
+mc_vid_ram VID_RAM(\r
+\r
+.I_CLKA(I_CLK_12M),\r
+.I_ADDRA(I_A[9:0]),\r
+.I_DA(W_VID_RAM_DI),\r
+.I_WEA(~I_VID_RAM_WRn),\r
+.I_CEA(~W_VID_RAM_CSn),\r
+.O_DA(W_VID_RAM_DOA),\r
+\r
+.I_CLKB(I_CLK_12M),\r
+.I_ADDRB(W_VID_RAM_A[9:0]),\r
+.I_DB(8'h00),\r
+.I_WEB(1'b0),\r
+.I_CEB(1'b1),\r
+.O_DB(W_VID_RAM_DOB)\r
+\r
+);\r
+//-- VIDEO DATA OUTPUT --------------\r
+assign O_BD = W_OBJ_RAM_D | W_VID_RAM_D;\r
+\r
+wire W_SRLD = ~(W_LDn | W_VID_RAM_A[11]);\r
+\r
+wire [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};\r
+\r
+wire [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
+\r
+assign O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
+\r
+wire [7:0]W_1K_D = I_OBJ_ROM_A_D;\r
+wire [7:0]W_1H_D = I_OBJ_ROM_B_D;\r
+\r
+//---------------------------------------------------------------------------------\r
+wire W_2L_Qa,W_2K_Qd;\r
+wire W_2J_Qa,W_2H_Qd;\r
+wire W_H_FLIP2X;\r
+\r
+wire [3:0]W_3L_A = {W_2J_Qa,W_2L_Qa, 1'b1,W_SRLD};\r
+wire [3:0]W_3L_B = {W_2H_Qd,W_2K_Qd,W_SRLD, 1'b1}; \r
+wire [3:0]W_3L_Y = W_H_FLIP2X ? W_3L_B: W_3L_A; // [3]=RAW1,[2]=RAW0\r
+\r
+wire W_RAW0 = W_3L_Y[2];\r
+wire W_RAW1 = W_3L_Y[3];\r
+\r
+wire W_SRCLK = I_CLK_6M;\r
+//------ PARTS 2KL ---------------------------------------------- \r
+wire [1:0]C_2KL = W_3L_Y[1:0];\r
+wire [7:0]I_2KL = W_1K_D;\r
+reg [7:0]reg_2KL;\r
+\r
+assign W_2L_Qa = reg_2KL[7];\r
+assign W_2K_Qd = reg_2KL[0];\r
+always@(posedge W_SRCLK)\r
+begin\r
+ case(C_2KL)\r
+ 2'b00: reg_2KL <= reg_2KL;\r
+ 2'b10: reg_2KL <= {reg_2KL[6:0],1'b0};\r
+ 2'b01: reg_2KL <= {1'b0,reg_2KL[7:1]};\r
+ 2'b11: reg_2KL <= I_2KL;\r
+ endcase\r
+end\r
+//------ PARTS 2HJ ---------------------------------------------- \r
+wire [1:0]C_2HJ = W_3L_Y[1:0];\r
+wire [7:0]I_2HJ = W_1H_D;\r
+reg [7:0]reg_2HJ;\r
+\r
+assign W_2J_Qa = reg_2HJ[7];\r
+assign W_2H_Qd = reg_2HJ[0];\r
+always@(posedge W_SRCLK)\r
+begin\r
+ case(C_2HJ)\r
+ 2'b00: reg_2HJ <= reg_2HJ;\r
+ 2'b10: reg_2HJ <= {reg_2HJ[6:0],1'b0};\r
+ 2'b01: reg_2HJ <= {1'b0,reg_2HJ[7:1]};\r
+ 2'b11: reg_2HJ <= I_2HJ;\r
+ endcase\r
+end\r
+\r
+//----- SHT2 -----------------------------------------------------\r
+// Prats 6K\r
+reg [2:0]W_6K_Q;\r
+always@(posedge W_COLLn) W_6K_Q <= W_H_POSI[2:0];\r
+\r
+// Prats 6P\r
+reg [6:0]W_6P_Q;\r
+always@(posedge I_CLK_6M)\r
+begin\r
+ if(W_LDn==1'b0) W_6P_Q <= {W_H_FLIP2,W_H_FLIP1,I_C_BLn,~I_H_CNT[8],W_6K_Q[2:0]};\r
+ else W_6P_Q <= W_6P_Q;\r
+end\r
+\r
+assign W_H_FLIP2X = W_6P_Q[6];\r
+wire W_H_FLIP1X = W_6P_Q[5];\r
+wire W_C_BLnX = W_6P_Q[4];\r
+wire W_256HnX = W_6P_Q[3];\r
+wire [2:0]W_CD = W_6P_Q[2:0];\r
+\r
+assign O_256HnX = W_256HnX;\r
+assign O_C_BLnX = W_C_BLnX;\r
+\r
+wire W_45T_CLR = W_CNTRCLRn | W_256HnX ;\r
+reg [7:0]W_45T_Q;\r
+\r
+always@(posedge I_CLK_6M)\r
+begin\r
+ if(W_45T_CLR==1'b0)\r
+ W_45T_Q <= 0;\r
+ else if(W_CNTRLDn==1'b0)\r
+ W_45T_Q <= W_H_POSI;\r
+ else\r
+ W_45T_Q <= W_45T_Q + 1;\r
+end\r
+\r
+wire [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
+wire W_LRAM_WE = ~I_CLK_6M;\r
+\r
+wire [4:0]W_LRAM_DI;\r
+wire [4:0]W_LRAM_DO;\r
+\r
+reg [1:0]W_RV;\r
+reg [2:0]W_RC;\r
+wire W_1U_CLK = ~I_CLK_6M;\r
+\r
+always@(posedge W_1U_CLK)\r
+begin\r
+ W_RV <= W_LRAM_DO[1:0]; \r
+ W_RC <= W_LRAM_DO[4:2];\r
+end\r
+\r
+wire W_LRAM_AND = ~(~((W_LRAM_A[4]|W_LRAM_A[5])|(W_LRAM_A[6]|W_LRAM_A[7]))|W_256HnX );\r
+wire W_RAW_OR = W_RAW0 | W_RAW1 ;\r
+\r
+wire [1:0]W_VID;\r
+wire [2:0]W_COL;\r
+\r
+assign W_VID[0] = ~(~(W_RAW0&W_RV[1])&W_RV[0]);\r
+assign W_VID[1] = ~(~(W_RAW1&W_RV[0])&W_RV[1]);\r
+assign W_COL[0] = ~(~(W_RAW_OR&W_CD[0]&W_RC[1]&W_RC[2])&W_RC[0]);\r
+assign W_COL[1] = ~(~(W_RAW_OR&W_CD[1]&W_RC[2]&W_RC[0])&W_RC[1]);\r
+assign W_COL[2] = ~(~(W_RAW_OR&W_CD[2]&W_RC[0]&W_RC[1])&W_RC[2]);\r
+\r
+assign O_VID = W_VID;\r
+assign O_COL = W_COL;\r
+\r
+assign W_LRAM_DI[0] = W_LRAM_AND&W_VID[0];\r
+assign W_LRAM_DI[1] = W_LRAM_AND&W_VID[1]; \r
+assign W_LRAM_DI[2] = W_LRAM_AND&W_COL[0];\r
+assign W_LRAM_DI[3] = W_LRAM_AND&W_COL[1];\r
+assign W_LRAM_DI[4] = W_LRAM_AND&W_COL[2];\r
+\r
+mc_lram LRAM(\r
+\r
+.I_CLK(I_CLK_18M),\r
+.I_ADDR(W_LRAM_A),\r
+.I_WE(W_LRAM_WE),\r
+.I_D(W_LRAM_DI),\r
+.O_Dn(W_LRAM_DO)\r
+\r
+);\r
+\r
+mc_missile MISSILE(\r
+\r
+.I_CLK_18M(I_CLK_18M),\r
+.I_CLK_6M(I_CLK_6M),\r
+.I_C_BLn_X(W_C_BLnX),\r
+.I_MLDn(W_MLDn),\r
+.I_SLDn(W_SLDn),\r
+.I_HPOS(W_H_POSI),\r
+\r
+.O_MISSILEn(O_MISSILEn),\r
+.O_SHELLn(O_SHELLn)\r
+\r
+);\r
+\r
+endmodule\r
+\r
+\r
--- /dev/null
+//-------------------------------------------------------------------\r
+// \r
+// PLAYSTATION CONTROLLER(DUALSHOCK TYPE) INTERFACE TOP \r
+// \r
+// Version : 2.00 \r
+// \r
+// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved \r
+// \r
+// Important ! \r
+// \r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program. \r
+// You can use this under your own risk.\r
+// \r
+// 2003.10.30 It is optimized for the FPGA game. \r
+// It was made an analog mode fixation.(Dualshock)\r
+// by K Degawa \r
+// \r
+//-------------------------------------------------------------------\r
+//--------- SIMULATION ---------------------------------------------- \r
+//`define SIMULATION_1 \r
+\r
+`ifdef SIMULATION_1\r
+`define Timer_siz 18 \r
+`else\r
+`define Timer_siz 12\r
+`endif\r
+//-------------------------------------------------------------------\r
+\r
+`timescale 100ps/10ps \r
+`include "src/mc_conf.v"\r
+\r
+module psPAD_top(\r
+\r
+I_CLK250K, // MAIN CLK 250KHz\r
+I_RSTn, // MAIN RESET\r
+O_psCLK, // psCLK CLK OUT\r
+O_psSEL, // psSEL OUT \r
+O_psTXD, // psTXD OUT\r
+I_psRXD, // psRXD IN\r
+O_RXD_1, // RX DATA 1 (8bit)\r
+O_RXD_2, // RX DATA 2 (8bit)\r
+O_RXD_3, // RX DATA 3 (8bit)\r
+O_RXD_4, // RX DATA 4 (8bit)\r
+O_RXD_5, // RX DATA 5 (8bit)\r
+O_RXD_6, // RX DATA 6 (8bit) \r
+I_CONF_SW, // \r
+I_MODE_SW, // \r
+I_MODE_EN, // \r
+I_VIB_SW, // Vibration SW VIB_SW[0] Small Moter OFF 0:ON 1:\r
+ // VIB_SW[1] Bic Moter OFF 0:ON 1(Dualshook Only)\r
+I_VIB_DAT // Vibration(Bic Moter)Data 8'H00-8'HFF (Dualshook Only)\r
+\r
+);\r
+\r
+input I_CLK250K,I_RSTn;\r
+input I_CONF_SW;\r
+input I_MODE_SW,I_MODE_EN;\r
+input [1:0]I_VIB_SW;\r
+input [7:0]I_VIB_DAT;\r
+input I_psRXD;\r
+output O_psCLK;\r
+output O_psSEL;\r
+output O_psTXD;\r
+output [7:0]O_RXD_1;\r
+output [7:0]O_RXD_2;\r
+output [7:0]O_RXD_3;\r
+output [7:0]O_RXD_4;\r
+output [7:0]O_RXD_5;\r
+output [7:0]O_RXD_6;\r
+\r
+wire W_scan_seq_pls;\r
+wire W_type;\r
+wire [3:0]W_byte_cnt;\r
+wire W_RXWT;\r
+wire W_TXWT;\r
+wire W_TXSET;\r
+wire W_TXEN;\r
+wire [7:0]W_TXD_DAT;\r
+wire [7:0]W_RXD_DAT;\r
+wire W_conf_ent;\r
+\r
+ps_pls_gan pls(\r
+\r
+.I_CLK(I_CLK250K),\r
+.I_RSTn(I_RSTn),\r
+.I_TYPE(W_type), // DEGITAL PAD 0: ANALOG PAD 1:\r
+\r
+.O_SCAN_SEQ_PLS(W_scan_seq_pls),\r
+.O_RXWT(W_RXWT),\r
+.O_TXWT(W_TXWT),\r
+.O_TXSET(W_TXSET),\r
+.O_TXEN(W_TXEN),\r
+.O_psCLK(O_psCLK),\r
+.O_psSEL(O_psSEL),\r
+.O_byte_cnt(W_byte_cnt),\r
+\r
+//.Timer(O_Timer)\r
+.Timer()\r
+\r
+); \r
+\r
+`ifdef Dualshock\r
+txd_commnd cmd(\r
+\r
+.I_CLK(W_TXSET),\r
+.I_RSTn(I_RSTn),\r
+.I_BYTE_CNT(W_byte_cnt),\r
+.I_MODE({I_CONF_SW,~I_MODE_EN,I_MODE_SW}),\r
+.I_VIB_SW(I_VIB_SW),\r
+.I_VIB_DAT(I_VIB_DAT),\r
+.I_RXD_DAT(W_RXD_DAT),\r
+.O_TXD_DAT(W_TXD_DAT),\r
+.O_TYPE(W_type),\r
+.O_CONF_ENT(W_conf_ent)\r
+\r
+);\r
+\r
+`else\r
+txd_commnd_EZ cmd(\r
+\r
+.I_CLK(W_TXSET),\r
+.I_RSTn(I_RSTn),\r
+.I_BYTE_CNT(W_byte_cnt),\r
+.I_MODE(),\r
+.I_VIB_SW(I_VIB_SW),\r
+.I_VIB_DAT(),\r
+.I_RXD_DAT(),\r
+.O_TXD_DAT(W_TXD_DAT),\r
+.O_TYPE(W_type),\r
+.O_CONF_ENT(W_conf_ent)\r
+\r
+);\r
+\r
+`endif\r
+\r
+ps_txd txd(\r
+\r
+.I_CLK(I_CLK250K),\r
+.I_RSTn(I_RSTn),\r
+.I_WT(W_TXWT),\r
+.I_EN(W_TXEN),\r
+.I_TXD_DAT(W_TXD_DAT),\r
+.O_psTXD(O_psTXD)\r
+\r
+);\r
+\r
+ps_rxd rxd(\r
+\r
+.I_CLK(O_psCLK),\r
+.I_RSTn(I_RSTn), \r
+.I_WT(W_RXWT),\r
+.I_psRXD(I_psRXD),\r
+.O_RXD_DAT(W_RXD_DAT)\r
+\r
+);\r
+\r
+//---------- RXD DATA DEC ----------------------------------------\r
+reg [7:0]O_RXD_1;\r
+reg [7:0]O_RXD_2;\r
+reg [7:0]O_RXD_3;\r
+reg [7:0]O_RXD_4;\r
+reg [7:0]O_RXD_5;\r
+reg [7:0]O_RXD_6;\r
+\r
+reg W_rxd_mask;\r
+always@(posedge W_scan_seq_pls) \r
+ W_rxd_mask <= ~W_conf_ent;\r
+\r
+always@(negedge W_RXWT)\r
+begin\r
+ if(W_rxd_mask)begin\r
+ case(W_byte_cnt)\r
+ 3: O_RXD_1 <= W_RXD_DAT;\r
+ 4: O_RXD_2 <= W_RXD_DAT;\r
+ 5: O_RXD_3 <= W_RXD_DAT;\r
+ 6: O_RXD_4 <= W_RXD_DAT;\r
+ 7: O_RXD_5 <= W_RXD_DAT;\r
+ 8: O_RXD_6 <= W_RXD_DAT;\r
+ default:;\r
+ endcase\r
+ end\r
+end\r
+\r
+endmodule\r
+\r
+module txd_commnd_EZ(\r
+\r
+I_CLK,\r
+I_RSTn,\r
+I_BYTE_CNT,\r
+I_MODE,\r
+I_VIB_SW,\r
+I_VIB_DAT,\r
+I_RXD_DAT,\r
+O_TXD_DAT,\r
+O_TYPE,\r
+O_CONF_ENT\r
+\r
+);\r
+\r
+input I_CLK,I_RSTn;\r
+input [3:0]I_BYTE_CNT;\r
+input [2:0]I_MODE;\r
+input [1:0]I_VIB_SW;\r
+input [7:0]I_VIB_DAT;\r
+input [7:0]I_RXD_DAT;\r
+output [7:0]O_TXD_DAT;\r
+output O_TYPE;\r
+output O_CONF_ENT;\r
+\r
+reg [7:0]O_TXD_DAT;\r
+\r
+assign O_TYPE = 1'b1;\r
+assign O_CONF_ENT = 1'b0;\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin\r
+ if(! I_RSTn)begin\r
+ O_TXD_DAT <= 8'h00;\r
+ end\r
+ else begin\r
+ case(I_BYTE_CNT)\r
+ 0:O_TXD_DAT <= 8'h01;\r
+ 1:O_TXD_DAT <= 8'h42;\r
+ 3:begin\r
+ if(I_VIB_SW) O_TXD_DAT <= 8'h40;\r
+ else O_TXD_DAT <= 8'h00;\r
+ end\r
+ 4:begin\r
+ if(I_VIB_SW) O_TXD_DAT <= 8'h01;\r
+ else O_TXD_DAT <= 8'h00;\r
+ end\r
+ default: O_TXD_DAT <= 8'h00;\r
+ endcase\r
+ end\r
+end\r
+\r
+endmodule\r
+\r
+module txd_commnd(\r
+\r
+\r
+I_CLK,\r
+I_RSTn,\r
+I_BYTE_CNT,\r
+I_MODE,\r
+I_VIB_SW,\r
+I_VIB_DAT,\r
+I_RXD_DAT,\r
+O_TXD_DAT,\r
+O_TYPE,\r
+O_CONF_ENT\r
+\r
+);\r
+\r
+input I_CLK,I_RSTn;\r
+input [3:0]I_BYTE_CNT;\r
+input [2:0]I_MODE;\r
+input [1:0]I_VIB_SW;\r
+input [7:0]I_VIB_DAT;\r
+input [7:0]I_RXD_DAT;\r
+output [7:0]O_TXD_DAT;\r
+output O_TYPE;\r
+output O_CONF_ENT;\r
+\r
+reg [7:0]O_TXD_DAT;\r
+reg [2:0]conf_state;\r
+reg conf_entry;\r
+reg conf_done;\r
+reg pad_status;\r
+reg pad_id;\r
+\r
+assign O_TYPE = pad_id;\r
+assign O_CONF_ENT = conf_entry;\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin\r
+ if(! I_RSTn) pad_id <= 1'b0; \r
+ else begin\r
+ if(I_BYTE_CNT==2)begin\r
+ case(I_RXD_DAT) //------ GET TYPE(Byte_SEQ)\r
+ 8'h23: pad_id <= 1'b1;\r
+ 8'h41: pad_id <= 1'b0;\r
+ 8'h53: pad_id <= 1'b1;\r
+ 8'h73: pad_id <= 1'b1;\r
+ 8'hE3: pad_id <= 1'b1;\r
+ 8'hF3: pad_id <= 1'b1;\r
+ default: pad_id <= 1'b0;\r
+ endcase\r
+ end\r
+ end\r
+end\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin\r
+ if(! I_RSTn)begin\r
+ O_TXD_DAT <= 8'h00;\r
+ conf_entry <= 1'b0;\r
+ conf_done <= 1'b1;\r
+ conf_state <= 0;\r
+ pad_status <= 0; \r
+ end\r
+ else begin\r
+//---------- nomal mode --------------------------------------------------------\r
+//----------------- read_data_and_vibrate_ex 01,42,00,WW,PP(,00,00,00,00)\r
+// --,ID,SS,XX,XX(,XX,XX,XX,XX)\r
+ if(~conf_entry)begin\r
+ case(I_BYTE_CNT)\r
+ 0:O_TXD_DAT <= 8'h01;\r
+ 1:O_TXD_DAT <= 8'h42;\r
+ 3:begin\r
+ if(pad_status)begin\r
+ if(I_VIB_SW[0]) O_TXD_DAT <= 8'h01;\r
+ else O_TXD_DAT <= 8'h00;\r
+ end\r
+ else begin\r
+ if(I_VIB_SW[0]|I_VIB_SW[1]) O_TXD_DAT <= 8'h40;\r
+ else O_TXD_DAT <= 8'h00; \r
+ end\r
+ end\r
+ 4:begin\r
+ if(pad_status)begin\r
+ if(I_VIB_SW[1]) O_TXD_DAT <= I_VIB_DAT;\r
+ else O_TXD_DAT <= 8'h00;\r
+ end\r
+ else begin\r
+ if(I_VIB_SW[0]|I_VIB_SW[1]) O_TXD_DAT <= 8'h01;\r
+ else O_TXD_DAT <= 8'h00; \r
+ end\r
+ if(pad_id==0)begin\r
+ if(conf_state == 0)\r
+ conf_entry <= 1'b1;\r
+ end\r
+ end\r
+ 8:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ if(pad_id==1)begin\r
+ if(conf_state == 0)\r
+ conf_entry <= 1'b1;\r
+ end\r
+ end \r
+ default: O_TXD_DAT <= 8'h00;\r
+ endcase\r
+ end\r
+//---------- confg mode --------------------------------------------------------\r
+ else begin\r
+ case(conf_state)\r
+ //-------- config_mode_enter (43): 01,43,00,01,00(,00 x 4 or XX x 16)\r
+ // --,ID,SS,XX,XX(,XX x 4 or XX x 16) \r
+ 0:begin\r
+ case(I_BYTE_CNT)\r
+ 0:begin\r
+ O_TXD_DAT <= 8'h01;\r
+ conf_done <= 1'b0;\r
+ end\r
+ 1:O_TXD_DAT <= 8'h43;\r
+ 3:O_TXD_DAT <= 8'h01;\r
+ 4:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ if(pad_id==0)begin\r
+ conf_state <= 1; \r
+ end\r
+ end\r
+ 8:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ if(pad_id==1)begin\r
+ conf_state <= 1; \r
+ end\r
+ end \r
+ default:O_TXD_DAT <= 8'h00;\r
+ endcase\r
+ end\r
+ //-------- set_mode_and_lock (44): 01,44,00,XX,YY,00,00,00,00\r
+ // \r
+ 1:begin\r
+ case(I_BYTE_CNT)\r
+ 0:O_TXD_DAT <= 8'h01;\r
+ 1:O_TXD_DAT <= 8'h44;\r
+ 2:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ if(I_RXD_DAT == 8'hF3)begin\r
+ conf_done <= 1'b0;\r
+ pad_status <= 1'b1;\r
+ end\r
+ else begin\r
+ conf_done <= 1'b1;\r
+ pad_status <= 1'b0;\r
+ end\r
+ end\r
+ 3:O_TXD_DAT <= 8'h01;\r
+ 4:begin\r
+ O_TXD_DAT <= 8'h03;\r
+ if(pad_id==0 && conf_done==1'b1)begin\r
+ conf_state <= 7;\r
+ conf_entry <= 1'b0;\r
+ end\r
+ end\r
+ 8:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ conf_state <= 3;\r
+ if(pad_id==1 && conf_done==1'b1)begin\r
+ conf_state <= 7;\r
+ conf_entry <= 1'b0;\r
+ end \r
+ end \r
+ default:O_TXD_DAT <= 8'h00;\r
+ endcase\r
+ end\r
+ //-------- query_model_and_mode (45): 01,45,00,5A,5A,5A,5A,5A,5A\r
+ // FF,F3,5A,TT,02,MM,VV,01,00\r
+/*\r
+ 1:begin\r
+ case(I_BYTE_CNT)\r
+ 0:O_TXD_DAT <= 8'h01;\r
+ 1:O_TXD_DAT <= 8'h45;\r
+ 2:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ conf_done <= (I_RXD_DAT == 8'hF3)? 1'b0:1'b1;\r
+ end\r
+ 4:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ if(I_RXD_DAT==8'h01 || I_RXD_DAT==8'h03) pad_status <= 1;\r
+ if(pad_id==0 && conf_done==1'b1)begin\r
+ conf_state <= 7;\r
+ conf_entry <= 1'b0;\r
+ end\r
+ end\r
+ 8:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ conf_state <= 2;\r
+ if(pad_id==1 && conf_done==1'b1)begin\r
+ conf_state <= 7;\r
+ conf_entry <= 1'b0;\r
+ end \r
+ end \r
+ default:O_TXD_DAT <= 8'h00;\r
+ endcase\r
+ end\r
+ //-------- set_mode_and_lock (44): 01,44,00,XX,YY,00,00,00,00\r
+ // --,F3,5A,00,00,00,00,00,00\r
+ 2:begin\r
+ case(I_BYTE_CNT)\r
+ 0:O_TXD_DAT <= 8'h01;\r
+ 1:O_TXD_DAT <= 8'h44;\r
+ 3:O_TXD_DAT <= 8'h01;\r
+ 4:O_TXD_DAT <= 8'h03;\r
+ 8:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ conf_state<= 3;\r
+ end\r
+ default:O_TXD_DAT <= 8'h00;\r
+ endcase\r
+ end\r
+*/\r
+ //-------- vibration_enable (4D): 01,4D,00,00,01,FF,FF,FF,FF\r
+ // --,F3,5A,XX,YY,FF,FF,FF,FF\r
+ 3:begin\r
+ case(I_BYTE_CNT)\r
+ 0:O_TXD_DAT <= 8'h01;\r
+ 1:O_TXD_DAT <= 8'h4D;\r
+ 2,3:O_TXD_DAT <= 8'h00;\r
+ 4:O_TXD_DAT <= 8'h01;\r
+ 8:begin\r
+ O_TXD_DAT <= 8'hFF; \r
+ conf_state<= 6;\r
+ end\r
+ default:O_TXD_DAT <= 8'hFF;\r
+ endcase\r
+ end\r
+ //-------- config_mode_exit (43): 01,43,00,00,00,00,00,00,00\r
+ // --,F3,5A,00,00,00,00,00,00\r
+ 6:begin\r
+ case(I_BYTE_CNT)\r
+ 0:O_TXD_DAT <= 8'h01;\r
+ 1:O_TXD_DAT <= 8'h43;\r
+ 2,3:O_TXD_DAT <= 8'h00;\r
+ 8:begin\r
+ O_TXD_DAT <= 8'h00;\r
+ conf_state<= 7;\r
+ conf_entry<= 1'b0;\r
+ conf_done <= 1'b1; \r
+ end\r
+ default:O_TXD_DAT <= 8'h00;\r
+ endcase\r
+ end\r
+ default:;\r
+ endcase\r
+ end\r
+ end\r
+end\r
+\r
+endmodule\r
+\r
+module ps_pls_gan(\r
+\r
+I_CLK,\r
+I_RSTn,\r
+I_TYPE,\r
+\r
+O_SCAN_SEQ_PLS,\r
+O_RXWT,\r
+O_TXWT,\r
+O_TXSET,\r
+O_TXEN,\r
+O_psCLK,\r
+O_psSEL,\r
+O_byte_cnt,\r
+\r
+Timer\r
+\r
+);\r
+\r
+parameter Timer_size = `Timer_siz;\r
+\r
+input I_CLK,I_RSTn;\r
+input I_TYPE;\r
+output O_SCAN_SEQ_PLS;\r
+output O_RXWT;\r
+output O_TXWT;\r
+output O_TXSET;\r
+output O_TXEN;\r
+output O_psCLK;\r
+output O_psSEL;\r
+output [3:0]O_byte_cnt;\r
+\r
+output [Timer_size-1:0]Timer;\r
+reg [Timer_size-1:0]Timer;\r
+\r
+reg O_SCAN_SEQ_PLS;\r
+reg RXWT;\r
+reg TXWT;\r
+reg TXSET;\r
+reg psCLK_gate;\r
+reg psSEL;\r
+reg [3:0]O_byte_cnt;\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin\r
+ if(! I_RSTn) Timer <= 0;\r
+ else Timer <= Timer+1;\r
+end\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin\r
+ if(! I_RSTn) \r
+ O_SCAN_SEQ_PLS <= 0;\r
+ else begin\r
+ if(Timer == 0) O_SCAN_SEQ_PLS <= 1; \r
+ else O_SCAN_SEQ_PLS <= 0; \r
+ end\r
+end\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin\r
+ if(! I_RSTn)\r
+ begin\r
+ psCLK_gate <= 1;\r
+ RXWT <= 0;\r
+ TXWT <= 0;\r
+ TXSET <= 0;\r
+ end\r
+ else begin\r
+ case(Timer[4:0])\r
+ 6: TXSET <= 1;\r
+ 8: TXSET <= 0;\r
+ 9: TXWT <= 1;\r
+ 11: TXWT <= 0;\r
+ 12: psCLK_gate <= 0;\r
+ 20: psCLK_gate <= 1;\r
+ 21: RXWT <= 1;\r
+ 23: RXWT <= 0;\r
+ default:;\r
+ endcase\r
+ end\r
+end\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin \r
+ if(! I_RSTn)\r
+ psSEL <= 1;\r
+ else begin \r
+ if(O_SCAN_SEQ_PLS == 1)\r
+ psSEL <= 0;\r
+ else if((I_TYPE == 0)&&(Timer == 158))\r
+ psSEL <= 1;\r
+ else if((I_TYPE == 1)&&(Timer == 286))\r
+ psSEL <= 1;\r
+ end\r
+end\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+begin \r
+ if(! I_RSTn)\r
+ O_byte_cnt <= 0;\r
+ else begin\r
+ if( O_SCAN_SEQ_PLS == 1)\r
+ O_byte_cnt <= 0;\r
+ else begin \r
+ if( Timer[4:0] == 5'b11111)begin\r
+ if(I_TYPE == 0 && O_byte_cnt == 5)\r
+ O_byte_cnt <= O_byte_cnt;\r
+ else if(I_TYPE == 1 && O_byte_cnt == 9)\r
+ O_byte_cnt <= O_byte_cnt;\r
+ else\r
+ O_byte_cnt <= O_byte_cnt+1;\r
+ end \r
+ end\r
+ end\r
+end\r
+\r
+assign O_psCLK = psCLK_gate | I_CLK | psSEL;\r
+assign O_psSEL = psSEL;\r
+assign O_RXWT = ~psSEL&RXWT;\r
+assign O_TXSET = ~psSEL&TXSET;\r
+assign O_TXWT = ~psSEL&TXWT;\r
+assign O_TXEN = ~psSEL&(~psCLK_gate);\r
+\r
+endmodule\r
+\r
+module ps_rxd(\r
+\r
+I_CLK,\r
+I_RSTn, \r
+I_WT,\r
+I_psRXD,\r
+O_RXD_DAT\r
+\r
+);\r
+\r
+input I_CLK,I_RSTn,I_WT;\r
+input I_psRXD;\r
+output [7:0]O_RXD_DAT;\r
+reg [7:0]O_RXD_DAT;\r
+reg [7:0]sp;\r
+\r
+always@(posedge I_CLK or negedge I_RSTn)\r
+ if(! I_RSTn) sp <= 1;\r
+ else sp <= { I_psRXD, sp[7:1]};\r
+always@(posedge I_WT or negedge I_RSTn)\r
+ if(! I_RSTn) O_RXD_DAT <= 1;\r
+ else O_RXD_DAT <= sp;\r
+\r
+endmodule\r
+\r
+module ps_txd(\r
+\r
+I_CLK,\r
+I_RSTn,\r
+I_WT,\r
+I_EN,\r
+I_TXD_DAT,\r
+O_psTXD\r
+\r
+);\r
+\r
+input I_CLK,I_RSTn;\r
+input I_WT,I_EN;\r
+input [7:0]I_TXD_DAT;\r
+output O_psTXD;\r
+reg O_psTXD;\r
+reg [7:0]ps;\r
+\r
+always@(negedge I_CLK or negedge I_RSTn)\r
+begin\r
+ if(! I_RSTn)begin \r
+ O_psTXD <= 1;\r
+ ps <= 0;\r
+ end\r
+ else begin\r
+ if(I_WT)\r
+ ps <= I_TXD_DAT;\r
+ else begin\r
+ if(I_EN)begin\r
+ O_psTXD <= ps[0];\r
+ ps <= {1'b1, ps[7:1]};\r
+ end\r
+ else begin\r
+ O_psTXD <= 1'd1;\r
+ ps <= ps;\r
+ end\r
+ end\r
+ end \r
+end\r
+\r
+endmodule
\ No newline at end of file
--- /dev/null
+module galaxian_roms(
+I_CLK_18432M,
+I_CLK_12M,
+I_ADDR,
+O_DATA
+);
+
+input I_CLK_12M;
+input I_CLK_18432M;
+input [18:0]I_ADDR;
+output [7:0]O_DATA;
+
+//CPU-Roms
+wire [7:0]U_ROM_D;
+reg [10:0]U_ROM_A;
+
+GALAXIAN_U U_ROM(
+.CLK(I_CLK_12M),
+.ADDR(U_ROM_A),
+.DATA(U_ROM_D),
+.ENA(1'b1)
+);
+
+wire [7:0]V_ROM_D;
+reg [10:0]V_ROM_A;
+
+GALAXIAN_V V_ROM(
+.CLK(I_CLK_12M),
+.ADDR(V_ROM_A),
+.DATA(V_ROM_D),
+.ENA(1'b1)
+);
+
+wire [7:0]W_ROM_D;
+reg [10:0]W_ROM_A;
+
+GALAXIAN_W W_ROM(
+.CLK(I_CLK_12M),
+.ADDR(W_ROM_A),
+.DATA(W_ROM_D),
+.ENA(1'b1)
+);
+
+wire [7:0]Y_ROM_D;
+reg [10:0]Y_ROM_A;
+
+GALAXIAN_Y Y_ROM(
+.CLK(YB_CLK_12M),
+.ADDR(Y_ROM_A),
+.DATA(Y_ROM_D),
+.ENA(1'b1)
+);
+
+//7L CPU-Rom
+wire [7:0]L_ROM_D;
+reg [10:0]L_ROM_A;
+
+GALAXIAN_7L L_ROM(
+.CLK(LB_CLK_12M),
+.ADDR(L_ROM_A),
+.DATA(L_ROM_D),
+.ENA(1'b1)
+);
+
+//1K VID-Rom
+wire [7:0]K_ROM_D;
+reg [10:0]K_ROM_A;
+
+GALAXIAN_1K K_ROM(
+.CLK(KB_CLK_12M),
+.ADDR(K_ROM_A),
+.DATA(K_ROM_D),
+.ENA(1'b1)
+);
+
+//1H VID-Rom
+wire [7:0]H_ROM_D;
+reg [10:0]H_ROM_A;
+
+GALAXIAN_1H H_ROM(
+.CLK(HB_CLK_12M),
+.ADDR(H_ROM_A),
+.DATA(H_ROM_D),
+.ENA(1'b1)
+);
+
+reg [7:0]DATA_OUT;
+
+// address map
+//--------------------------------------------------
+// 0x00000 - 0x007FF galmidw.u CPU-ROM
+// 0x00800 - 0x00FFF galmidw.v CPU-ROM
+// 0x01000 - 0x017FF galmidw.w CPU-ROM
+// 0x01800 - 0x01FFF galmidw.y CPU-ROM
+// 0x02000 - 0x027FF 7l CPU-ROM
+// 0x04000 - 0x047FF 1k.bin VID-ROM
+// 0x05000 - 0x057FF 1h.bin VID-ROM
+// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
+always @(posedge I_CLK_18432M)
+begin
+ if (I_ADDR <= 18'h7ff) begin
+ //u
+ U_ROM_A <= I_ADDR[10:0];
+ DATA_OUT <= U_ROM_D;
+ end
+ else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
+ //v
+ V_ROM_A <= I_ADDR[10:0];
+ DATA_OUT <= V_ROM_D;
+ end
+ else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
+ //w
+ W_ROM_A <= I_ADDR[10:0];
+ DATA_OUT <= W_ROM_D;
+ end
+ else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
+ //y
+ Y_ROM_A <= I_ADDR[10:0];
+ DATA_OUT <= Y_ROM_D;
+ end
+ else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
+ //7l
+ L_ROM_A <= I_ADDR[10:0];
+ DATA_OUT <= L_ROM_D;
+ end
+ else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
+ //1k
+ K_ROM_A <= I_ADDR[10:0];
+ DATA_OUT <= K_ROM_D;
+ end
+ else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
+ //1h
+ H_ROM_A <= I_ADDR[10:0];
+ DATA_OUT <= H_ROM_D;
+ end
+end
+
+assign O_DATA = DATA_OUT;
+
+endmodule
--- /dev/null
+//\r
+// Daniel Wallner's T80 header file for verilog\r
+//\r
+// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk. \r
+//\r
+//\r
+module T80as(\r
+ RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n,\r
+ M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n,\r
+ A,DI,DO,DOE);\r
+\r
+input RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n;\r
+output M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n;\r
+output [15:0] A;\r
+input [7:0] DI;\r
+output [7:0] DO;\r
+output DOE;\r
+\r
+endmodule\r
--- /dev/null
+//===============================================================================\r
+// FPGA MOONCRESTA T80_IP I/F\r
+//\r
+// Version : 1.00\r
+//\r
+// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
+//\r
+// Important !\r
+//\r
+// This program is freeware for non-commercial use. \r
+// An author does no guarantee about this program.\r
+// You can use this under your own risk.\r
+// \r
+//================================================================================\r
+\r
+module Z80IP(\r
+\r
+ADRS,\r
+DINP,\r
+DOUT,\r
+BUSWO,\r
+RESET_N,\r
+INT_N,\r
+NMI_N,\r
+WAIT_N,\r
+M1_N,\r
+MREQ_N,\r
+IORQ_N,\r
+RD_N, \r
+WR_N,\r
+RFSH_N,\r
+HALT_N,\r
+CLK\r
+\r
+);\r
+\r
+// I/O assign\r
+output [15:0]ADRS;\r
+input [7:0] DINP;\r
+output [7:0] DOUT;\r
+input RESET_N,INT_N,NMI_N,WAIT_N,CLK;\r
+output M1_N,MREQ_N,IORQ_N,RD_N,WR_N,RFSH_N,HALT_N,BUSWO;\r
+\r
+// Z80IP interface\r
+T80as z80core (\r
+\r
+.RESET_n(RESET_N),\r
+.CLK_n(CLK),\r
+.WAIT_n(WAIT_N),\r
+.INT_n(INT_N),\r
+.NMI_n(NMI_N),\r
+.BUSRQ_n(1'b1),\r
+.M1_n(M1_N),\r
+.MREQ_n(MREQ_N),\r
+.IORQ_n(IORQ_N),\r
+.RD_n(RD_N),\r
+.WR_n(WR_N),\r
+.RFSH_n(RFSH_N),\r
+.HALT_n(HALT_N),\r
+.BUSAK_n(),\r
+.A(ADRS),\r
+.DI(DINP),\r
+.DO(DOUT),\r
+.DOE(BUSWO)\r
+\r
+);\r
+\r
+endmodule\r
+\r
--- /dev/null
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0210 : Fixed wait and halt
+--
+-- 0211 : Fixed Refresh addition and IM 1
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+-- 0237 : Changed 8080 I/O address output, added IntE output
+--
+-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+-- 0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ IORQ : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DInst : in std_logic_vector(7 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0);
+ MC : out std_logic_vector(2 downto 0);
+ TS : out std_logic_vector(2 downto 0);
+ IntCycle_n : out std_logic;
+ IntE : out std_logic;
+ Stop : out std_logic
+ );
+end T80;
+
+architecture rtl of T80 is
+
+ constant aNone : std_logic_vector(2 downto 0) := "111";
+ constant aBC : std_logic_vector(2 downto 0) := "000";
+ constant aDE : std_logic_vector(2 downto 0) := "001";
+ constant aXY : std_logic_vector(2 downto 0) := "010";
+ constant aIOA : std_logic_vector(2 downto 0) := "100";
+ constant aSP : std_logic_vector(2 downto 0) := "101";
+ constant aZI : std_logic_vector(2 downto 0) := "110";
+
+ -- Registers
+ signal ACC, F : std_logic_vector(7 downto 0);
+ signal Ap, Fp : std_logic_vector(7 downto 0);
+ signal I : std_logic_vector(7 downto 0);
+ signal R : unsigned(7 downto 0);
+ signal SP, PC : unsigned(15 downto 0);
+ signal RegDIH : std_logic_vector(7 downto 0);
+ signal RegDIL : std_logic_vector(7 downto 0);
+ signal RegBusA : std_logic_vector(15 downto 0);
+ signal RegBusB : std_logic_vector(15 downto 0);
+ signal RegBusC : std_logic_vector(15 downto 0);
+ signal RegAddrA_r : std_logic_vector(2 downto 0);
+ signal RegAddrA : std_logic_vector(2 downto 0);
+ signal RegAddrB_r : std_logic_vector(2 downto 0);
+ signal RegAddrB : std_logic_vector(2 downto 0);
+ signal RegAddrC : std_logic_vector(2 downto 0);
+ signal RegWEH : std_logic;
+ signal RegWEL : std_logic;
+ signal Alternate : std_logic;
+
+ -- Help Registers
+ signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
+ signal IR : std_logic_vector(7 downto 0); -- Instruction register
+ signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
+ signal RegBusA_r : std_logic_vector(15 downto 0);
+
+ signal ID16 : signed(15 downto 0);
+ signal Save_Mux : std_logic_vector(7 downto 0);
+
+ signal TState : unsigned(2 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal IntE_FF1 : std_logic;
+ signal IntE_FF2 : std_logic;
+ signal Halt_FF : std_logic;
+ signal BusReq_s : std_logic;
+ signal BusAck : std_logic;
+ signal ClkEn : std_logic;
+ signal NMI_s : std_logic;
+ signal INT_s : std_logic;
+ signal IStatus : std_logic_vector(1 downto 0);
+
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal T_Res : std_logic;
+ signal XY_State : std_logic_vector(1 downto 0);
+ signal Pre_XY_F_M : std_logic_vector(2 downto 0);
+ signal NextIs_XY_Fetch : std_logic;
+ signal XY_Ind : std_logic;
+ signal No_BTR : std_logic;
+ signal BTR_r : std_logic;
+ signal Auto_Wait : std_logic;
+ signal Auto_Wait_t1 : std_logic;
+ signal Auto_Wait_t2 : std_logic;
+ signal IncDecZ : std_logic;
+
+ -- ALU signals
+ signal BusB : std_logic_vector(7 downto 0);
+ signal BusA : std_logic_vector(7 downto 0);
+ signal ALU_Q : std_logic_vector(7 downto 0);
+ signal F_Out : std_logic_vector(7 downto 0);
+
+ -- Registered micro code outputs
+ signal Read_To_Reg_r : std_logic_vector(4 downto 0);
+ signal Arith16_r : std_logic;
+ signal Z16_r : std_logic;
+ signal ALU_Op_r : std_logic_vector(3 downto 0);
+ signal Save_ALU_r : std_logic;
+ signal PreserveC_r : std_logic;
+ signal MCycles : std_logic_vector(2 downto 0);
+
+ -- Micro code outputs
+ signal MCycles_d : std_logic_vector(2 downto 0);
+ signal TStates : std_logic_vector(2 downto 0);
+ signal IntCycle : std_logic;
+ signal NMICycle : std_logic;
+ signal Inc_PC : std_logic;
+ signal Inc_WZ : std_logic;
+ signal IncDec_16 : std_logic_vector(3 downto 0);
+ signal Prefix : std_logic_vector(1 downto 0);
+ signal Read_To_Acc : std_logic;
+ signal Read_To_Reg : std_logic;
+ signal Set_BusB_To : std_logic_vector(3 downto 0);
+ signal Set_BusA_To : std_logic_vector(3 downto 0);
+ signal ALU_Op : std_logic_vector(3 downto 0);
+ signal Save_ALU : std_logic;
+ signal PreserveC : std_logic;
+ signal Arith16 : std_logic;
+ signal Set_Addr_To : std_logic_vector(2 downto 0);
+ signal Jump : std_logic;
+ signal JumpE : std_logic;
+ signal JumpXY : std_logic;
+ signal Call : std_logic;
+ signal RstP : std_logic;
+ signal LDZ : std_logic;
+ signal LDW : std_logic;
+ signal LDSPHL : std_logic;
+ signal IORQ_i : std_logic;
+ signal Special_LD : std_logic_vector(2 downto 0);
+ signal ExchangeDH : std_logic;
+ signal ExchangeRp : std_logic;
+ signal ExchangeAF : std_logic;
+ signal ExchangeRS : std_logic;
+ signal I_DJNZ : std_logic;
+ signal I_CPL : std_logic;
+ signal I_CCF : std_logic;
+ signal I_SCF : std_logic;
+ signal I_RETN : std_logic;
+ signal I_BT : std_logic;
+ signal I_BC : std_logic;
+ signal I_BTR : std_logic;
+ signal I_RLD : std_logic;
+ signal I_RRD : std_logic;
+ signal I_INRC : std_logic;
+ signal SetDI : std_logic;
+ signal SetEI : std_logic;
+ signal IMode : std_logic_vector(1 downto 0);
+ signal Halt : std_logic;
+
+begin
+
+ mcode : T80_MCode
+ generic map(
+ Mode => Mode,
+ Flag_C => Flag_C,
+ Flag_N => Flag_N,
+ Flag_P => Flag_P,
+ Flag_X => Flag_X,
+ Flag_H => Flag_H,
+ Flag_Y => Flag_Y,
+ Flag_Z => Flag_Z,
+ Flag_S => Flag_S)
+ port map(
+ IR => IR,
+ ISet => ISet,
+ MCycle => MCycle,
+ F => F,
+ NMICycle => NMICycle,
+ IntCycle => IntCycle,
+ MCycles => MCycles_d,
+ TStates => TStates,
+ Prefix => Prefix,
+ Inc_PC => Inc_PC,
+ Inc_WZ => Inc_WZ,
+ IncDec_16 => IncDec_16,
+ Read_To_Acc => Read_To_Acc,
+ Read_To_Reg => Read_To_Reg,
+ Set_BusB_To => Set_BusB_To,
+ Set_BusA_To => Set_BusA_To,
+ ALU_Op => ALU_Op,
+ Save_ALU => Save_ALU,
+ PreserveC => PreserveC,
+ Arith16 => Arith16,
+ Set_Addr_To => Set_Addr_To,
+ IORQ => IORQ_i,
+ Jump => Jump,
+ JumpE => JumpE,
+ JumpXY => JumpXY,
+ Call => Call,
+ RstP => RstP,
+ LDZ => LDZ,
+ LDW => LDW,
+ LDSPHL => LDSPHL,
+ Special_LD => Special_LD,
+ ExchangeDH => ExchangeDH,
+ ExchangeRp => ExchangeRp,
+ ExchangeAF => ExchangeAF,
+ ExchangeRS => ExchangeRS,
+ I_DJNZ => I_DJNZ,
+ I_CPL => I_CPL,
+ I_CCF => I_CCF,
+ I_SCF => I_SCF,
+ I_RETN => I_RETN,
+ I_BT => I_BT,
+ I_BC => I_BC,
+ I_BTR => I_BTR,
+ I_RLD => I_RLD,
+ I_RRD => I_RRD,
+ I_INRC => I_INRC,
+ SetDI => SetDI,
+ SetEI => SetEI,
+ IMode => IMode,
+ Halt => Halt,
+ NoRead => NoRead,
+ Write => Write);
+
+ alu : T80_ALU
+ generic map(
+ Mode => Mode,
+ Flag_C => Flag_C,
+ Flag_N => Flag_N,
+ Flag_P => Flag_P,
+ Flag_X => Flag_X,
+ Flag_H => Flag_H,
+ Flag_Y => Flag_Y,
+ Flag_Z => Flag_Z,
+ Flag_S => Flag_S)
+ port map(
+ Arith16 => Arith16_r,
+ Z16 => Z16_r,
+ ALU_Op => ALU_Op_r,
+ IR => IR(5 downto 0),
+ ISet => ISet,
+ BusA => BusA,
+ BusB => BusB,
+ F_In => F,
+ Q => ALU_Q,
+ F_Out => F_Out);
+
+ ClkEn <= CEN and not BusAck;
+
+ T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+ NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+ ((Set_Addr_To = aXY) or
+ (MCycle = "001" and IR = "11001011") or
+ (MCycle = "001" and IR = "00110110")) else '0';
+
+ Save_Mux <= BusB when ExchangeRp = '1' else
+ DI_Reg when Save_ALU_r = '0' else
+ ALU_Q;
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ PC <= (others => '0'); -- Program Counter
+ A <= (others => '0');
+ TmpAddr <= (others => '0');
+ IR <= "00000000";
+ ISet <= "00";
+ XY_State <= "00";
+ IStatus <= "00";
+ MCycles <= "000";
+ DO <= "00000000";
+
+ ACC <= (others => '1');
+ F <= (others => '1');
+ Ap <= (others => '1');
+ Fp <= (others => '1');
+ I <= (others => '0');
+ R <= (others => '0');
+ SP <= (others => '1');
+ Alternate <= '0';
+
+ Read_To_Reg_r <= "00000";
+ F <= (others => '1');
+ Arith16_r <= '0';
+ BTR_r <= '0';
+ Z16_r <= '0';
+ ALU_Op_r <= "0000";
+ Save_ALU_r <= '0';
+ PreserveC_r <= '0';
+ XY_Ind <= '0';
+
+ elsif CLK_n'event and CLK_n = '1' then
+
+ if ClkEn = '1' then
+
+ ALU_Op_r <= "0000";
+ Save_ALU_r <= '0';
+ Read_To_Reg_r <= "00000";
+
+ MCycles <= MCycles_d;
+
+ if IMode /= "11" then
+ IStatus <= IMode;
+ end if;
+
+ Arith16_r <= Arith16;
+ PreserveC_r <= PreserveC;
+ if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+ Z16_r <= '1';
+ else
+ Z16_r <= '0';
+ end if;
+
+ if MCycle = "001" and TState(2) = '0' then
+ -- MCycle = 1 and TState = 1, 2, or 3
+
+ if TState = 2 and Wait_n = '1' then
+ if Mode < 2 then
+ A(7 downto 0) <= std_logic_vector(R);
+ A(15 downto 8) <= I;
+ R(6 downto 0) <= R(6 downto 0) + 1;
+ end if;
+
+ if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+ PC <= PC + 1;
+ end if;
+
+ if IntCycle = '1' and IStatus = "01" then
+ IR <= "11111111";
+ elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+ IR <= "00000000";
+ else
+ IR <= DInst;
+ end if;
+
+ ISet <= "00";
+ if Prefix /= "00" then
+ if Prefix = "11" then
+ if IR(5) = '1' then
+ XY_State <= "10";
+ else
+ XY_State <= "01";
+ end if;
+ else
+ if Prefix = "10" then
+ XY_State <= "00";
+ XY_Ind <= '0';
+ end if;
+ ISet <= Prefix;
+ end if;
+ else
+ XY_State <= "00";
+ XY_Ind <= '0';
+ end if;
+ end if;
+
+ else
+ -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+ if MCycle = "110" then
+ XY_Ind <= '1';
+ if Prefix = "01" then
+ ISet <= "01";
+ end if;
+ end if;
+
+ if T_Res = '1' then
+ BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+ if Jump = '1' then
+ A(15 downto 8) <= DI_Reg;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ PC(15 downto 8) <= unsigned(DI_Reg);
+ PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+ elsif JumpXY = '1' then
+ A <= RegBusC;
+ PC <= unsigned(RegBusC);
+ elsif Call = '1' or RstP = '1' then
+ A <= TmpAddr;
+ PC <= unsigned(TmpAddr);
+ elsif MCycle = MCycles and NMICycle = '1' then
+ A <= "0000000001100110";
+ PC <= "0000000001100110";
+ elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+ A(15 downto 8) <= I;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ PC(15 downto 8) <= unsigned(I);
+ PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+ else
+ case Set_Addr_To is
+ when aXY =>
+ if XY_State = "00" then
+ A <= RegBusC;
+ else
+ if NextIs_XY_Fetch = '1' then
+ A <= std_logic_vector(PC);
+ else
+ A <= TmpAddr;
+ end if;
+ end if;
+ when aIOA =>
+ if Mode = 3 then
+ -- Memory map I/O on GBZ80
+ A(15 downto 8) <= (others => '1');
+ elsif Mode = 2 then
+ -- Duplicate I/O address on 8080
+ A(15 downto 8) <= DI_Reg;
+ else
+ A(15 downto 8) <= ACC;
+ end if;
+ A(7 downto 0) <= DI_Reg;
+ when aSP =>
+ A <= std_logic_vector(SP);
+ when aBC =>
+ if Mode = 3 and IORQ_i = '1' then
+ -- Memory map I/O on GBZ80
+ A(15 downto 8) <= (others => '1');
+ A(7 downto 0) <= RegBusC(7 downto 0);
+ else
+ A <= RegBusC;
+ end if;
+ when aDE =>
+ A <= RegBusC;
+ when aZI =>
+ if Inc_WZ = '1' then
+ A <= std_logic_vector(unsigned(TmpAddr) + 1);
+ else
+ A(15 downto 8) <= DI_Reg;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ end if;
+ when others =>
+ A <= std_logic_vector(PC);
+ end case;
+ end if;
+
+ Save_ALU_r <= Save_ALU;
+ ALU_Op_r <= ALU_Op;
+
+ if I_CPL = '1' then
+ -- CPL
+ ACC <= not ACC;
+ F(Flag_Y) <= not ACC(5);
+ F(Flag_H) <= '1';
+ F(Flag_X) <= not ACC(3);
+ F(Flag_N) <= '1';
+ end if;
+ if I_CCF = '1' then
+ -- CCF
+ F(Flag_C) <= not F(Flag_C);
+ F(Flag_Y) <= ACC(5);
+ F(Flag_H) <= F(Flag_C);
+ F(Flag_X) <= ACC(3);
+ F(Flag_N) <= '0';
+ end if;
+ if I_SCF = '1' then
+ -- SCF
+ F(Flag_C) <= '1';
+ F(Flag_Y) <= ACC(5);
+ F(Flag_H) <= '0';
+ F(Flag_X) <= ACC(3);
+ F(Flag_N) <= '0';
+ end if;
+ end if;
+
+ if TState = 2 and Wait_n = '1' then
+ if ISet = "01" and MCycle = "111" then
+ IR <= DInst;
+ end if;
+ if JumpE = '1' then
+ PC <= unsigned(signed(PC) + signed(DI_Reg));
+ elsif Inc_PC = '1' then
+ PC <= PC + 1;
+ end if;
+ if BTR_r = '1' then
+ PC <= PC - 2;
+ end if;
+ if RstP = '1' then
+ TmpAddr <= (others =>'0');
+ TmpAddr(5 downto 3) <= IR(5 downto 3);
+ end if;
+ end if;
+ if TState = 3 and MCycle = "110" then
+ TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+ end if;
+
+ if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+ if IncDec_16(2 downto 0) = "111" then
+ if IncDec_16(3) = '1' then
+ SP <= SP - 1;
+ else
+ SP <= SP + 1;
+ end if;
+ end if;
+ end if;
+
+ if LDSPHL = '1' then
+ SP <= unsigned(RegBusC);
+ end if;
+ if ExchangeAF = '1' then
+ Ap <= ACC;
+ ACC <= Ap;
+ Fp <= F;
+ F <= Fp;
+ end if;
+ if ExchangeRS = '1' then
+ Alternate <= not Alternate;
+ end if;
+ end if;
+
+ if TState = 3 then
+ if LDZ = '1' then
+ TmpAddr(7 downto 0) <= DI_Reg;
+ end if;
+ if LDW = '1' then
+ TmpAddr(15 downto 8) <= DI_Reg;
+ end if;
+
+ if Special_LD(2) = '1' then
+ case Special_LD(1 downto 0) is
+ when "00" =>
+ ACC <= I;
+ F(Flag_P) <= IntE_FF2;
+ when "01" =>
+ ACC <= std_logic_vector(R);
+ F(Flag_P) <= IntE_FF2;
+ when "10" =>
+ I <= ACC;
+ when others =>
+ R <= unsigned(ACC);
+ end case;
+ end if;
+ end if;
+
+ if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+ if Mode = 3 then
+ F(6) <= F_Out(6);
+ F(5) <= F_Out(5);
+ F(7) <= F_Out(7);
+ if PreserveC_r = '0' then
+ F(4) <= F_Out(4);
+ end if;
+ else
+ F(7 downto 1) <= F_Out(7 downto 1);
+ if PreserveC_r = '0' then
+ F(Flag_C) <= F_Out(0);
+ end if;
+ end if;
+ end if;
+ if T_Res = '1' and I_INRC = '1' then
+ F(Flag_H) <= '0';
+ F(Flag_N) <= '0';
+ if DI_Reg(7 downto 0) = "00000000" then
+ F(Flag_Z) <= '1';
+ else
+ F(Flag_Z) <= '0';
+ end if;
+ F(Flag_S) <= DI_Reg(7);
+ F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+ DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+ end if;
+
+ if TState = 1 and Auto_Wait_t1 = '0' then
+ DO <= BusB;
+ if I_RLD = '1' then
+ DO(3 downto 0) <= BusA(3 downto 0);
+ DO(7 downto 4) <= BusB(3 downto 0);
+ end if;
+ if I_RRD = '1' then
+ DO(3 downto 0) <= BusB(7 downto 4);
+ DO(7 downto 4) <= BusA(3 downto 0);
+ end if;
+ end if;
+
+ if T_Res = '1' then
+ Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+ Read_To_Reg_r(4) <= Read_To_Reg;
+ if Read_To_Acc = '1' then
+ Read_To_Reg_r(3 downto 0) <= "0111";
+ Read_To_Reg_r(4) <= '1';
+ end if;
+ end if;
+
+ if TState = 1 and I_BT = '1' then
+ F(Flag_X) <= ALU_Q(3);
+ F(Flag_Y) <= ALU_Q(1);
+ F(Flag_H) <= '0';
+ F(Flag_N) <= '0';
+ end if;
+ if I_BC = '1' or I_BT = '1' then
+ F(Flag_P) <= IncDecZ;
+ end if;
+
+ if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+ (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+ case Read_To_Reg_r is
+ when "10111" =>
+ ACC <= Save_Mux;
+ when "10110" =>
+ DO <= Save_Mux;
+ when "11000" =>
+ SP(7 downto 0) <= unsigned(Save_Mux);
+ when "11001" =>
+ SP(15 downto 8) <= unsigned(Save_Mux);
+ when "11011" =>
+ F <= Save_Mux;
+ when others =>
+ end case;
+ end if;
+
+ end if;
+
+ end if;
+
+ end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '1' then
+ if ClkEn = '1' then
+ -- Bus A / Write
+ RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+ if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+ RegAddrA_r <= XY_State(1) & "11";
+ end if;
+
+ -- Bus B
+ RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+ if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+ RegAddrB_r <= XY_State(1) & "11";
+ end if;
+
+ -- Address from register
+ RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+ -- Jump (HL), LD SP,HL
+ if (JumpXY = '1' or LDSPHL = '1') then
+ RegAddrC <= Alternate & "10";
+ end if;
+ if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+ RegAddrC <= XY_State(1) & "11";
+ end if;
+
+ if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+ IncDecZ <= F_Out(Flag_Z);
+ end if;
+ if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+ if ID16 = 0 then
+ IncDecZ <= '0';
+ else
+ IncDecZ <= '1';
+ end if;
+ end if;
+
+ RegBusA_r <= RegBusA;
+ end if;
+ end if;
+ end process;
+
+ RegAddrA <=
+ -- 16 bit increment/decrement
+ Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+ (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+ XY_State(1) & "11" when (TState = 2 or
+ (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+ -- EX HL,DL
+ Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+ Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+ -- Bus A / Write
+ RegAddrA_r;
+
+ RegAddrB <=
+ -- EX HL,DL
+ Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+ -- Bus B
+ RegAddrB_r;
+
+ ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+ signed(RegBusA) + 1;
+
+ process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+ ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+ begin
+ RegWEH <= '0';
+ RegWEL <= '0';
+ if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+ (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+ case Read_To_Reg_r is
+ when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+ RegWEH <= not Read_To_Reg_r(0);
+ RegWEL <= Read_To_Reg_r(0);
+ when others =>
+ end case;
+ end if;
+
+ if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+ RegWEH <= '1';
+ RegWEL <= '1';
+ end if;
+
+ if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+ case IncDec_16(1 downto 0) is
+ when "00" | "01" | "10" =>
+ RegWEH <= '1';
+ RegWEL <= '1';
+ when others =>
+ end case;
+ end if;
+ end process;
+
+ process (Save_Mux, RegBusB, RegBusA_r, ID16,
+ ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+ begin
+ RegDIH <= Save_Mux;
+ RegDIL <= Save_Mux;
+
+ if ExchangeDH = '1' and TState = 3 then
+ RegDIH <= RegBusB(15 downto 8);
+ RegDIL <= RegBusB(7 downto 0);
+ end if;
+ if ExchangeDH = '1' and TState = 4 then
+ RegDIH <= RegBusA_r(15 downto 8);
+ RegDIL <= RegBusA_r(7 downto 0);
+ end if;
+
+ if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+ RegDIH <= std_logic_vector(ID16(15 downto 8));
+ RegDIL <= std_logic_vector(ID16(7 downto 0));
+ end if;
+ end process;
+
+ Regs : T80_Reg
+ port map(
+ Clk => CLK_n,
+ CEN => ClkEn,
+ WEH => RegWEH,
+ WEL => RegWEL,
+ AddrA => RegAddrA,
+ AddrB => RegAddrB,
+ AddrC => RegAddrC,
+ DIH => RegDIH,
+ DIL => RegDIL,
+ DOAH => RegBusA(15 downto 8),
+ DOAL => RegBusA(7 downto 0),
+ DOBH => RegBusB(15 downto 8),
+ DOBL => RegBusB(7 downto 0),
+ DOCH => RegBusC(15 downto 8),
+ DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '1' then
+ if ClkEn = '1' then
+ case Set_BusB_To is
+ when "0111" =>
+ BusB <= ACC;
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+ if Set_BusB_To(0) = '1' then
+ BusB <= RegBusB(7 downto 0);
+ else
+ BusB <= RegBusB(15 downto 8);
+ end if;
+ when "0110" =>
+ BusB <= DI_Reg;
+ when "1000" =>
+ BusB <= std_logic_vector(SP(7 downto 0));
+ when "1001" =>
+ BusB <= std_logic_vector(SP(15 downto 8));
+ when "1010" =>
+ BusB <= "00000001";
+ when "1011" =>
+ BusB <= F;
+ when "1100" =>
+ BusB <= std_logic_vector(PC(7 downto 0));
+ when "1101" =>
+ BusB <= std_logic_vector(PC(15 downto 8));
+ when "1110" =>
+ BusB <= "00000000";
+ when others =>
+ BusB <= "--------";
+ end case;
+
+ case Set_BusA_To is
+ when "0111" =>
+ BusA <= ACC;
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+ if Set_BusA_To(0) = '1' then
+ BusA <= RegBusA(7 downto 0);
+ else
+ BusA <= RegBusA(15 downto 8);
+ end if;
+ when "0110" =>
+ BusA <= DI_Reg;
+ when "1000" =>
+ BusA <= std_logic_vector(SP(7 downto 0));
+ when "1001" =>
+ BusA <= std_logic_vector(SP(15 downto 8));
+ when "1010" =>
+ BusA <= "00000000";
+ when others =>
+ BusB <= "--------";
+ end case;
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+ process (RESET_n,CLK_n)
+ begin
+ if RESET_n = '0' then
+ RFSH_n <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
+ RFSH_n <= '0';
+ else
+ RFSH_n <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ MC <= std_logic_vector(MCycle);
+ TS <= std_logic_vector(TState);
+ DI_Reg <= DI;
+ HALT_n <= not Halt_FF;
+ BUSAK_n <= not BusAck;
+ IntCycle_n <= not IntCycle;
+ IntE <= IntE_FF1;
+ IORQ <= IORQ_i;
+ Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+ process (RESET_n, CLK_n)
+ variable OldNMI_n : std_logic;
+ begin
+ if RESET_n = '0' then
+ BusReq_s <= '0';
+ INT_s <= '0';
+ NMI_s <= '0';
+ OldNMI_n := '0';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ BusReq_s <= not BUSRQ_n;
+ INT_s <= not INT_n;
+ if NMICycle = '1' then
+ NMI_s <= '0';
+ elsif NMI_n = '0' and OldNMI_n = '1' then
+ NMI_s <= '1';
+ end if;
+ OldNMI_n := NMI_n;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ MCycle <= "001";
+ TState <= "000";
+ Pre_XY_F_M <= "000";
+ Halt_FF <= '0';
+ BusAck <= '0';
+ NMICycle <= '0';
+ IntCycle <= '0';
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ No_BTR <= '0';
+ Auto_Wait_t1 <= '0';
+ Auto_Wait_t2 <= '0';
+ M1_n <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ if T_Res = '1' then
+ Auto_Wait_t1 <= '0';
+ else
+ Auto_Wait_t1 <= Auto_Wait or IORQ_i;
+ end if;
+ Auto_Wait_t2 <= Auto_Wait_t1;
+ No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+ (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+ (I_BTR and (not IR(4) or F(Flag_Z)));
+ if TState = 2 then
+ if SetEI = '1' then
+ IntE_FF1 <= '1';
+ IntE_FF2 <= '1';
+ end if;
+ if I_RETN = '1' then
+ IntE_FF1 <= IntE_FF2;
+ end if;
+ end if;
+ if TState = 3 then
+ if SetDI = '1' then
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ end if;
+ end if;
+ if IntCycle = '1' or NMICycle = '1' then
+ Halt_FF <= '0';
+ end if;
+ if MCycle = "001" and TState = 2 and Wait_n = '1' then
+ M1_n <= '1';
+ end if;
+ if BusReq_s = '1' and BusAck = '1' then
+ else
+ BusAck <= '0';
+ if TState = 2 and Wait_n = '0' then
+ elsif T_Res = '1' then
+ if Halt = '1' then
+ Halt_FF <= '1';
+ end if;
+ if BusReq_s = '1' then
+ BusAck <= '1';
+ else
+ TState <= "001";
+ if NextIs_XY_Fetch = '1' then
+ MCycle <= "110";
+ Pre_XY_F_M <= MCycle;
+ if IR = "00110110" and Mode = 0 then
+ Pre_XY_F_M <= "010";
+ end if;
+ elsif (MCycle = "111") or
+ (MCycle = "110" and Mode = 1 and ISet /= "01") then
+ MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+ elsif (MCycle = MCycles) or
+ No_BTR = '1' or
+ (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+ M1_n <= '0';
+ MCycle <= "001";
+ IntCycle <= '0';
+ NMICycle <= '0';
+ if NMI_s = '1' and Prefix = "00" then
+ NMICycle <= '1';
+ IntE_FF1 <= '0';
+ elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+ IntCycle <= '1';
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ end if;
+ else
+ MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+ end if;
+ end if;
+ else
+ if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
+ (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
+ TState <= TState + 1;
+ end if;
+ end if;
+ end if;
+ if TState = 0 then
+ M1_n <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process (IntCycle, NMICycle, MCycle)
+ begin
+ Auto_Wait <= '0';
+ if IntCycle = '1' or NMICycle = '1' then
+ if MCycle = "001" then
+ Auto_Wait <= '1';
+ end if;
+ end if;
+ end process;
+
+end;
--- /dev/null
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+-- 0240 : Added GB operations
+--
+-- 0242 : Cleanup
+--
+-- 0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ Arith16 : in std_logic;
+ Z16 : in std_logic;
+ ALU_Op : in std_logic_vector(3 downto 0);
+ IR : in std_logic_vector(5 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ BusA : in std_logic_vector(7 downto 0);
+ BusB : in std_logic_vector(7 downto 0);
+ F_In : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ F_Out : out std_logic_vector(7 downto 0)
+ );
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+ procedure AddSub(A : std_logic_vector;
+ B : std_logic_vector;
+ Sub : std_logic;
+ Carry_In : std_logic;
+ signal Res : out std_logic_vector;
+ signal Carry : out std_logic) is
+ variable B_i : unsigned(A'length - 1 downto 0);
+ variable Res_i : unsigned(A'length + 1 downto 0);
+ begin
+ if Sub = '1' then
+ B_i := not unsigned(B);
+ else
+ B_i := unsigned(B);
+ end if;
+ Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+ Carry <= Res_i(A'length + 1);
+ Res <= std_logic_vector(Res_i(A'length downto 1));
+ end;
+
+ -- AddSub variables (temporary signals)
+ signal UseCarry : std_logic;
+ signal Carry7_v : std_logic;
+ signal Overflow_v : std_logic;
+ signal HalfCarry_v : std_logic;
+ signal Carry_v : std_logic;
+ signal Q_v : std_logic_vector(7 downto 0);
+
+ signal BitMask : std_logic_vector(7 downto 0);
+
+begin
+
+ with IR(5 downto 3) select BitMask <= "00000001" when "000",
+ "00000010" when "001",
+ "00000100" when "010",
+ "00001000" when "011",
+ "00010000" when "100",
+ "00100000" when "101",
+ "01000000" when "110",
+ "10000000" when others;
+
+ UseCarry <= not ALU_Op(2) and ALU_Op(0);
+ AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+ AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+ AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+ OverFlow_v <= Carry_v xor Carry7_v;
+
+ process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+ variable Q_t : std_logic_vector(7 downto 0);
+ variable DAA_Q : unsigned(8 downto 0);
+ begin
+ Q_t := "--------";
+ F_Out <= F_In;
+ DAA_Q := "---------";
+ case ALU_Op is
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_C) <= '0';
+ case ALU_OP(2 downto 0) is
+ when "000" | "001" => -- ADD, ADC
+ Q_t := Q_v;
+ F_Out(Flag_C) <= Carry_v;
+ F_Out(Flag_H) <= HalfCarry_v;
+ F_Out(Flag_P) <= OverFlow_v;
+ when "010" | "011" | "111" => -- SUB, SBC, CP
+ Q_t := Q_v;
+ F_Out(Flag_N) <= '1';
+ F_Out(Flag_C) <= not Carry_v;
+ F_Out(Flag_H) <= not HalfCarry_v;
+ F_Out(Flag_P) <= OverFlow_v;
+ when "100" => -- AND
+ Q_t(7 downto 0) := BusA and BusB;
+ F_Out(Flag_H) <= '1';
+ when "101" => -- XOR
+ Q_t(7 downto 0) := BusA xor BusB;
+ F_Out(Flag_H) <= '0';
+ when others => -- OR "110"
+ Q_t(7 downto 0) := BusA or BusB;
+ F_Out(Flag_H) <= '0';
+ end case;
+ if ALU_Op(2 downto 0) = "111" then -- CP
+ F_Out(Flag_X) <= BusB(3);
+ F_Out(Flag_Y) <= BusB(5);
+ else
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ end if;
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ if Z16 = '1' then
+ F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
+ end if;
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= Q_t(7);
+ case ALU_Op(2 downto 0) is
+ when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+ when others =>
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ end case;
+ if Arith16 = '1' then
+ F_Out(Flag_S) <= F_In(Flag_S);
+ F_Out(Flag_Z) <= F_In(Flag_Z);
+ F_Out(Flag_P) <= F_In(Flag_P);
+ end if;
+ when "1100" =>
+ -- DAA
+ F_Out(Flag_H) <= F_In(Flag_H);
+ F_Out(Flag_C) <= F_In(Flag_C);
+ DAA_Q(7 downto 0) := unsigned(BusA);
+ DAA_Q(8) := '0';
+ if F_In(Flag_N) = '0' then
+ -- After addition
+ -- Alow > 9 or H = 1
+ if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+ if (DAA_Q(3 downto 0) > 9) then
+ F_Out(Flag_H) <= '1';
+ else
+ F_Out(Flag_H) <= '0';
+ end if;
+ DAA_Q := DAA_Q + 6;
+ end if;
+ -- new Ahigh > 9 or C = 1
+ if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+ DAA_Q := DAA_Q + 96; -- 0x60
+ end if;
+ else
+ -- After subtraction
+ if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+ if DAA_Q(3 downto 0) > 5 then
+ F_Out(Flag_H) <= '0';
+ end if;
+ DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+ end if;
+ if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+ DAA_Q := DAA_Q - 352; -- 0x160
+ end if;
+ end if;
+ F_Out(Flag_X) <= DAA_Q(3);
+ F_Out(Flag_Y) <= DAA_Q(5);
+ F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+ Q_t := std_logic_vector(DAA_Q(7 downto 0));
+ if DAA_Q(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= DAA_Q(7);
+ F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+ DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+ when "1101" | "1110" =>
+ -- RLD, RRD
+ Q_t(7 downto 4) := BusA(7 downto 4);
+ if ALU_Op(0) = '1' then
+ Q_t(3 downto 0) := BusB(7 downto 4);
+ else
+ Q_t(3 downto 0) := BusB(3 downto 0);
+ end if;
+ F_Out(Flag_H) <= '0';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= Q_t(7);
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ when "1001" =>
+ -- BIT
+ Q_t(7 downto 0) := BusB and BitMask;
+ F_Out(Flag_S) <= Q_t(7);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ F_Out(Flag_P) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ F_Out(Flag_P) <= '0';
+ end if;
+ F_Out(Flag_H) <= '1';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= '0';
+ F_Out(Flag_Y) <= '0';
+ if IR(2 downto 0) /= "110" then
+ F_Out(Flag_X) <= BusB(3);
+ F_Out(Flag_Y) <= BusB(5);
+ end if;
+ when "1010" =>
+ -- SET
+ Q_t(7 downto 0) := BusB or BitMask;
+ when "1011" =>
+ -- RES
+ Q_t(7 downto 0) := BusB and not BitMask;
+ when "1000" =>
+ -- ROT
+ case IR(5 downto 3) is
+ when "000" => -- RLC
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := BusA(7);
+ F_Out(Flag_C) <= BusA(7);
+ when "010" => -- RL
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := F_In(Flag_C);
+ F_Out(Flag_C) <= BusA(7);
+ when "001" => -- RRC
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := BusA(0);
+ F_Out(Flag_C) <= BusA(0);
+ when "011" => -- RR
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := F_In(Flag_C);
+ F_Out(Flag_C) <= BusA(0);
+ when "100" => -- SLA
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := '0';
+ F_Out(Flag_C) <= BusA(7);
+ when "110" => -- SLL (Undocumented) / SWAP
+ if Mode = 3 then
+ Q_t(7 downto 4) := BusA(3 downto 0);
+ Q_t(3 downto 0) := BusA(7 downto 4);
+ F_Out(Flag_C) <= '0';
+ else
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := '1';
+ F_Out(Flag_C) <= BusA(7);
+ end if;
+ when "101" => -- SRA
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := BusA(7);
+ F_Out(Flag_C) <= BusA(0);
+ when others => -- SRL
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := '0';
+ F_Out(Flag_C) <= BusA(0);
+ end case;
+ F_Out(Flag_H) <= '0';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ F_Out(Flag_S) <= Q_t(7);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ if ISet = "00" then
+ F_Out(Flag_P) <= F_In(Flag_P);
+ F_Out(Flag_S) <= F_In(Flag_S);
+ F_Out(Flag_Z) <= F_In(Flag_Z);
+ end if;
+ when others =>
+ null;
+ end case;
+ Q <= Q_t;
+ end process;
+
+end;
--- /dev/null
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0211 : Fixed IM 1
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0235 : Added IM 2 fix by Mike Johnson
+--
+-- 0238 : Added NoRead signal
+--
+-- 0238b: Fixed instruction timing for POP and DJNZ
+--
+-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+--
+-- 0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_MCode is
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ IR : in std_logic_vector(7 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ MCycle : in std_logic_vector(2 downto 0);
+ F : in std_logic_vector(7 downto 0);
+ NMICycle : in std_logic;
+ IntCycle : in std_logic;
+ MCycles : out std_logic_vector(2 downto 0);
+ TStates : out std_logic_vector(2 downto 0);
+ Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+ Inc_PC : out std_logic;
+ Inc_WZ : out std_logic;
+ IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
+ Read_To_Reg : out std_logic;
+ Read_To_Acc : out std_logic;
+ Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+ Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+ ALU_Op : out std_logic_vector(3 downto 0);
+ -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+ Save_ALU : out std_logic;
+ PreserveC : out std_logic;
+ Arith16 : out std_logic;
+ Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+ IORQ : out std_logic;
+ Jump : out std_logic;
+ JumpE : out std_logic;
+ JumpXY : out std_logic;
+ Call : out std_logic;
+ RstP : out std_logic;
+ LDZ : out std_logic;
+ LDW : out std_logic;
+ LDSPHL : out std_logic;
+ Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+ ExchangeDH : out std_logic;
+ ExchangeRp : out std_logic;
+ ExchangeAF : out std_logic;
+ ExchangeRS : out std_logic;
+ I_DJNZ : out std_logic;
+ I_CPL : out std_logic;
+ I_CCF : out std_logic;
+ I_SCF : out std_logic;
+ I_RETN : out std_logic;
+ I_BT : out std_logic;
+ I_BC : out std_logic;
+ I_BTR : out std_logic;
+ I_RLD : out std_logic;
+ I_RRD : out std_logic;
+ I_INRC : out std_logic;
+ SetDI : out std_logic;
+ SetEI : out std_logic;
+ IMode : out std_logic_vector(1 downto 0);
+ Halt : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic
+ );
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+ constant aNone : std_logic_vector(2 downto 0) := "111";
+ constant aBC : std_logic_vector(2 downto 0) := "000";
+ constant aDE : std_logic_vector(2 downto 0) := "001";
+ constant aXY : std_logic_vector(2 downto 0) := "010";
+ constant aIOA : std_logic_vector(2 downto 0) := "100";
+ constant aSP : std_logic_vector(2 downto 0) := "101";
+ constant aZI : std_logic_vector(2 downto 0) := "110";
+-- constant aNone : std_logic_vector(2 downto 0) := "000";
+-- constant aXY : std_logic_vector(2 downto 0) := "001";
+-- constant aIOA : std_logic_vector(2 downto 0) := "010";
+-- constant aSP : std_logic_vector(2 downto 0) := "011";
+-- constant aBC : std_logic_vector(2 downto 0) := "100";
+-- constant aDE : std_logic_vector(2 downto 0) := "101";
+-- constant aZI : std_logic_vector(2 downto 0) := "110";
+
+ function is_cc_true(
+ F : std_logic_vector(7 downto 0);
+ cc : bit_vector(2 downto 0)
+ ) return boolean is
+ begin
+ if Mode = 3 then
+ case cc is
+ when "000" => return F(7) = '0'; -- NZ
+ when "001" => return F(7) = '1'; -- Z
+ when "010" => return F(4) = '0'; -- NC
+ when "011" => return F(4) = '1'; -- C
+ when "100" => return false;
+ when "101" => return false;
+ when "110" => return false;
+ when "111" => return false;
+ end case;
+ else
+ case cc is
+ when "000" => return F(6) = '0'; -- NZ
+ when "001" => return F(6) = '1'; -- Z
+ when "010" => return F(0) = '0'; -- NC
+ when "011" => return F(0) = '1'; -- C
+ when "100" => return F(2) = '0'; -- PO
+ when "101" => return F(2) = '1'; -- PE
+ when "110" => return F(7) = '0'; -- P
+ when "111" => return F(7) = '1'; -- M
+ end case;
+ end if;
+ end;
+
+begin
+
+ process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+ variable DDD : std_logic_vector(2 downto 0);
+ variable SSS : std_logic_vector(2 downto 0);
+ variable DPair : std_logic_vector(1 downto 0);
+ variable IRB : bit_vector(7 downto 0);
+ begin
+ DDD := IR(5 downto 3);
+ SSS := IR(2 downto 0);
+ DPair := IR(5 downto 4);
+ IRB := to_bitvector(IR);
+
+ MCycles <= "001";
+ if MCycle = "001" then
+ TStates <= "100";
+ else
+ TStates <= "011";
+ end if;
+ Prefix <= "00";
+ Inc_PC <= '0';
+ Inc_WZ <= '0';
+ IncDec_16 <= "0000";
+ Read_To_Acc <= '0';
+ Read_To_Reg <= '0';
+ Set_BusB_To <= "0000";
+ Set_BusA_To <= "0000";
+ ALU_Op <= "0" & IR(5 downto 3);
+ Save_ALU <= '0';
+ PreserveC <= '0';
+ Arith16 <= '0';
+ IORQ <= '0';
+ Set_Addr_To <= aNone;
+ Jump <= '0';
+ JumpE <= '0';
+ JumpXY <= '0';
+ Call <= '0';
+ RstP <= '0';
+ LDZ <= '0';
+ LDW <= '0';
+ LDSPHL <= '0';
+ Special_LD <= "000";
+ ExchangeDH <= '0';
+ ExchangeRp <= '0';
+ ExchangeAF <= '0';
+ ExchangeRS <= '0';
+ I_DJNZ <= '0';
+ I_CPL <= '0';
+ I_CCF <= '0';
+ I_SCF <= '0';
+ I_RETN <= '0';
+ I_BT <= '0';
+ I_BC <= '0';
+ I_BTR <= '0';
+ I_RLD <= '0';
+ I_RRD <= '0';
+ I_INRC <= '0';
+ SetDI <= '0';
+ SetEI <= '0';
+ IMode <= "11";
+ Halt <= '0';
+ NoRead <= '0';
+ Write <= '0';
+
+ case ISet is
+ when "00" =>
+
+------------------------------------------------------------------------------
+--
+-- Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+ case IRB is
+-- 8 BIT LOAD GROUP
+ when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+ |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+ |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+ |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+ |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+ |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+ |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+ -- LD r,r'
+ Set_BusB_To(2 downto 0) <= SSS;
+ ExchangeRp <= '1';
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+ -- LD r,n
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+ -- LD r,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+ -- LD (HL),r
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00110110" =>
+ -- LD (HL),n
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aXY;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00001010" =>
+ -- LD A,(BC)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "00011010" =>
+ -- LD A,(DE)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aDE;
+ when 2 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "00111010" =>
+ if Mode = 3 then
+ -- LDD A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IncDec_16 <= "1110";
+ when others => null;
+ end case;
+ else
+ -- LD A,(nn)
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ when 4 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "00000010" =>
+ -- LD (BC),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00010010" =>
+ -- LD (DE),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aDE;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00110010" =>
+ if Mode = 3 then
+ -- LDD (HL),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "1110";
+ when others => null;
+ end case;
+ else
+ -- LD (nn),A
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ Set_BusB_To <= "0111";
+ when 4 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+
+-- 16 BIT LOAD GROUP
+ when "00000001"|"00010001"|"00100001"|"00110001" =>
+ -- LD dd,nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1000";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '1';
+ end if;
+ when 3 =>
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1001";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+ when "00101010" =>
+ if Mode = 3 then
+ -- LDI A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IncDec_16 <= "0110";
+ when others => null;
+ end case;
+ else
+ -- LD HL,(nn)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Set_BusA_To(2 downto 0) <= "101"; -- L
+ Read_To_Reg <= '1';
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Set_BusA_To(2 downto 0) <= "100"; -- H
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "00100010" =>
+ if Mode = 3 then
+ -- LDI (HL),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "0110";
+ when others => null;
+ end case;
+ else
+ -- LD (nn),HL
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ Set_BusB_To <= "0101"; -- L
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ Set_BusB_To <= "0100"; -- H
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11111001" =>
+ -- LD SP,HL
+ TStates <= "110";
+ LDSPHL <= '1';
+ when "11000101"|"11010101"|"11100101"|"11110101" =>
+ -- PUSH qq
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_TO <= aSP;
+ if DPAIR = "11" then
+ Set_BusB_To <= "0111";
+ else
+ Set_BusB_To(2 downto 1) <= DPAIR;
+ Set_BusB_To(0) <= '0';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 2 =>
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ if DPAIR = "11" then
+ Set_BusB_To <= "1011";
+ else
+ Set_BusB_To(2 downto 1) <= DPAIR;
+ Set_BusB_To(0) <= '1';
+ Set_BusB_To(3) <= '0';
+ end if;
+ Write <= '1';
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "11000001"|"11010001"|"11100001"|"11110001" =>
+ -- POP qq
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1011";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '1';
+ end if;
+ when 3 =>
+ IncDec_16 <= "0111";
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "0111";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+ when "11101011" =>
+ if Mode /= 3 then
+ -- EX DE,HL
+ ExchangeDH <= '1';
+ end if;
+ when "00001000" =>
+ if Mode = 3 then
+ -- LD (nn),SP
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ Set_BusB_To <= "1000";
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ Set_BusB_To <= "1001";
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ elsif Mode < 2 then
+ -- EX AF,AF'
+ ExchangeAF <= '1';
+ end if;
+ when "11011001" =>
+ if Mode = 3 then
+ -- RETI
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ I_RETN <= '1';
+ SetEI <= '1';
+ when others => null;
+ end case;
+ elsif Mode < 2 then
+ -- EXX
+ ExchangeRS <= '1';
+ end if;
+ when "11100011" =>
+ if Mode /= 3 then
+ -- EX (SP),HL
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aSP;
+ when 2 =>
+ Read_To_Reg <= '1';
+ Set_BusA_To <= "0101";
+ Set_BusB_To <= "0101";
+ Set_Addr_To <= aSP;
+ when 3 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ TStates <= "100";
+ Write <= '1';
+ when 4 =>
+ Read_To_Reg <= '1';
+ Set_BusA_To <= "0100";
+ Set_BusB_To <= "0100";
+ Set_Addr_To <= aSP;
+ when 5 =>
+ IncDec_16 <= "1111";
+ TStates <= "101";
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+ when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+ |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+ |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+ |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+ |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+ -- ADD A,r
+ -- ADC A,r
+ -- SUB A,r
+ -- SBC A,r
+ -- AND A,r
+ -- OR A,r
+ -- XOR A,r
+ -- CP A,r
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+ -- ADD A,(HL)
+ -- ADC A,(HL)
+ -- SUB A,(HL)
+ -- SBC A,(HL)
+ -- AND A,(HL)
+ -- OR A,(HL)
+ -- XOR A,(HL)
+ -- CP A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ when others => null;
+ end case;
+ when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+ -- ADD A,n
+ -- ADC A,n
+ -- SUB A,n
+ -- SBC A,n
+ -- AND A,n
+ -- OR A,n
+ -- XOR A,n
+ -- CP A,n
+ MCycles <= "010";
+ if MCycle = "010" then
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ end if;
+ when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+ -- INC r
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0000";
+ when "00110100" =>
+ -- INC (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0000";
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+ -- DEC r
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0010";
+ when "00110101" =>
+ -- DEC (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ ALU_Op <= "0010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+ when "00100111" =>
+ -- DAA
+ Set_BusA_To(2 downto 0) <= "111";
+ Read_To_Reg <= '1';
+ ALU_Op <= "1100";
+ Save_ALU <= '1';
+ when "00101111" =>
+ -- CPL
+ I_CPL <= '1';
+ when "00111111" =>
+ -- CCF
+ I_CCF <= '1';
+ when "00110111" =>
+ -- SCF
+ I_SCF <= '1';
+ when "00000000" =>
+ if NMICycle = '1' then
+ -- NMI
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ TStates <= "100";
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ TStates <= "100";
+ Write <= '1';
+ when others => null;
+ end case;
+ elsif IntCycle = '1' then
+ -- INT (IM 2)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ LDZ <= '1';
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ TStates <= "100";
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ TStates <= "100";
+ Write <= '1';
+ when 4 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 5 =>
+ Jump <= '1';
+ when others => null;
+ end case;
+ else
+ -- NOP
+ end if;
+ when "01110110" =>
+ -- HALT
+ Halt <= '1';
+ when "11110011" =>
+ -- DI
+ SetDI <= '1';
+ when "11111011" =>
+ -- EI
+ SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+ when "00001001"|"00011001"|"00101001"|"00111001" =>
+ -- ADD HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ Arith16 <= '1';
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ Arith16 <= '1';
+ when others =>
+ end case;
+ when "00000011"|"00010011"|"00100011"|"00110011" =>
+ -- INC ss
+ TStates <= "110";
+ IncDec_16(3 downto 2) <= "01";
+ IncDec_16(1 downto 0) <= DPair;
+ when "00001011"|"00011011"|"00101011"|"00111011" =>
+ -- DEC ss
+ TStates <= "110";
+ IncDec_16(3 downto 2) <= "11";
+ IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+ when "00000111"
+ -- RLCA
+ |"00010111"
+ -- RLA
+ |"00001111"
+ -- RRCA
+ |"00011111" =>
+ -- RRA
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+
+-- JUMP GROUP
+ when "11000011" =>
+ -- JP nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ Jump <= '1';
+ when others => null;
+ end case;
+ when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+ if IR(5) = '1' and Mode = 3 then
+ case IRB(4 downto 3) is
+ when "00" =>
+ -- LD ($FF00+C),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "01" =>
+ -- LD (nn),A
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ Set_BusB_To <= "0111";
+ when 4 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "10" =>
+ -- LD A,($FF00+C)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "11" =>
+ -- LD A,(nn)
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ when 4 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ end case;
+ else
+ -- JP cc,nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ Jump <= '1';
+ end if;
+ when others => null;
+ end case;
+ end if;
+ when "00011000" =>
+ if Mode /= 2 then
+ -- JR e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00111000" =>
+ if Mode /= 2 then
+ -- JR C,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_C) = '0' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00110000" =>
+ if Mode /= 2 then
+ -- JR NC,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_C) = '1' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00101000" =>
+ if Mode /= 2 then
+ -- JR Z,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_Z) = '0' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00100000" =>
+ if Mode /= 2 then
+ -- JR NZ,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_Z) = '1' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "11101001" =>
+ -- JP (HL)
+ JumpXY <= '1';
+ when "00010000" =>
+ if Mode = 3 then
+ I_DJNZ <= '1';
+ elsif Mode < 2 then
+ -- DJNZ,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ I_DJNZ <= '1';
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= "000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ I_DJNZ <= '1';
+ Inc_PC <= '1';
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+
+-- CALL AND RETURN GROUP
+ when "11001101" =>
+ -- CALL nn
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ IncDec_16 <= "1111";
+ Inc_PC <= '1';
+ TStates <= "100";
+ Set_Addr_To <= aSP;
+ LDW <= '1';
+ Set_BusB_To <= "1101";
+ when 4 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 5 =>
+ Write <= '1';
+ Call <= '1';
+ when others => null;
+ end case;
+ when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+ if IR(5) = '0' or Mode /= 3 then
+ -- CALL cc,nn
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ LDW <= '1';
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ IncDec_16 <= "1111";
+ Set_Addr_TO <= aSP;
+ TStates <= "100";
+ Set_BusB_To <= "1101";
+ else
+ MCycles <= "011";
+ end if;
+ when 4 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 5 =>
+ Write <= '1';
+ Call <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11001001" =>
+ -- RET
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ when others => null;
+ end case;
+ when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+ if IR(5) = '1' and Mode = 3 then
+ case IRB(4 downto 3) is
+ when "00" =>
+ -- LD ($FF00+nn),A
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ Set_BusB_To <= "0111";
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "01" =>
+ -- ADD SP,n
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ ALU_Op <= "0000";
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To <= "1000";
+ Set_BusB_To <= "0110";
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To <= "1001";
+ Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+ when others =>
+ end case;
+ when "10" =>
+ -- LD A,($FF00+nn)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ when 3 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "11" =>
+ -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Set_BusA_To(2 downto 0) <= "101"; -- L
+ Read_To_Reg <= '1';
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Set_BusA_To(2 downto 0) <= "100"; -- H
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ end case;
+ else
+ -- RET cc
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ Set_Addr_TO <= aSP;
+ else
+ MCycles <= "001";
+ end if;
+ TStates <= "101";
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ when others => null;
+ end case;
+ end if;
+ when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+ -- RST p
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ Write <= '1';
+ RstP <= '1';
+ when others => null;
+ end case;
+
+-- INPUT AND OUTPUT GROUP
+ when "11011011" =>
+ if Mode /= 3 then
+ -- IN A,(n)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ when 3 =>
+ Read_To_Acc <= '1';
+ IORQ <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11010011" =>
+ if Mode /= 3 then
+ -- OUT (n),A
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ Set_BusB_To <= "0111";
+ when 3 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others => null;
+ end case;
+ end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+ when "11001011" =>
+ if Mode /= 2 then
+ Prefix <= "01";
+ end if;
+
+ when "11101101" =>
+ if Mode < 2 then
+ Prefix <= "10";
+ end if;
+
+ when "11011101"|"11111101" =>
+ if Mode < 2 then
+ Prefix <= "11";
+ end if;
+
+ end case;
+
+ when "01" =>
+
+------------------------------------------------------------------------------
+--
+-- CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+ Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+ Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+ case IRB is
+ when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+ |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+ |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+ |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+ |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+ |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+ |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+ |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+ -- RLC r
+ -- RL r
+ -- RRC r
+ -- RR r
+ -- SLA r
+ -- SRA r
+ -- SRL r
+ -- SLL r (Undocumented) / SWAP r
+ if MCycle = "001" then
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+ -- RLC (HL)
+ -- RL (HL)
+ -- RRC (HL)
+ -- RR (HL)
+ -- SRA (HL)
+ -- SRL (HL)
+ -- SLA (HL)
+ -- SLL (HL) (Undocumented) / SWAP (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others =>
+ end case;
+ when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+ |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+ |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+ |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+ |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+ |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+ |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+ |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+ -- BIT b,r
+ if MCycle = "001" then
+ Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+ ALU_Op <= "1001";
+ end if;
+ when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+ -- BIT b,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1001";
+ TStates <= "100";
+ when others =>
+ end case;
+ when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+ |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+ |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+ |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+ |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+ |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+ |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+ |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+ -- SET b,r
+ if MCycle = "001" then
+ ALU_Op <= "1010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+ -- SET b,(HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others =>
+ end case;
+ when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+ |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+ |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+ |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+ |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+ -- RES b,r
+ if MCycle = "001" then
+ ALU_Op <= "1011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+ -- RES b,(HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others =>
+ end case;
+ end case;
+
+ when others =>
+
+------------------------------------------------------------------------------
+--
+-- ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+ case IRB is
+ when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+ |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+ |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+ |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+ |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+ |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+ |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+ |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+ |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+ | "10100100"|"10100101"|"10100110"|"10100111"
+ | "10101100"|"10101101"|"10101110"|"10101111"
+ | "10110100"|"10110101"|"10110110"|"10110111"
+ | "10111100"|"10111101"|"10111110"|"10111111"
+ |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+ |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+ |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+ |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+ |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+ |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+ |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+ |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+ null; -- NOP, undocumented
+ when "01111110"|"01111111" =>
+ -- NOP, undocumented
+ null;
+-- 8 BIT LOAD GROUP
+ when "01010111" =>
+ -- LD A,I
+ Special_LD <= "100";
+ TStates <= "101";
+ when "01011111" =>
+ -- LD A,R
+ Special_LD <= "101";
+ TStates <= "101";
+ when "01000111" =>
+ -- LD I,A
+ Special_LD <= "110";
+ TStates <= "101";
+ when "01001111" =>
+ -- LD R,A
+ Special_LD <= "111";
+ TStates <= "101";
+-- 16 BIT LOAD GROUP
+ when "01001011"|"01011011"|"01101011"|"01111011" =>
+ -- LD dd,(nn)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Read_To_Reg <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusA_To <= "1000";
+ else
+ Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusA_To(0) <= '1';
+ end if;
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Read_To_Reg <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusA_To <= "1001";
+ else
+ Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+ when "01000011"|"01010011"|"01100011"|"01110011" =>
+ -- LD (nn),dd
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusB_To <= "1000";
+ else
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusB_To <= "1001";
+ else
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '0';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "10100000" | "10101000" | "10110000" | "10111000" =>
+ -- LDI, LDD, LDIR, LDDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ IncDec_16 <= "1100"; -- BC
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "0000";
+ Set_Addr_To <= aDE;
+ if IR(3) = '0' then
+ IncDec_16 <= "0110"; -- IX
+ else
+ IncDec_16 <= "1110";
+ end if;
+ when 3 =>
+ I_BT <= '1';
+ TStates <= "101";
+ Write <= '1';
+ if IR(3) = '0' then
+ IncDec_16 <= "0101"; -- DE
+ else
+ IncDec_16 <= "1101";
+ end if;
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "10100001" | "10101001" | "10110001" | "10111001" =>
+ -- CPI, CPD, CPIR, CPDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ IncDec_16 <= "1100"; -- BC
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "0111";
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ if IR(3) = '0' then
+ IncDec_16 <= "0110";
+ else
+ IncDec_16 <= "1110";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ I_BC <= '1';
+ TStates <= "101";
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+ -- NEG
+ Alu_OP <= "0010";
+ Set_BusB_To <= "0111";
+ Set_BusA_To <= "1010";
+ Read_To_Acc <= '1';
+ Save_ALU <= '1';
+ when "01000110"|"01001110"|"01100110"|"01101110" =>
+ -- IM 0
+ IMode <= "00";
+ when "01010110"|"01110110" =>
+ -- IM 1
+ IMode <= "01";
+ when "01011110"|"01110111" =>
+ -- IM 2
+ IMode <= "10";
+-- 16 bit arithmetic
+ when "01001010"|"01011010"|"01101010"|"01111010" =>
+ -- ADC HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0001";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '0';
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ when others =>
+ end case;
+ when "01000010"|"01010010"|"01100010"|"01110010" =>
+ -- SBC HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ when 3 =>
+ NoRead <= '1';
+ ALU_Op <= "0011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ when others =>
+ end case;
+ when "01101111" =>
+ -- RLD
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ Set_Addr_To <= aXY;
+ when 3 =>
+ Read_To_Reg <= '1';
+ Set_BusB_To(2 downto 0) <= "110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1101";
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Save_ALU <= '1';
+ when 4 =>
+ I_RLD <= '1';
+ Write <= '1';
+ when others =>
+ end case;
+ when "01100111" =>
+ -- RRD
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Set_Addr_To <= aXY;
+ when 3 =>
+ Read_To_Reg <= '1';
+ Set_BusB_To(2 downto 0) <= "110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1110";
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Save_ALU <= '1';
+ when 4 =>
+ I_RRD <= '1';
+ Write <= '1';
+ when others =>
+ end case;
+ when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+ -- RETI, RETN
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ I_RETN <= '1';
+ when others => null;
+ end case;
+ when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+ -- IN r,(C)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ IORQ <= '1';
+ if IR(5 downto 3) /= "110" then
+ Read_To_Reg <= '1';
+ Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+ end if;
+ I_INRC <= '1';
+ when others =>
+ end case;
+ when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+ -- OUT (C),r
+ -- OUT (C),0
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To(2 downto 0) <= IR(5 downto 3);
+ if IR(5 downto 3) = "110" then
+ Set_BusB_To(3) <= '1';
+ end if;
+ when 2 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "10100010" | "10101010" | "10110010" | "10111010" =>
+ -- INI, IND, INIR, INDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "1010";
+ Set_BusA_To <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ IORQ <= '1';
+ Set_BusB_To <= "0110";
+ Set_Addr_To <= aXY;
+ when 3 =>
+ if IR(3) = '0' then
+ IncDec_16 <= "0010";
+ else
+ IncDec_16 <= "1010";
+ end if;
+ TStates <= "100";
+ Write <= '1';
+ I_BTR <= '1';
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "10100011" | "10101011" | "10110011" | "10111011" =>
+ -- OUTI, OUTD, OTIR, OTDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "1010";
+ Set_BusA_To <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_Addr_To <= aBC;
+ when 3 =>
+ if IR(3) = '0' then
+ IncDec_16 <= "0010";
+ else
+ IncDec_16 <= "1010";
+ end if;
+ IORQ <= '1';
+ Write <= '1';
+ I_BTR <= '1';
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end case;
+
+ end case;
+
+ if Mode = 1 then
+ if MCycle = "001" then
+-- TStates <= "100";
+ else
+ TStates <= "011";
+ end if;
+ end if;
+
+ if Mode = 3 then
+ if MCycle = "001" then
+-- TStates <= "100";
+ else
+ TStates <= "100";
+ end if;
+ end if;
+
+ if Mode < 2 then
+ if MCycle = "110" then
+ Inc_PC <= '1';
+ if Mode = 1 then
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ end if;
+ if IRB = "00110110" or IRB = "11001011" then
+ Set_Addr_To <= aNone;
+ end if;
+ end if;
+ if MCycle = "111" then
+ if Mode = 0 then
+ TStates <= "101";
+ end if;
+ if ISet /= "01" then
+ Set_Addr_To <= aXY;
+ end if;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ if IRB = "00110110" or ISet = "01" then
+ -- LD (HL),n
+ Inc_PC <= '1';
+ else
+ NoRead <= '1';
+ end if;
+ end if;
+ end if;
+
+ end process;
+
+end;
--- /dev/null
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+ component T80
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ IORQ : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DInst : in std_logic_vector(7 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0);
+ MC : out std_logic_vector(2 downto 0);
+ TS : out std_logic_vector(2 downto 0);
+ IntCycle_n : out std_logic;
+ IntE : out std_logic;
+ Stop : out std_logic
+ );
+ end component;
+
+ component T80_Reg
+ port(
+ Clk : in std_logic;
+ CEN : in std_logic;
+ WEH : in std_logic;
+ WEL : in std_logic;
+ AddrA : in std_logic_vector(2 downto 0);
+ AddrB : in std_logic_vector(2 downto 0);
+ AddrC : in std_logic_vector(2 downto 0);
+ DIH : in std_logic_vector(7 downto 0);
+ DIL : in std_logic_vector(7 downto 0);
+ DOAH : out std_logic_vector(7 downto 0);
+ DOAL : out std_logic_vector(7 downto 0);
+ DOBH : out std_logic_vector(7 downto 0);
+ DOBL : out std_logic_vector(7 downto 0);
+ DOCH : out std_logic_vector(7 downto 0);
+ DOCL : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component T80_MCode
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ IR : in std_logic_vector(7 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ MCycle : in std_logic_vector(2 downto 0);
+ F : in std_logic_vector(7 downto 0);
+ NMICycle : in std_logic;
+ IntCycle : in std_logic;
+ MCycles : out std_logic_vector(2 downto 0);
+ TStates : out std_logic_vector(2 downto 0);
+ Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+ Inc_PC : out std_logic;
+ Inc_WZ : out std_logic;
+ IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
+ Read_To_Reg : out std_logic;
+ Read_To_Acc : out std_logic;
+ Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+ Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+ ALU_Op : out std_logic_vector(3 downto 0);
+ -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+ Save_ALU : out std_logic;
+ PreserveC : out std_logic;
+ Arith16 : out std_logic;
+ Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+ IORQ : out std_logic;
+ Jump : out std_logic;
+ JumpE : out std_logic;
+ JumpXY : out std_logic;
+ Call : out std_logic;
+ RstP : out std_logic;
+ LDZ : out std_logic;
+ LDW : out std_logic;
+ LDSPHL : out std_logic;
+ Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+ ExchangeDH : out std_logic;
+ ExchangeRp : out std_logic;
+ ExchangeAF : out std_logic;
+ ExchangeRS : out std_logic;
+ I_DJNZ : out std_logic;
+ I_CPL : out std_logic;
+ I_CCF : out std_logic;
+ I_SCF : out std_logic;
+ I_RETN : out std_logic;
+ I_BT : out std_logic;
+ I_BC : out std_logic;
+ I_BTR : out std_logic;
+ I_RLD : out std_logic;
+ I_RRD : out std_logic;
+ I_INRC : out std_logic;
+ SetDI : out std_logic;
+ SetEI : out std_logic;
+ IMode : out std_logic_vector(1 downto 0);
+ Halt : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic
+ );
+ end component;
+
+ component T80_ALU
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ Arith16 : in std_logic;
+ Z16 : in std_logic;
+ ALU_Op : in std_logic_vector(3 downto 0);
+ IR : in std_logic_vector(5 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ BusA : in std_logic_vector(7 downto 0);
+ BusB : in std_logic_vector(7 downto 0);
+ F_In : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ F_Out : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+end;
--- /dev/null
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0242 : Initial release
+--
+-- 0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+ port(
+ Clk : in std_logic;
+ CEN : in std_logic;
+ WEH : in std_logic;
+ WEL : in std_logic;
+ AddrA : in std_logic_vector(2 downto 0);
+ AddrB : in std_logic_vector(2 downto 0);
+ AddrC : in std_logic_vector(2 downto 0);
+ DIH : in std_logic_vector(7 downto 0);
+ DIL : in std_logic_vector(7 downto 0);
+ DOAH : out std_logic_vector(7 downto 0);
+ DOAL : out std_logic_vector(7 downto 0);
+ DOBH : out std_logic_vector(7 downto 0);
+ DOBL : out std_logic_vector(7 downto 0);
+ DOCH : out std_logic_vector(7 downto 0);
+ DOCL : out std_logic_vector(7 downto 0)
+ );
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+ type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+ signal RegsH : Register_Image(0 to 7);
+ signal RegsL : Register_Image(0 to 7);
+
+begin
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if CEN = '1' then
+ if WEH = '1' then
+ RegsH(to_integer(unsigned(AddrA))) <= DIH;
+ end if;
+ if WEL = '1' then
+ RegsL(to_integer(unsigned(AddrA))) <= DIL;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ DOAH <= RegsH(to_integer(unsigned(AddrA)));
+ DOAL <= RegsL(to_integer(unsigned(AddrA)));
+ DOBH <= RegsH(to_integer(unsigned(AddrB)));
+ DOBL <= RegsL(to_integer(unsigned(AddrB)));
+ DOCH <= RegsH(to_integer(unsigned(AddrC)));
+ DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
--- /dev/null
+------------------------------------------------------------------------------
+-- t80as.vhd : The non-tristate signal edition of t80a.vhd
+--
+-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
+--
+-- 1.separate 'D' to 'DO' and 'DI'.
+-- 2.added 'DOE' to 'DO' enable signal.(data direction)
+-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'.
+--
+-- There is a mark of "--AS" in all the change points.
+--
+------------------------------------------------------------------------------
+
+--
+-- Z80 compatible microprocessor core, asynchronous top level
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0211 : Fixed interrupt cycle
+--
+-- 0235 : Updated for T80 interface change
+--
+-- 0238 : Updated for T80 interface change
+--
+-- 0240 : Updated for T80 interface change
+--
+-- 0242 : Updated for T80 interface change
+--
+-- 0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80as is
+ generic(
+ Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+--AS-- D : inout std_logic_vector(7 downto 0)
+--AS>>
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0);
+ DOE : out std_logic
+--<<AS
+ );
+end T80as;
+
+architecture rtl of T80as is
+
+ signal CEN : std_logic;
+ signal Reset_s : std_logic;
+ signal IntCycle_n : std_logic;
+ signal IORQ : std_logic;
+ signal NoRead : std_logic;
+ signal Write : std_logic;
+ signal MREQ : std_logic;
+ signal MReq_Inhibit : std_logic;
+ signal Req_Inhibit : std_logic;
+ signal RD : std_logic;
+ signal MREQ_n_i : std_logic;
+ signal IORQ_n_i : std_logic;
+ signal RD_n_i : std_logic;
+ signal WR_n_i : std_logic;
+ signal RFSH_n_i : std_logic;
+ signal BUSAK_n_i : std_logic;
+ signal A_i : std_logic_vector(15 downto 0);
+--AS-- signal DO : std_logic_vector(7 downto 0);
+ signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
+ signal Wait_s : std_logic;
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal TState : std_logic_vector(2 downto 0);
+
+begin
+
+ CEN <= '1';
+
+ BUSAK_n <= BUSAK_n_i;
+ MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
+ RD_n_i <= not RD or Req_Inhibit;
+
+--AS-- MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
+--AS-- IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
+--AS-- RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
+--AS-- WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
+--AS-- RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
+--AS-- A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
+--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
+--AS>>
+ MREQ_n <= MREQ_n_i;
+ IORQ_n <= IORQ_n_i;
+ RD_n <= RD_n_i;
+ WR_n <= WR_n_i;
+ RFSH_n <= RFSH_n_i;
+ A <= A_i;
+ DOE <= Write when BUSAK_n_i = '1' else '0';
+--<<AS
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ Reset_s <= '0';
+ elsif CLK_n'event and CLK_n = '1' then
+ Reset_s <= '1';
+ end if;
+ end process;
+
+ u0 : T80
+ generic map(
+ Mode => Mode,
+ IOWait => 1)
+ port map(
+ CEN => CEN,
+ M1_n => M1_n,
+ IORQ => IORQ,
+ NoRead => NoRead,
+ Write => Write,
+ RFSH_n => RFSH_n_i,
+ HALT_n => HALT_n,
+ WAIT_n => Wait_s,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ RESET_n => Reset_s,
+ BUSRQ_n => BUSRQ_n,
+ BUSAK_n => BUSAK_n_i,
+ CLK_n => CLK_n,
+ A => A_i,
+-- DInst => D,
+ DInst => DI,
+ DI => DI_Reg,
+ DO => DO,
+ MC => MCycle,
+ TS => TState,
+ IntCycle_n => IntCycle_n);
+
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '0' then
+ Wait_s <= WAIT_n;
+ if TState = "011" and BUSAK_n_i = '1' then
+--AS-- DI_Reg <= to_x01(D);
+--AS>>
+ DI_Reg <= to_x01(DI);
+--<<AS
+ end if;
+ end if;
+ end process;
+
+ process (Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ WR_n_i <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ WR_n_i <= '1';
+ if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
+ WR_n_i <= not Write;
+ end if;
+ end if;
+ end process;
+
+ process (Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ Req_Inhibit <= '0';
+ elsif CLK_n'event and CLK_n = '1' then
+ if MCycle = "001" and TState = "010" then
+ Req_Inhibit <= '1';
+ else
+ Req_Inhibit <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ MReq_Inhibit <= '0';
+ elsif CLK_n'event and CLK_n = '0' then
+ if MCycle = "001" and TState = "010" then
+ MReq_Inhibit <= '1';
+ else
+ MReq_Inhibit <= '0';
+ end if;
+ end if;
+ end process;
+
+ process(Reset_s,CLK_n)
+ begin
+ if Reset_s = '0' then
+ RD <= '0';
+ IORQ_n_i <= '1';
+ MREQ <= '0';
+ elsif CLK_n'event and CLK_n = '0' then
+
+ if MCycle = "001" then
+ if TState = "001" then
+ RD <= IntCycle_n;
+ MREQ <= IntCycle_n;
+ IORQ_n_i <= IntCycle_n;
+ end if;
+ if TState = "011" then
+ RD <= '0';
+ IORQ_n_i <= '1';
+ MREQ <= '1';
+ end if;
+ if TState = "100" then
+ MREQ <= '0';
+ end if;
+ else
+ if TState = "001" and NoRead = '0' then
+ RD <= not Write;
+ IORQ_n_i <= not IORQ;
+ MREQ <= not IORQ;
+ end if;
+ if TState = "011" then
+ RD <= '0';
+ IORQ_n_i <= '1';
+ MREQ <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+end;
projects / fpga-games / commitdiff