change timing for rom access
[fpga-games] / galaxian / src / mc_top.v
1 //===============================================================================
2 // FPGA GALAXIAN TOP
3 //
4 // Version : 2.50
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 // 2004- 4-30 galaxian modify by K.DEGAWA
15 // 2004- 5- 6 first release.
16 // 2004- 8-23 Improvement with T80-IP.
17 // 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.
18 // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
19 //================================================================================
20
21 `include "src/mc_conf.v"
22
23 module mc_top(
24
25 // FPGA_USE
26 I_CLK_125M,
27
28 `ifdef PSPAD_USE
29 // PS_PAD interface
30 psCLK,
31 psSEL,
32 psTXD,
33 psRXD,
34 `endif
35
36 // ROM IF
37 //O_ROM_AB,
38 //I_ROM_DB,
39 //O_ROM_OEn,
40 //O_ROM_CSn,
41 //O_ROM_WEn,
42
43 // INPORT SW IF
44 I_PSW,
45
46 // SOUND OUT
47 O_SOUND_OUT_L,
48 O_SOUND_OUT_R,
49
50 // VGA (VIDEO) IF
51 O_VGA_R,
52 O_VGA_G,
53 O_VGA_B,
54 O_VGA_H_SYNCn,
55 O_VGA_V_SYNCn
56
57 );
58
59 // FPGA_USE
60 input I_CLK_125M;
61
62 // CPU ADDRESS BUS
63 wire [15:0]W_A;
64 // CPU IF
65 wire W_CPU_RDn;
66 wire W_CPU_WRn;
67 wire W_CPU_MREQn;
68 wire W_CPU_RFSHn;
69 wire W_CPU_BUSAKn;
70 wire W_CPU_IORQn;
71 wire W_CPU_M1n;
72 wire W_CPU_CLK;
73 wire W_CPU_HRDWR_RESETn;
74 wire W_CPU_WAITn;
75 wire W_CPU_NMIn;
76
77 `ifdef PSPAD_USE
78 // PS_PAD interface
79 input psRXD;
80 output psTXD,psCLK,psSEL;
81 `endif
82
83 // ROM IF
84 //output [18:0]O_ROM_AB;
85 //input [7:0]I_ROM_DB;
86 //output O_ROM_OEn;
87 //output O_ROM_CSn;
88 //output O_ROM_WEn;
89
90 // INPORT SW IF
91 input [8:0]I_PSW;
92
93 // SOUND OUT
94 output O_SOUND_OUT_L;
95 output O_SOUND_OUT_R;
96
97 // VGA (VIDEO) IF
98 output [3:0]O_VGA_R;
99 output [3:0]O_VGA_G;
100 output [3:0]O_VGA_B;
101 output O_VGA_H_SYNCn;
102 output O_VGA_V_SYNCn;
103
104 wire W_RESETn = |(~I_PSW[8:5]);
105 //------ CLOCK GEN ---------------------------
106 wire I_CLK_18432M;
107 wire W_CLK_12M,WB_CLK_12M;
108 wire W_CLK_6M,WB_CLK_6M;
109 wire W_STARS_CLK;
110 wire W_ROM_CLK;
111
112 mc_dcm clockgen(
113 .CLKIN_IN(I_CLK_125M),
114 .RST_IN(! W_RESETn),
115 .CLKFX_OUT(I_CLK_18432M),
116 .CLK0_OUT(W_ROM_CLK)
117 );
118
119 //------ H&V COUNTER -------------------------
120 wire [8:0]W_H_CNT;
121 wire [7:0]W_V_CNT;
122 wire W_H_BL;
123 wire W_V_BLn;
124 wire W_C_BLn;
125 wire W_H_SYNC;
126 wire W_V_SYNC;
127
128 //------ CPU RAM ----------------------------
129 wire [7:0]W_CPU_RAM_DO;
130
131 //------ ADDRESS DECDER ----------------------
132 wire W_CPU_ROM_CSn;
133 wire W_CPU_RAM_RDn;
134 wire W_CPU_RAM_WRn;
135 wire W_CPU_RAM_CSn;
136 wire W_OBJ_RAM_RDn;
137 wire W_OBJ_RAM_WRn;
138 wire W_OBJ_RAM_RQn;
139 wire W_VID_RAM_RDn;
140 wire W_VID_RAM_WRn;
141 wire W_SW0_OEn;
142 wire W_SW1_OEn;
143 wire W_DIP_OEn;
144 wire W_WDR_OEn;
145 wire W_LAMP_WEn;
146 wire W_SOUND_WEn;
147 wire W_PITCHn;
148 wire W_H_FLIP;
149 wire W_V_FLIP;
150 wire W_BD_G;
151 wire W_STARS_ON;
152
153 wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;
154 wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;
155 //------- INPORT -----------------------------
156 wire [7:0]W_SW_DO;
157 //------- VIDEO -----------------------------
158 wire [7:0]W_VID_DO;
159 //--------------------------------------------
160
161 mc_clock MC_CLK(
162
163 .I_CLK_18M(I_CLK_18432M),
164 .O_CLK_12M(WB_CLK_12M),
165 .O_CLK_06M(WB_CLK_6M)
166
167 );
168
169 `ifdef DEVICE_CYCLONE
170 assign W_CLK_12M = WB_CLK_12M;
171 assign W_CLK_6M = WB_CLK_6M;
172 `endif
173 `ifdef DEVICE_SPARTAN2E
174 BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );
175 BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );
176 `endif
177 //--- DATA I/F -------------------------------------
178 reg [7:0]W_CPU_ROM_DO;
179 wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;
180
181 wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;
182 wire [7:0]W_BDI;
183
184 //--- CPU I/F -------------------------------------
185 reg [3:0]rst_count;
186 always@(posedge W_H_CNT[0] or negedge W_RESETn)
187 begin
188 if(! W_RESETn) rst_count <= 0;
189 else begin
190 if( rst_count == 15)
191 rst_count <= rst_count;
192 else
193 rst_count <= rst_count+1;
194 end
195 end
196
197 assign W_CPU_RESETn = W_RESETn;
198 assign W_CPU_CLK = W_H_CNT[0];
199
200 Z80IP CPU(
201
202 .CLK(W_CPU_CLK),
203 .RESET_N(W_CPU_RESETn),
204 .INT_N(1'b1),
205 .NMI_N(W_CPU_NMIn),
206 .ADRS(W_A),
207 .DOUT(W_BDI),
208 .DINP(W_BDO),
209 .M1_N(),
210 .MREQ_N(W_CPU_MREQn),
211 .IORQ_N(),
212 .RD_N(W_CPU_RDn ),
213 .WR_N(W_CPU_WRn ),
214 .WAIT_N(W_CPU_WAITn),
215 .BUSWO(),
216 .RFSH_N(W_CPU_RFSHn),
217 .HALT_N()
218
219 );
220
221 wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;
222
223 mc_cpu_ram MC_CPU_RAM(
224
225 .I_CLK(W_CPU_RAM_CLK),
226 .I_ADDR(W_A[9:0]),
227 .I_D(W_BDI),
228 .I_WE(~W_CPU_WRn),
229 .I_OE(~W_CPU_RAM_RDn ),
230 .O_D(W_CPU_RAM_DO)
231
232 );
233
234
235 mc_adec MC_ADEC(
236
237 .I_CLK_12M(W_CLK_12M),
238 .I_CLK_6M(W_CLK_6M),
239 .I_CPU_CLK(W_H_CNT[0]),
240 .I_RSTn(W_RESETn),
241
242 .I_CPU_A(W_A),
243 .I_CPU_D(W_BDI[0]),
244 .I_MREQn(W_CPU_MREQn),
245 .I_RFSHn(W_CPU_RFSHn),
246 .I_RDn(W_CPU_RDn),
247 .I_WRn(W_CPU_WRn),
248 .I_H_BL(W_H_BL),
249 .I_V_BLn(W_V_BLn),
250
251 .O_WAITn(W_CPU_WAITn),
252 .O_NMIn(W_CPU_NMIn),
253 .O_CPU_ROM_CSn(W_CPU_ROM_CSn),
254 .O_CPU_RAM_RDn(W_CPU_RAM_RDn),
255 .O_CPU_RAM_WRn(W_CPU_RAM_WRn),
256 .O_CPU_RAM_CSn(W_CPU_RAM_CSn),
257 .O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
258 .O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
259 .O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
260 .O_VID_RAM_RDn(W_VID_RAM_RDn),
261 .O_VID_RAM_WRn(W_VID_RAM_WRn),
262 .O_SW0_OEn(W_SW0_OEn),
263 .O_SW1_OEn(W_SW1_OEn),
264 .O_DIP_OEn(W_DIP_OEn),
265 .O_WDR_OEn(W_WDR_OEn),
266 .O_LAMP_WEn(W_LAMP_WEn),
267 .O_SOUND_WEn(W_SOUND_WEn),
268 .O_PITCHn(W_PITCHn),
269 .O_H_FLIP(W_H_FLIP),
270 .O_V_FLIP(W_V_FLIP),
271 .O_BD_G(W_BD_G),
272 .O_STARS_ON(W_STARS_ON)
273
274 );
275
276 //-------- SOUND I/F -----------------------------
277 //--- Parts 9L ---------
278 reg [7:0]W_9L_Q;
279 always@(posedge W_CLK_12M or negedge W_RESETn)
280 begin
281 if(W_RESETn == 1'b0)begin
282 W_9L_Q <= 0;
283 end
284 else begin
285 if(W_SOUND_WEn == 1'b0)begin
286 case(W_A[2:0])
287 3'h0 : W_9L_Q[0] <= W_BDI[0];
288 3'h1 : W_9L_Q[1] <= W_BDI[0];
289 3'h2 : W_9L_Q[2] <= W_BDI[0];
290 3'h3 : W_9L_Q[3] <= W_BDI[0];
291 3'h4 : W_9L_Q[4] <= W_BDI[0];
292 3'h5 : W_9L_Q[5] <= W_BDI[0];
293 3'h6 : W_9L_Q[6] <= W_BDI[0];
294 3'h7 : W_9L_Q[7] <= W_BDI[0];
295 endcase
296 end
297 end
298 end
299 wire W_VOL1 = W_9L_Q[6];
300 wire W_VOL2 = W_9L_Q[7];
301 wire W_FIRE = W_9L_Q[5];
302 wire W_HIT = W_9L_Q[3];
303 wire W_FS3 = W_9L_Q[2];
304 wire W_FS2 = W_9L_Q[1];
305 wire W_FS1 = W_9L_Q[0];
306 //---------------------------------------------------
307 //---- CPU DATA WATCH -------------------------------
308 wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;
309
310 reg [1:0]on_game;
311 always @(posedge W_CPU_CLK)
312 begin
313 if(~ZMWR)begin
314 if(W_A == 16'h4007)begin
315 if(W_BDI == 8'h00)
316 on_game[0] <= 1;
317 else
318 on_game[0] <= 0;
319 end
320 if(W_A == 16'h4005)begin
321 if(W_BDI == 8'h03 || W_BDI == 8'h04 )
322 on_game[1] <= 1;
323 else
324 on_game[1] <= 0;
325 end
326 end
327 end
328
329 `ifdef PSPAD_USE
330 reg died;
331 always @(posedge W_CPU_CLK)
332 begin
333 if(~ZMWR)begin
334 if(W_A == 16'h4206)begin
335 if(W_BDI == 8'h00)
336 died <= 0;
337 else
338 died <= 1;
339 end
340 end
341 end
342 //---- PS_PAD Interface -----------------------------
343 wire [8:0]ps_PSW;
344 wire VIB_SW = died & (&on_game[1:0]);
345
346 fpga_arcade_if pspad(
347
348 .CLK_18M432(I_CLK_18432M),
349 .I_RSTn(W_RESETn),
350 .psCLK(psCLK),
351 .psSEL(psSEL),
352 .psTXD(psTXD),
353 .psRXD(psRXD),
354 .ps_PSW(ps_PSW),
355 .I_VIB_SW(VIB_SW)
356
357 );
358 `endif
359 //---- SW Interface ---------------------------------
360 `ifdef PSPAD_USE
361 wire L1 = I_PSW[2] & ps_PSW[2];
362 wire R1 = I_PSW[3] & ps_PSW[3];
363 wire U1 = I_PSW[0];
364 wire D1 = I_PSW[1];
365 wire J1 = I_PSW[4] & ps_PSW[8];
366
367 wire S1 = (U1|J1) & ps_PSW[6];
368 wire S2 = (D1|J1) & ps_PSW[7];
369
370 wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];
371 `else
372 wire L1 = ! I_PSW[2];
373 wire R1 = ! I_PSW[3];
374 wire U1 = ! I_PSW[0];
375 wire D1 = ! I_PSW[1];
376 wire J1 = ! I_PSW[4];
377
378 wire S1 = ! I_PSW[5];
379 wire S2 = ! I_PSW[7];
380
381 wire C1 = ! I_PSW[6];
382 `endif
383 wire C2 = ! I_PSW[8];
384
385 wire L2 = L1;
386 wire R2 = R1;
387 wire U2 = U1;
388 wire D2 = D1;
389 wire J2 = J1;
390
391 mc_inport MC_INPORT(
392
393 .I_COIN1(~C1), // ACTIVE HI
394 .I_COIN2(~C2), // ACTIVE HI
395 .I_1P_LE(~L1), // ACTIVE HI
396 .I_1P_RI(~R1), // ACTIVE HI
397 .I_1P_SH(~J1), // ACTIVE HI
398 .I_2P_LE(~L2), // ACTIVE HI
399 .I_2P_RI(~R2), // ACTIVE HI
400 .I_2P_SH(~J2), // ACTIVE HI
401 .I_1P_START(~S1), // ACTIVE HI
402 .I_2P_START(~S2), // ACTIVE HI
403
404 .I_SW0_OEn(W_SW0_OEn),
405 .I_SW1_OEn(W_SW1_OEn),
406 .I_DIP_OEn(W_DIP_OEn),
407
408 .O_D(W_SW_DO)
409
410 );
411
412 //-----------------------------------------------------------------------------
413 //------- ROM -------------------------------------------------------
414 reg [18:0]ROM_A;
415 wire [10:0]W_OBJ_ROM_A;
416 reg [7:0]W_OBJ_ROM_A_D;
417 reg [7:0]W_OBJ_ROM_B_D;
418
419 wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;
420 reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;
421
422 wire [7:0]ROM_D; // = I_ROM_DB;
423 //assign O_ROM_AB = ROM_A;
424
425 //assign O_ROM_OEn = 1'b0;
426 //assign O_ROM_CSn = 1'b0;
427 //assign O_ROM_WEn = 1'b1;
428
429 galaxian_roms ROMS(
430 .I_ROM_CLK(W_ROM_CLK),
431 .I_ADDR(ROM_A),
432 .O_DATA(ROM_D)
433 );
434
435
436 reg [1:0]clk_d;
437 reg [4:0]seq;
438 always @(posedge I_CLK_18432M)
439 begin
440 // 24 phase generator
441 clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];
442 clk_d[1] <= clk_d[0];
443 seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;
444 case(seq)
445 0:begin
446 ROM_A <= W_WAV_A0;
447 W_CPU_ROM_DO <= ROM_D;
448 end
449 2:begin
450 ROM_A <= W_WAV_A1;
451 W_WAV_D0 <= ROM_D;
452 end
453 4:begin
454 ROM_A <= {3'h0,W_A[15:0]};
455 W_WAV_D1 <= ROM_D;
456 end
457 6:begin
458 ROM_A <= W_WAV_A2;
459 W_CPU_ROM_DO <= ROM_D;
460 end
461 8:W_WAV_D2 <= ROM_D;
462 10:ROM_A <= {3'h0,W_A[15:0]};
463 12:W_CPU_ROM_DO <= ROM_D;
464 14:ROM_A <= {3'h0,W_A[15:0]};
465 16:begin
466 ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};
467 W_CPU_ROM_DO <= ROM_D;
468 end
469 18:begin
470 ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};
471 W_OBJ_ROM_A_D <= ROM_D;
472 end
473 20:begin
474 ROM_A <= {3'h0,W_A[15:0]};
475 W_OBJ_ROM_B_D <= ROM_D;
476 end
477 default:;
478 endcase
479 end
480 //-----------------------------------------------------------------------------
481
482 wire W_V_BL2n;
483
484 mc_hv_count MC_HV(
485
486 .I_CLK(WB_CLK_6M),
487 .I_RSTn(W_RESETn),
488
489 .O_H_CNT(W_H_CNT),
490 .O_H_SYNC(W_H_SYNC),
491 .O_H_BL(W_H_BL),
492 .O_V_CNT(W_V_CNT),
493 .O_V_SYNC(W_V_SYNC),
494 .O_V_BL2n(W_V_BL2n),
495 .O_V_BLn(W_V_BLn),
496 .O_C_BLn(W_C_BLn)
497
498 );
499
500 //------ VIDEO -----------------------------
501 wire W_8HF;
502 wire W_1VF;
503 wire W_C_BLnX;
504 wire W_256HnX;
505 wire W_MISSILEn;
506 wire W_SHELLn;
507 wire [1:0]W_VID;
508 wire [2:0]W_COL;
509
510 mc_video MC_VID(
511 .I_CLK_18M(I_CLK_18432M),
512 .I_CLK_12M(W_CLK_12M),
513 .I_CLK_6M(W_CLK_6M),
514 .I_H_CNT(W_H_CNT),
515 .I_V_CNT(W_V_CNT),
516 .I_H_FLIP(W_H_FLIP),
517 .I_V_FLIP(W_V_FLIP),
518 .I_V_BLn(W_V_BLn),
519 .I_C_BLn(W_C_BLn),
520
521 .I_A(W_A[9:0]),
522 .I_OBJ_SUB_A(3'b000),
523 .I_BD(W_BDI),
524 .I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
525 .I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
526 .I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
527 .I_VID_RAM_RDn(W_VID_RAM_RDn),
528 .I_VID_RAM_WRn(W_VID_RAM_WRn),
529
530 .O_OBJ_ROM_A(W_OBJ_ROM_A),
531 .I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),
532 .I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),
533
534 .O_C_BLnX(W_C_BLnX),
535 .O_8HF(W_8HF),
536 .O_256HnX(W_256HnX),
537 .O_1VF(W_1VF),
538 .O_MISSILEn(W_MISSILEn),
539 .O_SHELLn(W_SHELLn),
540 .O_BD(W_VID_DO),
541 .O_VID(W_VID),
542 .O_COL(W_COL)
543
544 );
545
546 wire W_C_BLX;
547 wire W_STARS_OFFn;
548 wire [2:0]W_VIDEO_R;
549 wire [2:0]W_VIDEO_G;
550 wire [1:0]W_VIDEO_B;
551
552 mc_col_pal MC_COL_PAL(
553
554 .I_CLK_12M(W_CLK_12M),
555 .I_CLK_6M(W_CLK_6M),
556 .I_VID(W_VID),
557 .I_COL(W_COL),
558 .I_C_BLnX(W_C_BLnX),
559
560 .O_C_BLX(W_C_BLX),
561 .O_STARS_OFFn(W_STARS_OFFn),
562 .O_R(W_VIDEO_R),
563 .O_G(W_VIDEO_G),
564 .O_B(W_VIDEO_B)
565
566 );
567
568 wire [2:0]W_STARS_R;
569 wire [2:0]W_STARS_G;
570 wire [1:0]W_STARS_B;
571
572 mc_stars MC_STARS(
573
574 .I_CLK_18M(I_CLK_18432M),
575 `ifdef DEVICE_CYCLONE
576 .I_CLK_6M(~WB_CLK_6M),
577 `endif
578 `ifdef DEVICE_SPARTAN2E
579 .I_CLK_6M(WB_CLK_6M),
580 `endif
581 .I_H_FLIP(W_H_FLIP),
582 .I_V_SYNC(W_V_SYNC),
583 .I_8HF(W_8HF),
584 .I_256HnX(W_256HnX),
585 .I_1VF(W_1VF),
586 .I_2V(W_V_CNT[1]),
587 .I_STARS_ON(W_STARS_ON),
588 .I_STARS_OFFn(W_STARS_OFFn),
589
590 .O_R(W_STARS_R),
591 .O_G(W_STARS_G),
592 .O_B(W_STARS_B),
593 .O_NOISE()
594
595 );
596
597 wire [2:0]W_R;
598 wire [2:0]W_G;
599 wire [1:0]W_B;
600
601 mc_vedio_mix MIX(
602
603 .I_VID_R(W_VIDEO_R),
604 .I_VID_G(W_VIDEO_G),
605 .I_VID_B(W_VIDEO_B),
606 .I_STR_R(W_STARS_R),
607 .I_STR_G(W_STARS_G),
608 .I_STR_B(W_STARS_B),
609
610 .I_C_BLnXX(~W_C_BLX),
611 .I_C_BLX(W_C_BLX | ~W_V_BL2n),
612 .I_MISSILEn(W_MISSILEn),
613 .I_SHELLn(W_SHELLn),
614
615 .O_R(W_R),
616 .O_G(W_G),
617 .O_B(W_B)
618
619 );
620
621 wire [2:0]W_VGA_R;
622 wire [2:0]W_VGA_G;
623 wire [1:0]W_VGA_B;
624
625 `ifdef VGA_USE
626 mc_vga_if VGA(
627
628 // input
629 .I_CLK_1(W_CLK_6M),
630 .I_CLK_2(W_CLK_12M),
631 .I_R(W_R),
632 .I_G(W_G),
633 .I_B(W_B),
634 .I_H_SYNC(W_H_SYNC),
635 .I_V_SYNC(W_V_SYNC),
636 // output
637 .O_R(W_VGA_R),
638 .O_G(W_VGA_G),
639 .O_B(W_VGA_B),
640 .O_H_SYNCn(O_VGA_H_SYNCn),
641 .O_V_SYNCn(O_VGA_V_SYNCn)
642
643 );
644
645 `else
646
647 assign W_VGA_R[2:0] = W_R;
648
649 assign W_VGA_G[2:0] = W_G;
650
651 assign W_VGA_B[1:0] = W_B;
652
653 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED
654 assign O_VGA_H_SYNCn = ~W_H_SYNC ;
655 assign O_VGA_V_SYNCn = ~W_V_SYNC ;
656
657 `endif
658
659 assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};
660
661 assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};
662
663 assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};
664
665 wire [7:0]W_SDAT_A;
666
667 mc_sound_a MC_SOUND_A(
668
669 .I_CLK_12M(W_CLK_12M),
670 .I_CLK_6M(W_CLK_6M),
671 .I_H_CNT1(W_H_CNT[1]),
672 .I_BD(W_BDI),
673 .I_PITCHn(W_PITCHn),
674 .I_VOL1(W_VOL1),
675 .I_VOL2(W_VOL2),
676
677 .O_SDAT(W_SDAT_A),
678 .O_DO()
679
680 );
681
682 wire [7:0]W_SDAT_B;
683
684 mc_sound_b MC_SOUND_B(
685
686 .I_CLK1(I_CLK_18432M),
687 .I_CLK2(W_CLK_6M),
688 .I_RSTn(rst_count[3]),
689 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),
690
691 .O_WAV_A0(W_WAV_A0),
692 .O_WAV_A1(W_WAV_A1),
693 .O_WAV_A2(W_WAV_A2),
694 .I_WAV_D0(W_WAV_D0),
695 .I_WAV_D1(W_WAV_D1),
696 .I_WAV_D2(W_WAV_D2),
697
698 .O_SDAT(W_SDAT_B)
699
700 );
701
702 wire W_DAC_A;
703 wire W_DAC_B;
704
705 assign O_SOUND_OUT_L = W_DAC_A;
706 assign O_SOUND_OUT_R = W_DAC_B;
707
708 dac wav_dac_a(
709
710 .Clk(I_CLK_18432M),
711 .Reset(~W_RESETn),
712 .DACin(W_SDAT_A),
713 .DACout(W_DAC_A)
714
715 );
716
717 dac wav_dac_b(
718
719 .Clk(I_CLK_18432M),
720 .Reset(~W_RESETn),
721 .DACin(W_SDAT_B),
722 .DACout(W_DAC_B)
723
724 );
725
726
727 endmodule
728
Impressum, Datenschutz