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fix rom clock
author
Michael Gernoth
<michael@gernoth.net>
Tue, 29 Apr 2008 11:42:19 +0000
(13:42 +0200)
committer
Michael Gernoth
<michael@gernoth.net>
Tue, 29 Apr 2008 11:42:19 +0000
(13:42 +0200)
galaxian/src/roms.v
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diff --git
a/galaxian/src/roms.v
b/galaxian/src/roms.v
index 403302d11d6765a97aa817a4a2224de21c09f053..3a0cf4f68b0c124004405af2e1791f4773d5111f 100644
(file)
--- a/
galaxian/src/roms.v
+++ b/
galaxian/src/roms.v
@@
-45,7
+45,7
@@
wire [7:0]Y_ROM_D;
reg [10:0]Y_ROM_A;
GALAXIAN_Y Y_ROM(
reg [10:0]Y_ROM_A;
GALAXIAN_Y Y_ROM(
-.CLK(
YB
_CLK_12M),
+.CLK(
I
_CLK_12M),
.ADDR(Y_ROM_A),
.DATA(Y_ROM_D),
.ENA(1'b1)
.ADDR(Y_ROM_A),
.DATA(Y_ROM_D),
.ENA(1'b1)
@@
-56,7
+56,7
@@
wire [7:0]L_ROM_D;
reg [10:0]L_ROM_A;
GALAXIAN_7L L_ROM(
reg [10:0]L_ROM_A;
GALAXIAN_7L L_ROM(
-.CLK(
LB
_CLK_12M),
+.CLK(
I
_CLK_12M),
.ADDR(L_ROM_A),
.DATA(L_ROM_D),
.ENA(1'b1)
.ADDR(L_ROM_A),
.DATA(L_ROM_D),
.ENA(1'b1)
@@
-67,7
+67,7
@@
wire [7:0]K_ROM_D;
reg [10:0]K_ROM_A;
GALAXIAN_1K K_ROM(
reg [10:0]K_ROM_A;
GALAXIAN_1K K_ROM(
-.CLK(
KB
_CLK_12M),
+.CLK(
I
_CLK_12M),
.ADDR(K_ROM_A),
.DATA(K_ROM_D),
.ENA(1'b1)
.ADDR(K_ROM_A),
.DATA(K_ROM_D),
.ENA(1'b1)
@@
-78,7
+78,7
@@
wire [7:0]H_ROM_D;
reg [10:0]H_ROM_A;
GALAXIAN_1H H_ROM(
reg [10:0]H_ROM_A;
GALAXIAN_1H H_ROM(
-.CLK(
HB
_CLK_12M),
+.CLK(
I
_CLK_12M),
.ADDR(H_ROM_A),
.DATA(H_ROM_D),
.ENA(1'b1)
.ADDR(H_ROM_A),
.DATA(H_ROM_D),
.ENA(1'b1)
@@
-96,39
+96,39
@@
reg [7:0]DATA_OUT;
// 0x04000 - 0x047FF 1k.bin VID-ROM
// 0x05000 - 0x057FF 1h.bin VID-ROM
// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
// 0x04000 - 0x047FF 1k.bin VID-ROM
// 0x05000 - 0x057FF 1h.bin VID-ROM
// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
-always
@(posedge I_CLK_18432M)
+always
begin
if (I_ADDR <= 18'h7ff) begin
//u
U_ROM_A <= I_ADDR[10:0];
DATA_OUT <= U_ROM_D;
end
begin
if (I_ADDR <= 18'h7ff) begin
//u
U_ROM_A <= I_ADDR[10:0];
DATA_OUT <= U_ROM_D;
end
-
else
if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
+ if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
//v
V_ROM_A <= I_ADDR[10:0];
DATA_OUT <= V_ROM_D;
end
//v
V_ROM_A <= I_ADDR[10:0];
DATA_OUT <= V_ROM_D;
end
-
else
if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
+ if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
//w
W_ROM_A <= I_ADDR[10:0];
DATA_OUT <= W_ROM_D;
end
//w
W_ROM_A <= I_ADDR[10:0];
DATA_OUT <= W_ROM_D;
end
-
else
if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
+ if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
//y
Y_ROM_A <= I_ADDR[10:0];
DATA_OUT <= Y_ROM_D;
end
//y
Y_ROM_A <= I_ADDR[10:0];
DATA_OUT <= Y_ROM_D;
end
-
else
if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
+ if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
//7l
L_ROM_A <= I_ADDR[10:0];
DATA_OUT <= L_ROM_D;
end
//7l
L_ROM_A <= I_ADDR[10:0];
DATA_OUT <= L_ROM_D;
end
-
else
if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
+ if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
//1k
K_ROM_A <= I_ADDR[10:0];
DATA_OUT <= K_ROM_D;
end
//1k
K_ROM_A <= I_ADDR[10:0];
DATA_OUT <= K_ROM_D;
end
-
else
if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
+ if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
//1h
H_ROM_A <= I_ADDR[10:0];
DATA_OUT <= H_ROM_D;
//1h
H_ROM_A <= I_ADDR[10:0];
DATA_OUT <= H_ROM_D;
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