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Merge pull request #23 from holiman/master
[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23
24 static uint32_t iso14a_timeout;
25 uint8_t *trace = (uint8_t *) BigBuf+TRACE_OFFSET;
26 int rsamples = 0;
27 int traceLen = 0;
28 int tracing = TRUE;
29 uint8_t trigger = 0;
30 // the block number for the ISO14443-4 PCB
31 static uint8_t iso14_pcb_blocknum = 0;
32
33 //
34 // ISO14443 timing:
35 //
36 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
37 #define REQUEST_GUARD_TIME (7000/16 + 1)
38 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
39 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
40 // bool LastCommandWasRequest = FALSE;
41
42 //
43 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
44 //
45 // When the PM acts as reader and is receiving tag data, it takes
46 // 3 ticks delay in the AD converter
47 // 16 ticks until the modulation detector completes and sets curbit
48 // 8 ticks until bit_to_arm is assigned from curbit
49 // 8*16 ticks for the transfer from FPGA to ARM
50 // 4*16 ticks until we measure the time
51 // - 8*16 ticks because we measure the time of the previous transfer
52 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
53
54 // When the PM acts as a reader and is sending, it takes
55 // 4*16 ticks until we can write data to the sending hold register
56 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
57 // 8 ticks until the first transfer starts
58 // 8 ticks later the FPGA samples the data
59 // 1 tick to assign mod_sig_coil
60 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
61
62 // When the PM acts as tag and is receiving it takes
63 // 2 ticks delay in the RF part (for the first falling edge),
64 // 3 ticks for the A/D conversion,
65 // 8 ticks on average until the start of the SSC transfer,
66 // 8 ticks until the SSC samples the first data
67 // 7*16 ticks to complete the transfer from FPGA to ARM
68 // 8 ticks until the next ssp_clk rising edge
69 // 4*16 ticks until we measure the time
70 // - 8*16 ticks because we measure the time of the previous transfer
71 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
72
73 // The FPGA will report its internal sending delay in
74 uint16_t FpgaSendQueueDelay;
75 // the 5 first bits are the number of bits buffered in mod_sig_buf
76 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
77 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
78
79 // When the PM acts as tag and is sending, it takes
80 // 4*16 ticks until we can write data to the sending hold register
81 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
82 // 8 ticks until the first transfer starts
83 // 8 ticks later the FPGA samples the data
84 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
85 // + 1 tick to assign mod_sig_coil
86 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
87
88 // When the PM acts as sniffer and is receiving tag data, it takes
89 // 3 ticks A/D conversion
90 // 14 ticks to complete the modulation detection
91 // 8 ticks (on average) until the result is stored in to_arm
92 // + the delays in transferring data - which is the same for
93 // sniffing reader and tag data and therefore not relevant
94 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
95
96 // When the PM acts as sniffer and is receiving reader data, it takes
97 // 2 ticks delay in analogue RF receiver (for the falling edge of the
98 // start bit, which marks the start of the communication)
99 // 3 ticks A/D conversion
100 // 8 ticks on average until the data is stored in to_arm.
101 // + the delays in transferring data - which is the same for
102 // sniffing reader and tag data and therefore not relevant
103 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
104
105 //variables used for timing purposes:
106 //these are in ssp_clk cycles:
107 uint32_t NextTransferTime;
108 uint32_t LastTimeProxToAirStart;
109 uint32_t LastProxToAirDuration;
110
111
112
113 // CARD TO READER - manchester
114 // Sequence D: 11110000 modulation with subcarrier during first half
115 // Sequence E: 00001111 modulation with subcarrier during second half
116 // Sequence F: 00000000 no modulation with subcarrier
117 // READER TO CARD - miller
118 // Sequence X: 00001100 drop after half a period
119 // Sequence Y: 00000000 no drop
120 // Sequence Z: 11000000 drop at start
121 #define SEC_D 0xf0
122 #define SEC_E 0x0f
123 #define SEC_F 0x00
124 #define SEC_X 0x0c
125 #define SEC_Y 0x00
126 #define SEC_Z 0xc0
127
128 const uint8_t OddByteParity[256] = {
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
142 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
143 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
144 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
145 };
146
147
148 void iso14a_set_trigger(bool enable) {
149 trigger = enable;
150 }
151
152 void iso14a_clear_trace() {
153 memset(trace, 0x44, TRACE_SIZE);
154 traceLen = 0;
155 }
156
157 void iso14a_set_tracing(bool enable) {
158 tracing = enable;
159 }
160
161 void iso14a_set_timeout(uint32_t timeout) {
162 iso14a_timeout = timeout;
163 }
164
165 //-----------------------------------------------------------------------------
166 // Generate the parity value for a byte sequence
167 //
168 //-----------------------------------------------------------------------------
169 byte_t oddparity (const byte_t bt)
170 {
171 return OddByteParity[bt];
172 }
173
174 uint32_t GetParity(const uint8_t * pbtCmd, int iLen)
175 {
176 int i;
177 uint32_t dwPar = 0;
178
179 // Generate the parity bits
180 for (i = 0; i < iLen; i++) {
181 // and save them to a 32Bit word
182 dwPar |= ((OddByteParity[pbtCmd[i]]) << i);
183 }
184 return dwPar;
185 }
186
187 void AppendCrc14443a(uint8_t* data, int len)
188 {
189 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
190 }
191
192 // The function LogTrace() is also used by the iClass implementation in iClass.c
193 bool RAMFUNC LogTrace(const uint8_t * btBytes, uint8_t iLen, uint32_t timestamp, uint32_t dwParity, bool readerToTag)
194 {
195 if (!tracing) return FALSE;
196 // Return when trace is full
197 if (traceLen + sizeof(timestamp) + sizeof(dwParity) + iLen >= TRACE_SIZE) {
198 tracing = FALSE; // don't trace any more
199 return FALSE;
200 }
201
202 // Trace the random, i'm curious
203 trace[traceLen++] = ((timestamp >> 0) & 0xff);
204 trace[traceLen++] = ((timestamp >> 8) & 0xff);
205 trace[traceLen++] = ((timestamp >> 16) & 0xff);
206 trace[traceLen++] = ((timestamp >> 24) & 0xff);
207
208 if (!readerToTag) {
209 trace[traceLen - 1] |= 0x80;
210 }
211 trace[traceLen++] = ((dwParity >> 0) & 0xff);
212 trace[traceLen++] = ((dwParity >> 8) & 0xff);
213 trace[traceLen++] = ((dwParity >> 16) & 0xff);
214 trace[traceLen++] = ((dwParity >> 24) & 0xff);
215 trace[traceLen++] = iLen;
216 if (btBytes != NULL && iLen != 0) {
217 memcpy(trace + traceLen, btBytes, iLen);
218 }
219 traceLen += iLen;
220 return TRUE;
221 }
222
223 //=============================================================================
224 // ISO 14443 Type A - Miller decoder
225 //=============================================================================
226 // Basics:
227 // This decoder is used when the PM3 acts as a tag.
228 // The reader will generate "pauses" by temporarily switching of the field.
229 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
230 // The FPGA does a comparison with a threshold and would deliver e.g.:
231 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
232 // The Miller decoder needs to identify the following sequences:
233 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
234 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
235 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
236 // Note 1: the bitstream may start at any time. We therefore need to sync.
237 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
238 //-----------------------------------------------------------------------------
239 static tUart Uart;
240
241 // Lookup-Table to decide if 4 raw bits are a modulation.
242 // We accept two or three consecutive "0" in any position with the rest "1"
243 const bool Mod_Miller_LUT[] = {
244 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
245 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
246 };
247 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
248 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
249
250 void UartReset()
251 {
252 Uart.state = STATE_UNSYNCD;
253 Uart.bitCount = 0;
254 Uart.len = 0; // number of decoded data bytes
255 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
256 Uart.parityBits = 0; //
257 Uart.twoBits = 0x0000; // buffer for 2 Bits
258 Uart.highCnt = 0;
259 Uart.startTime = 0;
260 Uart.endTime = 0;
261 }
262
263
264 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
265 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
266 {
267
268 Uart.twoBits = (Uart.twoBits << 8) | bit;
269
270 if (Uart.state == STATE_UNSYNCD) { // not yet synced
271 if (Uart.highCnt < 7) { // wait for a stable unmodulated signal
272 if (Uart.twoBits == 0xffff) {
273 Uart.highCnt++;
274 } else {
275 Uart.highCnt = 0;
276 }
277 } else {
278 Uart.syncBit = 0xFFFF; // not set
279 // look for 00xx1111 (the start bit)
280 if ((Uart.twoBits & 0x6780) == 0x0780) Uart.syncBit = 7;
281 else if ((Uart.twoBits & 0x33C0) == 0x03C0) Uart.syncBit = 6;
282 else if ((Uart.twoBits & 0x19E0) == 0x01E0) Uart.syncBit = 5;
283 else if ((Uart.twoBits & 0x0CF0) == 0x00F0) Uart.syncBit = 4;
284 else if ((Uart.twoBits & 0x0678) == 0x0078) Uart.syncBit = 3;
285 else if ((Uart.twoBits & 0x033C) == 0x003C) Uart.syncBit = 2;
286 else if ((Uart.twoBits & 0x019E) == 0x001E) Uart.syncBit = 1;
287 else if ((Uart.twoBits & 0x00CF) == 0x000F) Uart.syncBit = 0;
288 if (Uart.syncBit != 0xFFFF) {
289 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
290 Uart.startTime -= Uart.syncBit;
291 Uart.endTime = Uart.startTime;
292 Uart.state = STATE_START_OF_COMMUNICATION;
293 }
294 }
295
296 } else {
297
298 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
299 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
300 UartReset();
301 Uart.highCnt = 6;
302 } else { // Modulation in first half = Sequence Z = logic "0"
303 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
304 UartReset();
305 Uart.highCnt = 6;
306 } else {
307 Uart.bitCount++;
308 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
309 Uart.state = STATE_MILLER_Z;
310 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
311 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
312 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
313 Uart.parityBits <<= 1; // make room for the parity bit
314 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
315 Uart.bitCount = 0;
316 Uart.shiftReg = 0;
317 }
318 }
319 }
320 } else {
321 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
322 Uart.bitCount++;
323 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
324 Uart.state = STATE_MILLER_X;
325 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
326 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
327 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
328 Uart.parityBits <<= 1; // make room for the new parity bit
329 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
330 Uart.bitCount = 0;
331 Uart.shiftReg = 0;
332 }
333 } else { // no modulation in both halves - Sequence Y
334 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
335 Uart.state = STATE_UNSYNCD;
336 if(Uart.len == 0 && Uart.bitCount > 0) { // if we decoded some bits
337 Uart.shiftReg >>= (9 - Uart.bitCount); // add them to the output
338 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
339 Uart.parityBits <<= 1; // no parity bit - add "0"
340 Uart.bitCount--; // last "0" was part of the EOC sequence
341 }
342 return TRUE;
343 }
344 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
345 UartReset();
346 Uart.highCnt = 6;
347 } else { // a logic "0"
348 Uart.bitCount++;
349 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
350 Uart.state = STATE_MILLER_Y;
351 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
352 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
353 Uart.parityBits <<= 1; // make room for the parity bit
354 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
355 Uart.bitCount = 0;
356 Uart.shiftReg = 0;
357 }
358 }
359 }
360 }
361
362 }
363
364 return FALSE; // not finished yet, need more data
365 }
366
367
368
369 //=============================================================================
370 // ISO 14443 Type A - Manchester decoder
371 //=============================================================================
372 // Basics:
373 // This decoder is used when the PM3 acts as a reader.
374 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
375 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
376 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
377 // The Manchester decoder needs to identify the following sequences:
378 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
379 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
380 // 8 ticks unmodulated: Sequence F = end of communication
381 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
382 // Note 1: the bitstream may start at any time. We therefore need to sync.
383 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
384 static tDemod Demod;
385
386 // Lookup-Table to decide if 4 raw bits are a modulation.
387 // We accept three or four "1" in any position
388 const bool Mod_Manchester_LUT[] = {
389 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
390 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
391 };
392
393 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
394 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
395
396
397 void DemodReset()
398 {
399 Demod.state = DEMOD_UNSYNCD;
400 Demod.len = 0; // number of decoded data bytes
401 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
402 Demod.parityBits = 0; //
403 Demod.collisionPos = 0; // Position of collision bit
404 Demod.twoBits = 0xffff; // buffer for 2 Bits
405 Demod.highCnt = 0;
406 Demod.startTime = 0;
407 Demod.endTime = 0;
408 }
409
410 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
411 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
412 {
413
414 Demod.twoBits = (Demod.twoBits << 8) | bit;
415
416 if (Demod.state == DEMOD_UNSYNCD) {
417
418 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
419 if (Demod.twoBits == 0x0000) {
420 Demod.highCnt++;
421 } else {
422 Demod.highCnt = 0;
423 }
424 } else {
425 Demod.syncBit = 0xFFFF; // not set
426 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
427 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
428 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
429 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
430 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
431 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
432 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
433 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
434 if (Demod.syncBit != 0xFFFF) {
435 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
436 Demod.startTime -= Demod.syncBit;
437 Demod.bitCount = offset; // number of decoded data bits
438 Demod.state = DEMOD_MANCHESTER_DATA;
439 }
440 }
441
442 } else {
443
444 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
445 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
446 if (!Demod.collisionPos) {
447 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
448 }
449 } // modulation in first half only - Sequence D = 1
450 Demod.bitCount++;
451 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
452 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
453 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
454 Demod.parityBits <<= 1; // make room for the parity bit
455 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
456 Demod.bitCount = 0;
457 Demod.shiftReg = 0;
458 }
459 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
460 } else { // no modulation in first half
461 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
462 Demod.bitCount++;
463 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
464 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
465 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
466 Demod.parityBits <<= 1; // make room for the new parity bit
467 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
468 Demod.bitCount = 0;
469 Demod.shiftReg = 0;
470 }
471 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
472 } else { // no modulation in both halves - End of communication
473 if (Demod.len > 0 || Demod.bitCount > 0) { // received something
474 if(Demod.bitCount > 0) { // if we decoded bits
475 Demod.shiftReg >>= (9 - Demod.bitCount); // add the remaining decoded bits to the output
476 Demod.output[Demod.len++] = Demod.shiftReg & 0xff;
477 // No parity bit, so just shift a 0
478 Demod.parityBits <<= 1;
479 }
480 return TRUE; // we are finished with decoding the raw data sequence
481 } else { // nothing received. Start over
482 DemodReset();
483 }
484 }
485 }
486
487 }
488
489 return FALSE; // not finished yet, need more data
490 }
491
492 //=============================================================================
493 // Finally, a `sniffer' for ISO 14443 Type A
494 // Both sides of communication!
495 //=============================================================================
496
497 //-----------------------------------------------------------------------------
498 // Record the sequence of commands sent by the reader to the tag, with
499 // triggering so that we start recording at the point that the tag is moved
500 // near the reader.
501 //-----------------------------------------------------------------------------
502 void RAMFUNC SnoopIso14443a(uint8_t param) {
503 // param:
504 // bit 0 - trigger from first card answer
505 // bit 1 - trigger from first reader 7-bit request
506
507 LEDsoff();
508 // init trace buffer
509 iso14a_clear_trace();
510 iso14a_set_tracing(TRUE);
511
512 // We won't start recording the frames that we acquire until we trigger;
513 // a good trigger condition to get started is probably when we see a
514 // response from the tag.
515 // triggered == FALSE -- to wait first for card
516 bool triggered = !(param & 0x03);
517
518 // The command (reader -> tag) that we're receiving.
519 // The length of a received command will in most cases be no more than 18 bytes.
520 // So 32 should be enough!
521 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
522 // The response (tag -> reader) that we're receiving.
523 uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET);
524
525 // As we receive stuff, we copy it from receivedCmd or receivedResponse
526 // into trace, along with its length and other annotations.
527 //uint8_t *trace = (uint8_t *)BigBuf;
528
529 // The DMA buffer, used to stream samples from the FPGA
530 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
531 uint8_t *data = dmaBuf;
532 uint8_t previous_data = 0;
533 int maxDataLen = 0;
534 int dataLen = 0;
535 bool TagIsActive = FALSE;
536 bool ReaderIsActive = FALSE;
537
538 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
539
540 // Set up the demodulator for tag -> reader responses.
541 Demod.output = receivedResponse;
542
543 // Set up the demodulator for the reader -> tag commands
544 Uart.output = receivedCmd;
545
546 // Setup and start DMA.
547 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
548
549 // And now we loop, receiving samples.
550 for(uint32_t rsamples = 0; TRUE; ) {
551
552 if(BUTTON_PRESS()) {
553 DbpString("cancelled by button");
554 break;
555 }
556
557 LED_A_ON();
558 WDT_HIT();
559
560 int register readBufDataP = data - dmaBuf;
561 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
562 if (readBufDataP <= dmaBufDataP){
563 dataLen = dmaBufDataP - readBufDataP;
564 } else {
565 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
566 }
567 // test for length of buffer
568 if(dataLen > maxDataLen) {
569 maxDataLen = dataLen;
570 if(dataLen > 400) {
571 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
572 break;
573 }
574 }
575 if(dataLen < 1) continue;
576
577 // primary buffer was stopped( <-- we lost data!
578 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
579 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
580 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
581 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
582 }
583 // secondary buffer sets as primary, secondary buffer was stopped
584 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
585 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
586 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
587 }
588
589 LED_A_OFF();
590
591 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
592
593 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
594 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
595 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
596 LED_C_ON();
597
598 // check - if there is a short 7bit request from reader
599 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
600
601 if(triggered) {
602 if (!LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, Uart.parityBits, TRUE)) break;
603 if (!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
604 }
605 /* And ready to receive another command. */
606 UartReset();
607 /* And also reset the demod code, which might have been */
608 /* false-triggered by the commands from the reader. */
609 DemodReset();
610 LED_B_OFF();
611 }
612 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
613 }
614
615 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
616 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
617 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
618 LED_B_ON();
619
620 if (!LogTrace(receivedResponse, Demod.len, Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER, Demod.parityBits, FALSE)) break;
621 if (!LogTrace(NULL, 0, Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER, 0, FALSE)) break;
622
623 if ((!triggered) && (param & 0x01)) triggered = TRUE;
624
625 // And ready to receive another response.
626 DemodReset();
627 LED_C_OFF();
628 }
629 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
630 }
631 }
632
633 previous_data = *data;
634 rsamples++;
635 data++;
636 if(data == dmaBuf + DMA_BUFFER_SIZE) {
637 data = dmaBuf;
638 }
639 } // main cycle
640
641 DbpString("COMMAND FINISHED");
642
643 FpgaDisableSscDma();
644 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
645 Dbprintf("traceLen=%d, Uart.output[0]=%08x", traceLen, (uint32_t)Uart.output[0]);
646 LEDsoff();
647 }
648
649 //-----------------------------------------------------------------------------
650 // Prepare tag messages
651 //-----------------------------------------------------------------------------
652 static void CodeIso14443aAsTagPar(const uint8_t *cmd, int len, uint32_t dwParity)
653 {
654 int i;
655
656 ToSendReset();
657
658 // Correction bit, might be removed when not needed
659 ToSendStuffBit(0);
660 ToSendStuffBit(0);
661 ToSendStuffBit(0);
662 ToSendStuffBit(0);
663 ToSendStuffBit(1); // 1
664 ToSendStuffBit(0);
665 ToSendStuffBit(0);
666 ToSendStuffBit(0);
667
668 // Send startbit
669 ToSend[++ToSendMax] = SEC_D;
670 LastProxToAirDuration = 8 * ToSendMax - 4;
671
672 for(i = 0; i < len; i++) {
673 int j;
674 uint8_t b = cmd[i];
675
676 // Data bits
677 for(j = 0; j < 8; j++) {
678 if(b & 1) {
679 ToSend[++ToSendMax] = SEC_D;
680 } else {
681 ToSend[++ToSendMax] = SEC_E;
682 }
683 b >>= 1;
684 }
685
686 // Get the parity bit
687 if ((dwParity >> i) & 0x01) {
688 ToSend[++ToSendMax] = SEC_D;
689 LastProxToAirDuration = 8 * ToSendMax - 4;
690 } else {
691 ToSend[++ToSendMax] = SEC_E;
692 LastProxToAirDuration = 8 * ToSendMax;
693 }
694 }
695
696 // Send stopbit
697 ToSend[++ToSendMax] = SEC_F;
698
699 // Convert from last byte pos to length
700 ToSendMax++;
701 }
702
703 static void CodeIso14443aAsTag(const uint8_t *cmd, int len){
704 CodeIso14443aAsTagPar(cmd, len, GetParity(cmd, len));
705 }
706
707
708 static void Code4bitAnswerAsTag(uint8_t cmd)
709 {
710 int i;
711
712 ToSendReset();
713
714 // Correction bit, might be removed when not needed
715 ToSendStuffBit(0);
716 ToSendStuffBit(0);
717 ToSendStuffBit(0);
718 ToSendStuffBit(0);
719 ToSendStuffBit(1); // 1
720 ToSendStuffBit(0);
721 ToSendStuffBit(0);
722 ToSendStuffBit(0);
723
724 // Send startbit
725 ToSend[++ToSendMax] = SEC_D;
726
727 uint8_t b = cmd;
728 for(i = 0; i < 4; i++) {
729 if(b & 1) {
730 ToSend[++ToSendMax] = SEC_D;
731 LastProxToAirDuration = 8 * ToSendMax - 4;
732 } else {
733 ToSend[++ToSendMax] = SEC_E;
734 LastProxToAirDuration = 8 * ToSendMax;
735 }
736 b >>= 1;
737 }
738
739 // Send stopbit
740 ToSend[++ToSendMax] = SEC_F;
741
742 // Convert from last byte pos to length
743 ToSendMax++;
744 }
745
746 //-----------------------------------------------------------------------------
747 // Wait for commands from reader
748 // Stop when button is pressed
749 // Or return TRUE when command is captured
750 //-----------------------------------------------------------------------------
751 static int GetIso14443aCommandFromReader(uint8_t *received, int *len, int maxLen)
752 {
753 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
754 // only, since we are receiving, not transmitting).
755 // Signal field is off with the appropriate LED
756 LED_D_OFF();
757 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
758
759 // Now run a `software UART' on the stream of incoming samples.
760 UartReset();
761 Uart.output = received;
762
763 // clear RXRDY:
764 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
765
766 for(;;) {
767 WDT_HIT();
768
769 if(BUTTON_PRESS()) return FALSE;
770
771 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
772 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
773 if(MillerDecoding(b, 0)) {
774 *len = Uart.len;
775 return TRUE;
776 }
777 }
778 }
779 }
780
781 static int EmSendCmd14443aRaw(uint8_t *resp, int respLen, bool correctionNeeded);
782 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
783 int EmSend4bit(uint8_t resp);
784 int EmSendCmdExPar(uint8_t *resp, int respLen, bool correctionNeeded, uint32_t par);
785 int EmSendCmdExPar(uint8_t *resp, int respLen, bool correctionNeeded, uint32_t par);
786 int EmSendCmdEx(uint8_t *resp, int respLen, bool correctionNeeded);
787 int EmSendCmd(uint8_t *resp, int respLen);
788 int EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par);
789 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint32_t reader_Parity,
790 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint32_t tag_Parity);
791
792 static uint8_t* free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
793
794 typedef struct {
795 uint8_t* response;
796 size_t response_n;
797 uint8_t* modulation;
798 size_t modulation_n;
799 uint32_t ProxToAirDuration;
800 } tag_response_info_t;
801
802 void reset_free_buffer() {
803 free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
804 }
805
806 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
807 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
808 // This will need the following byte array for a modulation sequence
809 // 144 data bits (18 * 8)
810 // 18 parity bits
811 // 2 Start and stop
812 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
813 // 1 just for the case
814 // ----------- +
815 // 166 bytes, since every bit that needs to be send costs us a byte
816 //
817
818 // Prepare the tag modulation bits from the message
819 CodeIso14443aAsTag(response_info->response,response_info->response_n);
820
821 // Make sure we do not exceed the free buffer space
822 if (ToSendMax > max_buffer_size) {
823 Dbprintf("Out of memory, when modulating bits for tag answer:");
824 Dbhexdump(response_info->response_n,response_info->response,false);
825 return false;
826 }
827
828 // Copy the byte array, used for this modulation to the buffer position
829 memcpy(response_info->modulation,ToSend,ToSendMax);
830
831 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
832 response_info->modulation_n = ToSendMax;
833 response_info->ProxToAirDuration = LastProxToAirDuration;
834
835 return true;
836 }
837
838 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
839 // Retrieve and store the current buffer index
840 response_info->modulation = free_buffer_pointer;
841
842 // Determine the maximum size we can use from our buffer
843 size_t max_buffer_size = (((uint8_t *)BigBuf)+FREE_BUFFER_OFFSET+FREE_BUFFER_SIZE)-free_buffer_pointer;
844
845 // Forward the prepare tag modulation function to the inner function
846 if (prepare_tag_modulation(response_info,max_buffer_size)) {
847 // Update the free buffer offset
848 free_buffer_pointer += ToSendMax;
849 return true;
850 } else {
851 return false;
852 }
853 }
854
855 //-----------------------------------------------------------------------------
856 // Main loop of simulated tag: receive commands from reader, decide what
857 // response to send, and send it.
858 //-----------------------------------------------------------------------------
859 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
860 {
861 // Enable and clear the trace
862 iso14a_clear_trace();
863 iso14a_set_tracing(TRUE);
864
865 uint8_t sak;
866
867 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
868 uint8_t response1[2];
869
870 switch (tagType) {
871 case 1: { // MIFARE Classic
872 // Says: I am Mifare 1k - original line
873 response1[0] = 0x04;
874 response1[1] = 0x00;
875 sak = 0x08;
876 } break;
877 case 2: { // MIFARE Ultralight
878 // Says: I am a stupid memory tag, no crypto
879 response1[0] = 0x04;
880 response1[1] = 0x00;
881 sak = 0x00;
882 } break;
883 case 3: { // MIFARE DESFire
884 // Says: I am a DESFire tag, ph33r me
885 response1[0] = 0x04;
886 response1[1] = 0x03;
887 sak = 0x20;
888 } break;
889 case 4: { // ISO/IEC 14443-4
890 // Says: I am a javacard (JCOP)
891 response1[0] = 0x04;
892 response1[1] = 0x00;
893 sak = 0x28;
894 } break;
895 default: {
896 Dbprintf("Error: unkown tagtype (%d)",tagType);
897 return;
898 } break;
899 }
900
901 // The second response contains the (mandatory) first 24 bits of the UID
902 uint8_t response2[5];
903
904 // Check if the uid uses the (optional) part
905 uint8_t response2a[5];
906 if (uid_2nd) {
907 response2[0] = 0x88;
908 num_to_bytes(uid_1st,3,response2+1);
909 num_to_bytes(uid_2nd,4,response2a);
910 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
911
912 // Configure the ATQA and SAK accordingly
913 response1[0] |= 0x40;
914 sak |= 0x04;
915 } else {
916 num_to_bytes(uid_1st,4,response2);
917 // Configure the ATQA and SAK accordingly
918 response1[0] &= 0xBF;
919 sak &= 0xFB;
920 }
921
922 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
923 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
924
925 // Prepare the mandatory SAK (for 4 and 7 byte UID)
926 uint8_t response3[3];
927 response3[0] = sak;
928 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
929
930 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
931 uint8_t response3a[3];
932 response3a[0] = sak & 0xFB;
933 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
934
935 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
936 uint8_t response6[] = { 0x04, 0x58, 0x00, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS
937 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
938
939 #define TAG_RESPONSE_COUNT 7
940 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
941 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
942 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
943 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
944 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
945 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
946 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
947 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
948 };
949
950 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
951 // Such a response is less time critical, so we can prepare them on the fly
952 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
953 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
954 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
955 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
956 tag_response_info_t dynamic_response_info = {
957 .response = dynamic_response_buffer,
958 .response_n = 0,
959 .modulation = dynamic_modulation_buffer,
960 .modulation_n = 0
961 };
962
963 // Reset the offset pointer of the free buffer
964 reset_free_buffer();
965
966 // Prepare the responses of the anticollision phase
967 // there will be not enough time to do this at the moment the reader sends it REQA
968 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
969 prepare_allocated_tag_modulation(&responses[i]);
970 }
971
972 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
973 int len = 0;
974
975 // To control where we are in the protocol
976 int order = 0;
977 int lastorder;
978
979 // Just to allow some checks
980 int happened = 0;
981 int happened2 = 0;
982 int cmdsRecvd = 0;
983
984 // We need to listen to the high-frequency, peak-detected path.
985 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
986
987 cmdsRecvd = 0;
988 tag_response_info_t* p_response;
989
990 LED_A_ON();
991 for(;;) {
992 // Clean receive command buffer
993
994 if(!GetIso14443aCommandFromReader(receivedCmd, &len, RECV_CMD_SIZE)) {
995 DbpString("Button press");
996 break;
997 }
998
999 p_response = NULL;
1000
1001 // doob - added loads of debug strings so we can see what the reader is saying to us during the sim as hi14alist is not populated
1002 // Okay, look at the command now.
1003 lastorder = order;
1004 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1005 p_response = &responses[0]; order = 1;
1006 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1007 p_response = &responses[0]; order = 6;
1008 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1009 p_response = &responses[1]; order = 2;
1010 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1011 p_response = &responses[2]; order = 20;
1012 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1013 p_response = &responses[3]; order = 3;
1014 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1015 p_response = &responses[4]; order = 30;
1016 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1017 EmSendCmdEx(data+(4*receivedCmd[0]),16,false);
1018 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1019 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1020 p_response = NULL;
1021 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1022 // DbpString("Reader requested we HALT!:");
1023 if (tracing) {
1024 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1025 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1026 }
1027 p_response = NULL;
1028 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1029 p_response = &responses[5]; order = 7;
1030 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1031 if (tagType == 1 || tagType == 2) { // RATS not supported
1032 EmSend4bit(CARD_NACK_NA);
1033 p_response = NULL;
1034 } else {
1035 p_response = &responses[6]; order = 70;
1036 }
1037 } else if (order == 7 && len == 8) { // Received authentication request
1038 if (tracing) {
1039 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1040 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1041 }
1042 uint32_t nr = bytes_to_num(receivedCmd,4);
1043 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1044 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1045 } else {
1046 // Check for ISO 14443A-4 compliant commands, look at left nibble
1047 switch (receivedCmd[0]) {
1048
1049 case 0x0B:
1050 case 0x0A: { // IBlock (command)
1051 dynamic_response_info.response[0] = receivedCmd[0];
1052 dynamic_response_info.response[1] = 0x00;
1053 dynamic_response_info.response[2] = 0x90;
1054 dynamic_response_info.response[3] = 0x00;
1055 dynamic_response_info.response_n = 4;
1056 } break;
1057
1058 case 0x1A:
1059 case 0x1B: { // Chaining command
1060 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1061 dynamic_response_info.response_n = 2;
1062 } break;
1063
1064 case 0xaa:
1065 case 0xbb: {
1066 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1067 dynamic_response_info.response_n = 2;
1068 } break;
1069
1070 case 0xBA: { //
1071 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1072 dynamic_response_info.response_n = 2;
1073 } break;
1074
1075 case 0xCA:
1076 case 0xC2: { // Readers sends deselect command
1077 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1078 dynamic_response_info.response_n = 2;
1079 } break;
1080
1081 default: {
1082 // Never seen this command before
1083 if (tracing) {
1084 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1085 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1086 }
1087 Dbprintf("Received unknown command (len=%d):",len);
1088 Dbhexdump(len,receivedCmd,false);
1089 // Do not respond
1090 dynamic_response_info.response_n = 0;
1091 } break;
1092 }
1093
1094 if (dynamic_response_info.response_n > 0) {
1095 // Copy the CID from the reader query
1096 dynamic_response_info.response[1] = receivedCmd[1];
1097
1098 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1099 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1100 dynamic_response_info.response_n += 2;
1101
1102 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1103 Dbprintf("Error preparing tag response");
1104 if (tracing) {
1105 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1106 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1107 }
1108 break;
1109 }
1110 p_response = &dynamic_response_info;
1111 }
1112 }
1113
1114 // Count number of wakeups received after a halt
1115 if(order == 6 && lastorder == 5) { happened++; }
1116
1117 // Count number of other messages after a halt
1118 if(order != 6 && lastorder == 5) { happened2++; }
1119
1120 if(cmdsRecvd > 999) {
1121 DbpString("1000 commands later...");
1122 break;
1123 }
1124 cmdsRecvd++;
1125
1126 if (p_response != NULL) {
1127 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1128 // do the tracing for the previous reader request and this tag answer:
1129 EmLogTrace(Uart.output,
1130 Uart.len,
1131 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1132 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1133 Uart.parityBits,
1134 p_response->response,
1135 p_response->response_n,
1136 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1137 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1138 SwapBits(GetParity(p_response->response, p_response->response_n), p_response->response_n));
1139 }
1140
1141 if (!tracing) {
1142 Dbprintf("Trace Full. Simulation stopped.");
1143 break;
1144 }
1145 }
1146
1147 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1148 LED_A_OFF();
1149 }
1150
1151
1152 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1153 // of bits specified in the delay parameter.
1154 void PrepareDelayedTransfer(uint16_t delay)
1155 {
1156 uint8_t bitmask = 0;
1157 uint8_t bits_to_shift = 0;
1158 uint8_t bits_shifted = 0;
1159
1160 delay &= 0x07;
1161 if (delay) {
1162 for (uint16_t i = 0; i < delay; i++) {
1163 bitmask |= (0x01 << i);
1164 }
1165 ToSend[ToSendMax++] = 0x00;
1166 for (uint16_t i = 0; i < ToSendMax; i++) {
1167 bits_to_shift = ToSend[i] & bitmask;
1168 ToSend[i] = ToSend[i] >> delay;
1169 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1170 bits_shifted = bits_to_shift;
1171 }
1172 }
1173 }
1174
1175
1176 //-------------------------------------------------------------------------------------
1177 // Transmit the command (to the tag) that was placed in ToSend[].
1178 // Parameter timing:
1179 // if NULL: transfer at next possible time, taking into account
1180 // request guard time and frame delay time
1181 // if == 0: transfer immediately and return time of transfer
1182 // if != 0: delay transfer until time specified
1183 //-------------------------------------------------------------------------------------
1184 static void TransmitFor14443a(const uint8_t *cmd, int len, uint32_t *timing)
1185 {
1186
1187 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1188
1189 uint32_t ThisTransferTime = 0;
1190
1191 if (timing) {
1192 if(*timing == 0) { // Measure time
1193 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1194 } else {
1195 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1196 }
1197 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1198 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1199 LastTimeProxToAirStart = *timing;
1200 } else {
1201 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1202 while(GetCountSspClk() < ThisTransferTime);
1203 LastTimeProxToAirStart = ThisTransferTime;
1204 }
1205
1206 // clear TXRDY
1207 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1208
1209 // for(uint16_t c = 0; c < 10;) { // standard delay for each transfer (allow tag to be ready after last transmission)
1210 // if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1211 // AT91C_BASE_SSC->SSC_THR = SEC_Y;
1212 // c++;
1213 // }
1214 // }
1215
1216 uint16_t c = 0;
1217 for(;;) {
1218 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1219 AT91C_BASE_SSC->SSC_THR = cmd[c];
1220 c++;
1221 if(c >= len) {
1222 break;
1223 }
1224 }
1225 }
1226
1227 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1228
1229 }
1230
1231
1232 //-----------------------------------------------------------------------------
1233 // Prepare reader command (in bits, support short frames) to send to FPGA
1234 //-----------------------------------------------------------------------------
1235 void CodeIso14443aBitsAsReaderPar(const uint8_t * cmd, int bits, uint32_t dwParity)
1236 {
1237 int i, j;
1238 int last;
1239 uint8_t b;
1240
1241 ToSendReset();
1242
1243 // Start of Communication (Seq. Z)
1244 ToSend[++ToSendMax] = SEC_Z;
1245 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1246 last = 0;
1247
1248 size_t bytecount = nbytes(bits);
1249 // Generate send structure for the data bits
1250 for (i = 0; i < bytecount; i++) {
1251 // Get the current byte to send
1252 b = cmd[i];
1253 size_t bitsleft = MIN((bits-(i*8)),8);
1254
1255 for (j = 0; j < bitsleft; j++) {
1256 if (b & 1) {
1257 // Sequence X
1258 ToSend[++ToSendMax] = SEC_X;
1259 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1260 last = 1;
1261 } else {
1262 if (last == 0) {
1263 // Sequence Z
1264 ToSend[++ToSendMax] = SEC_Z;
1265 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1266 } else {
1267 // Sequence Y
1268 ToSend[++ToSendMax] = SEC_Y;
1269 last = 0;
1270 }
1271 }
1272 b >>= 1;
1273 }
1274
1275 // Only transmit (last) parity bit if we transmitted a complete byte
1276 if (j == 8) {
1277 // Get the parity bit
1278 if ((dwParity >> i) & 0x01) {
1279 // Sequence X
1280 ToSend[++ToSendMax] = SEC_X;
1281 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1282 last = 1;
1283 } else {
1284 if (last == 0) {
1285 // Sequence Z
1286 ToSend[++ToSendMax] = SEC_Z;
1287 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1288 } else {
1289 // Sequence Y
1290 ToSend[++ToSendMax] = SEC_Y;
1291 last = 0;
1292 }
1293 }
1294 }
1295 }
1296
1297 // End of Communication: Logic 0 followed by Sequence Y
1298 if (last == 0) {
1299 // Sequence Z
1300 ToSend[++ToSendMax] = SEC_Z;
1301 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1302 } else {
1303 // Sequence Y
1304 ToSend[++ToSendMax] = SEC_Y;
1305 last = 0;
1306 }
1307 ToSend[++ToSendMax] = SEC_Y;
1308
1309 // Convert to length of command:
1310 ToSendMax++;
1311 }
1312
1313 //-----------------------------------------------------------------------------
1314 // Prepare reader command to send to FPGA
1315 //-----------------------------------------------------------------------------
1316 void CodeIso14443aAsReaderPar(const uint8_t * cmd, int len, uint32_t dwParity)
1317 {
1318 CodeIso14443aBitsAsReaderPar(cmd,len*8,dwParity);
1319 }
1320
1321 //-----------------------------------------------------------------------------
1322 // Wait for commands from reader
1323 // Stop when button is pressed (return 1) or field was gone (return 2)
1324 // Or return 0 when command is captured
1325 //-----------------------------------------------------------------------------
1326 static int EmGetCmd(uint8_t *received, int *len)
1327 {
1328 *len = 0;
1329
1330 uint32_t timer = 0, vtime = 0;
1331 int analogCnt = 0;
1332 int analogAVG = 0;
1333
1334 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1335 // only, since we are receiving, not transmitting).
1336 // Signal field is off with the appropriate LED
1337 LED_D_OFF();
1338 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1339
1340 // Set ADC to read field strength
1341 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1342 AT91C_BASE_ADC->ADC_MR =
1343 ADC_MODE_PRESCALE(32) |
1344 ADC_MODE_STARTUP_TIME(16) |
1345 ADC_MODE_SAMPLE_HOLD_TIME(8);
1346 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1347 // start ADC
1348 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1349
1350 // Now run a 'software UART' on the stream of incoming samples.
1351 UartReset();
1352 Uart.output = received;
1353
1354 // Clear RXRDY:
1355 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1356
1357 for(;;) {
1358 WDT_HIT();
1359
1360 if (BUTTON_PRESS()) return 1;
1361
1362 // test if the field exists
1363 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1364 analogCnt++;
1365 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1366 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1367 if (analogCnt >= 32) {
1368 if ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1369 vtime = GetTickCount();
1370 if (!timer) timer = vtime;
1371 // 50ms no field --> card to idle state
1372 if (vtime - timer > 50) return 2;
1373 } else
1374 if (timer) timer = 0;
1375 analogCnt = 0;
1376 analogAVG = 0;
1377 }
1378 }
1379
1380 // receive and test the miller decoding
1381 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1382 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1383 if(MillerDecoding(b, 0)) {
1384 *len = Uart.len;
1385 return 0;
1386 }
1387 }
1388
1389 }
1390 }
1391
1392
1393 static int EmSendCmd14443aRaw(uint8_t *resp, int respLen, bool correctionNeeded)
1394 {
1395 uint8_t b;
1396 uint16_t i = 0;
1397 uint32_t ThisTransferTime;
1398
1399 // Modulate Manchester
1400 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1401
1402 // include correction bit if necessary
1403 if (Uart.parityBits & 0x01) {
1404 correctionNeeded = TRUE;
1405 }
1406 if(correctionNeeded) {
1407 // 1236, so correction bit needed
1408 i = 0;
1409 } else {
1410 i = 1;
1411 }
1412
1413 // clear receiving shift register and holding register
1414 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1415 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1416 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1417 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1418
1419 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1420 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1421 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1422 if (AT91C_BASE_SSC->SSC_RHR) break;
1423 }
1424
1425 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1426
1427 // Clear TXRDY:
1428 AT91C_BASE_SSC->SSC_THR = SEC_F;
1429
1430 // send cycle
1431 for(; i <= respLen; ) {
1432 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1433 AT91C_BASE_SSC->SSC_THR = resp[i++];
1434 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1435 }
1436
1437 if(BUTTON_PRESS()) {
1438 break;
1439 }
1440 }
1441
1442 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1443 for (i = 0; i < 2 ; ) {
1444 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1445 AT91C_BASE_SSC->SSC_THR = SEC_F;
1446 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1447 i++;
1448 }
1449 }
1450
1451 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1452
1453 return 0;
1454 }
1455
1456 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1457 Code4bitAnswerAsTag(resp);
1458 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1459 // do the tracing for the previous reader request and this tag answer:
1460 EmLogTrace(Uart.output,
1461 Uart.len,
1462 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1463 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1464 Uart.parityBits,
1465 &resp,
1466 1,
1467 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1468 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1469 SwapBits(GetParity(&resp, 1), 1));
1470 return res;
1471 }
1472
1473 int EmSend4bit(uint8_t resp){
1474 return EmSend4bitEx(resp, false);
1475 }
1476
1477 int EmSendCmdExPar(uint8_t *resp, int respLen, bool correctionNeeded, uint32_t par){
1478 CodeIso14443aAsTagPar(resp, respLen, par);
1479 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1480 // do the tracing for the previous reader request and this tag answer:
1481 EmLogTrace(Uart.output,
1482 Uart.len,
1483 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1484 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1485 Uart.parityBits,
1486 resp,
1487 respLen,
1488 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1489 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1490 SwapBits(GetParity(resp, respLen), respLen));
1491 return res;
1492 }
1493
1494 int EmSendCmdEx(uint8_t *resp, int respLen, bool correctionNeeded){
1495 return EmSendCmdExPar(resp, respLen, correctionNeeded, GetParity(resp, respLen));
1496 }
1497
1498 int EmSendCmd(uint8_t *resp, int respLen){
1499 return EmSendCmdExPar(resp, respLen, false, GetParity(resp, respLen));
1500 }
1501
1502 int EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par){
1503 return EmSendCmdExPar(resp, respLen, false, par);
1504 }
1505
1506 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint32_t reader_Parity,
1507 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint32_t tag_Parity)
1508 {
1509 if (tracing) {
1510 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1511 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1512 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1513 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1514 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1515 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1516 reader_EndTime = tag_StartTime - exact_fdt;
1517 reader_StartTime = reader_EndTime - reader_modlen;
1518 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_Parity, TRUE)) {
1519 return FALSE;
1520 } else if (!LogTrace(NULL, 0, reader_EndTime, 0, TRUE)) {
1521 return FALSE;
1522 } else if (!LogTrace(tag_data, tag_len, tag_StartTime, tag_Parity, FALSE)) {
1523 return FALSE;
1524 } else {
1525 return (!LogTrace(NULL, 0, tag_EndTime, 0, FALSE));
1526 }
1527 } else {
1528 return TRUE;
1529 }
1530 }
1531
1532 //-----------------------------------------------------------------------------
1533 // Wait a certain time for tag response
1534 // If a response is captured return TRUE
1535 // If it takes too long return FALSE
1536 //-----------------------------------------------------------------------------
1537 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint16_t offset, int maxLen)
1538 {
1539 uint16_t c;
1540
1541 // Set FPGA mode to "reader listen mode", no modulation (listen
1542 // only, since we are receiving, not transmitting).
1543 // Signal field is on with the appropriate LED
1544 LED_D_ON();
1545 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1546
1547 // Now get the answer from the card
1548 DemodReset();
1549 Demod.output = receivedResponse;
1550
1551 // clear RXRDY:
1552 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1553
1554 c = 0;
1555 for(;;) {
1556 WDT_HIT();
1557
1558 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1559 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1560 if(ManchesterDecoding(b, offset, 0)) {
1561 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1562 return TRUE;
1563 } else if(c++ > iso14a_timeout) {
1564 return FALSE;
1565 }
1566 }
1567 }
1568 }
1569
1570 void ReaderTransmitBitsPar(uint8_t* frame, int bits, uint32_t par, uint32_t *timing)
1571 {
1572
1573 CodeIso14443aBitsAsReaderPar(frame,bits,par);
1574
1575 // Send command to tag
1576 TransmitFor14443a(ToSend, ToSendMax, timing);
1577 if(trigger)
1578 LED_A_ON();
1579
1580 // Log reader command in trace buffer
1581 if (tracing) {
1582 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1583 LogTrace(NULL, 0, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, 0, TRUE);
1584 }
1585 }
1586
1587 void ReaderTransmitPar(uint8_t* frame, int len, uint32_t par, uint32_t *timing)
1588 {
1589 ReaderTransmitBitsPar(frame,len*8,par, timing);
1590 }
1591
1592 void ReaderTransmitBits(uint8_t* frame, int len, uint32_t *timing)
1593 {
1594 // Generate parity and redirect
1595 ReaderTransmitBitsPar(frame,len,GetParity(frame,len/8), timing);
1596 }
1597
1598 void ReaderTransmit(uint8_t* frame, int len, uint32_t *timing)
1599 {
1600 // Generate parity and redirect
1601 ReaderTransmitBitsPar(frame,len*8,GetParity(frame,len), timing);
1602 }
1603
1604 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset)
1605 {
1606 if (!GetIso14443aAnswerFromTag(receivedAnswer,offset,160)) return FALSE;
1607 if (tracing) {
1608 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.parityBits, FALSE);
1609 LogTrace(NULL, 0, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, 0, FALSE);
1610 }
1611 return Demod.len;
1612 }
1613
1614 int ReaderReceive(uint8_t* receivedAnswer)
1615 {
1616 return ReaderReceiveOffset(receivedAnswer, 0);
1617 }
1618
1619 int ReaderReceivePar(uint8_t *receivedAnswer, uint32_t *parptr)
1620 {
1621 if (!GetIso14443aAnswerFromTag(receivedAnswer,0,160)) return FALSE;
1622 if (tracing) {
1623 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.parityBits, FALSE);
1624 LogTrace(NULL, 0, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, 0, FALSE);
1625 }
1626 *parptr = Demod.parityBits;
1627 return Demod.len;
1628 }
1629
1630 /* performs iso14443a anticollision procedure
1631 * fills the uid pointer unless NULL
1632 * fills resp_data unless NULL */
1633 int iso14443a_select_card(byte_t* uid_ptr, iso14a_card_select_t* p_hi14a_card, uint32_t* cuid_ptr) {
1634 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1635 uint8_t sel_all[] = { 0x93,0x20 };
1636 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1637 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1638 uint8_t* resp = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET); // was 3560 - tied to other size changes
1639 byte_t uid_resp[4];
1640 size_t uid_resp_len;
1641
1642 uint8_t sak = 0x04; // cascade uid
1643 int cascade_level = 0;
1644 int len;
1645
1646 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1647 ReaderTransmitBitsPar(wupa,7,0, NULL);
1648
1649 // Receive the ATQA
1650 if(!ReaderReceive(resp)) return 0;
1651 // Dbprintf("atqa: %02x %02x",resp[0],resp[1]);
1652
1653 if(p_hi14a_card) {
1654 memcpy(p_hi14a_card->atqa, resp, 2);
1655 p_hi14a_card->uidlen = 0;
1656 memset(p_hi14a_card->uid,0,10);
1657 }
1658
1659 // clear uid
1660 if (uid_ptr) {
1661 memset(uid_ptr,0,10);
1662 }
1663
1664 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1665 // which case we need to make a cascade 2 request and select - this is a long UID
1666 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1667 for(; sak & 0x04; cascade_level++) {
1668 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1669 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1670
1671 // SELECT_ALL
1672 ReaderTransmit(sel_all,sizeof(sel_all), NULL);
1673 if (!ReaderReceive(resp)) return 0;
1674
1675 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1676 memset(uid_resp, 0, 4);
1677 uint16_t uid_resp_bits = 0;
1678 uint16_t collision_answer_offset = 0;
1679 // anti-collision-loop:
1680 while (Demod.collisionPos) {
1681 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1682 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1683 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1684 uid_resp[uid_resp_bits & 0xf8] |= UIDbit << (uid_resp_bits % 8);
1685 }
1686 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1687 uid_resp_bits++;
1688 // construct anticollosion command:
1689 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1690 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1691 sel_uid[2+i] = uid_resp[i];
1692 }
1693 collision_answer_offset = uid_resp_bits%8;
1694 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1695 if (!ReaderReceiveOffset(resp, collision_answer_offset)) return 0;
1696 }
1697 // finally, add the last bits and BCC of the UID
1698 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1699 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1700 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1701 }
1702
1703 } else { // no collision, use the response to SELECT_ALL as current uid
1704 memcpy(uid_resp,resp,4);
1705 }
1706 uid_resp_len = 4;
1707 // Dbprintf("uid: %02x %02x %02x %02x",uid_resp[0],uid_resp[1],uid_resp[2],uid_resp[3]);
1708
1709 // calculate crypto UID. Always use last 4 Bytes.
1710 if(cuid_ptr) {
1711 *cuid_ptr = bytes_to_num(uid_resp, 4);
1712 }
1713
1714 // Construct SELECT UID command
1715 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1716 memcpy(sel_uid+2,uid_resp,4); // the UID
1717 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1718 AppendCrc14443a(sel_uid,7); // calculate and add CRC
1719 ReaderTransmit(sel_uid,sizeof(sel_uid), NULL);
1720
1721 // Receive the SAK
1722 if (!ReaderReceive(resp)) return 0;
1723 sak = resp[0];
1724
1725 // Test if more parts of the uid are comming
1726 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1727 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1728 // http://www.nxp.com/documents/application_note/AN10927.pdf
1729 // This was earlier:
1730 //memcpy(uid_resp, uid_resp + 1, 3);
1731 // But memcpy should not be used for overlapping arrays,
1732 // and memmove appears to not be available in the arm build.
1733 // So this has been replaced with a for-loop:
1734 for(int xx = 0; xx < 3; xx++) uid_resp[xx] = uid_resp[xx+1];
1735
1736 uid_resp_len = 3;
1737 }
1738
1739 if(uid_ptr) {
1740 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1741 }
1742
1743 if(p_hi14a_card) {
1744 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1745 p_hi14a_card->uidlen += uid_resp_len;
1746 }
1747 }
1748
1749 if(p_hi14a_card) {
1750 p_hi14a_card->sak = sak;
1751 p_hi14a_card->ats_len = 0;
1752 }
1753
1754 if( (sak & 0x20) == 0) {
1755 return 2; // non iso14443a compliant tag
1756 }
1757
1758 // Request for answer to select
1759 AppendCrc14443a(rats, 2);
1760 ReaderTransmit(rats, sizeof(rats), NULL);
1761
1762 if (!(len = ReaderReceive(resp))) return 0;
1763
1764 if(p_hi14a_card) {
1765 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1766 p_hi14a_card->ats_len = len;
1767 }
1768
1769 // reset the PCB block number
1770 iso14_pcb_blocknum = 0;
1771 return 1;
1772 }
1773
1774 void iso14443a_setup(uint8_t fpga_minor_mode) {
1775 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1776 // Set up the synchronous serial port
1777 FpgaSetupSsc();
1778 // connect Demodulated Signal to ADC:
1779 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1780
1781 // Signal field is on with the appropriate LED
1782 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1783 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1784 LED_D_ON();
1785 } else {
1786 LED_D_OFF();
1787 }
1788 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1789
1790 // Start the timer
1791 StartCountSspClk();
1792
1793 DemodReset();
1794 UartReset();
1795 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1796 iso14a_set_timeout(1050); // 10ms default
1797 }
1798
1799 int iso14_apdu(uint8_t * cmd, size_t cmd_len, void * data) {
1800 uint8_t real_cmd[cmd_len+4];
1801 real_cmd[0] = 0x0a; //I-Block
1802 // put block number into the PCB
1803 real_cmd[0] |= iso14_pcb_blocknum;
1804 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1805 memcpy(real_cmd+2, cmd, cmd_len);
1806 AppendCrc14443a(real_cmd,cmd_len+2);
1807
1808 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1809 size_t len = ReaderReceive(data);
1810 uint8_t * data_bytes = (uint8_t *) data;
1811 if (!len)
1812 return 0; //DATA LINK ERROR
1813 // if we received an I- or R(ACK)-Block with a block number equal to the
1814 // current block number, toggle the current block number
1815 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1816 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1817 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1818 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1819 {
1820 iso14_pcb_blocknum ^= 1;
1821 }
1822
1823 return len;
1824 }
1825
1826 //-----------------------------------------------------------------------------
1827 // Read an ISO 14443a tag. Send out commands and store answers.
1828 //
1829 //-----------------------------------------------------------------------------
1830 void ReaderIso14443a(UsbCommand *c)
1831 {
1832 iso14a_command_t param = c->arg[0];
1833 uint8_t *cmd = c->d.asBytes;
1834 size_t len = c->arg[1];
1835 size_t lenbits = c->arg[2];
1836 uint32_t arg0 = 0;
1837 byte_t buf[USB_CMD_DATA_SIZE];
1838
1839 if(param & ISO14A_CONNECT) {
1840 iso14a_clear_trace();
1841 }
1842
1843 iso14a_set_tracing(TRUE);
1844
1845 if(param & ISO14A_REQUEST_TRIGGER) {
1846 iso14a_set_trigger(TRUE);
1847 }
1848
1849 if(param & ISO14A_CONNECT) {
1850 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1851 if(!(param & ISO14A_NO_SELECT)) {
1852 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1853 arg0 = iso14443a_select_card(NULL,card,NULL);
1854 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1855 }
1856 }
1857
1858 if(param & ISO14A_SET_TIMEOUT) {
1859 iso14a_timeout = c->arg[2];
1860 }
1861
1862 if(param & ISO14A_APDU) {
1863 arg0 = iso14_apdu(cmd, len, buf);
1864 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1865 }
1866
1867 if(param & ISO14A_RAW) {
1868 if(param & ISO14A_APPEND_CRC) {
1869 AppendCrc14443a(cmd,len);
1870 len += 2;
1871 if (lenbits) lenbits += 16;
1872 }
1873 if(lenbits>0) {
1874 ReaderTransmitBitsPar(cmd,lenbits,GetParity(cmd,lenbits/8), NULL);
1875 } else {
1876 ReaderTransmit(cmd,len, NULL);
1877 }
1878 arg0 = ReaderReceive(buf);
1879 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1880 }
1881
1882 if(param & ISO14A_REQUEST_TRIGGER) {
1883 iso14a_set_trigger(FALSE);
1884 }
1885
1886 if(param & ISO14A_NO_DISCONNECT) {
1887 return;
1888 }
1889
1890 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1891 LEDsoff();
1892 }
1893
1894
1895 // Determine the distance between two nonces.
1896 // Assume that the difference is small, but we don't know which is first.
1897 // Therefore try in alternating directions.
1898 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1899
1900 uint16_t i;
1901 uint32_t nttmp1, nttmp2;
1902
1903 if (nt1 == nt2) return 0;
1904
1905 nttmp1 = nt1;
1906 nttmp2 = nt2;
1907
1908 for (i = 1; i < 32768; i++) {
1909 nttmp1 = prng_successor(nttmp1, 1);
1910 if (nttmp1 == nt2) return i;
1911 nttmp2 = prng_successor(nttmp2, 1);
1912 if (nttmp2 == nt1) return -i;
1913 }
1914
1915 return(-99999); // either nt1 or nt2 are invalid nonces
1916 }
1917
1918
1919 //-----------------------------------------------------------------------------
1920 // Recover several bits of the cypher stream. This implements (first stages of)
1921 // the algorithm described in "The Dark Side of Security by Obscurity and
1922 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
1923 // (article by Nicolas T. Courtois, 2009)
1924 //-----------------------------------------------------------------------------
1925 void ReaderMifare(bool first_try)
1926 {
1927 // Mifare AUTH
1928 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
1929 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
1930 static uint8_t mf_nr_ar3;
1931
1932 uint8_t* receivedAnswer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
1933
1934 iso14a_clear_trace();
1935 iso14a_set_tracing(TRUE);
1936
1937 byte_t nt_diff = 0;
1938 byte_t par = 0;
1939 //byte_t par_mask = 0xff;
1940 static byte_t par_low = 0;
1941 bool led_on = TRUE;
1942 uint8_t uid[10];
1943 uint32_t cuid;
1944
1945 uint32_t nt =0 ;
1946 uint32_t previous_nt = 0;
1947 static uint32_t nt_attacked = 0;
1948 byte_t par_list[8] = {0,0,0,0,0,0,0,0};
1949 byte_t ks_list[8] = {0,0,0,0,0,0,0,0};
1950
1951 static uint32_t sync_time;
1952 static uint32_t sync_cycles;
1953 int catch_up_cycles = 0;
1954 int last_catch_up = 0;
1955 uint16_t consecutive_resyncs = 0;
1956 int isOK = 0;
1957
1958
1959
1960 if (first_try) {
1961 mf_nr_ar3 = 0;
1962 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
1963 sync_time = GetCountSspClk() & 0xfffffff8;
1964 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
1965 nt_attacked = 0;
1966 nt = 0;
1967 par = 0;
1968 }
1969 else {
1970 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1971 // nt_attacked = prng_successor(nt_attacked, 1);
1972 mf_nr_ar3++;
1973 mf_nr_ar[3] = mf_nr_ar3;
1974 par = par_low;
1975 }
1976
1977 LED_A_ON();
1978 LED_B_OFF();
1979 LED_C_OFF();
1980
1981
1982 for(uint16_t i = 0; TRUE; i++) {
1983
1984 WDT_HIT();
1985
1986 // Test if the action was cancelled
1987 if(BUTTON_PRESS()) {
1988 break;
1989 }
1990
1991 LED_C_ON();
1992
1993 if(!iso14443a_select_card(uid, NULL, &cuid)) {
1994 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1995 continue;
1996 }
1997
1998 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
1999 catch_up_cycles = 0;
2000
2001 // if we missed the sync time already, advance to the next nonce repeat
2002 while(GetCountSspClk() > sync_time) {
2003 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2004 }
2005
2006 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2007 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2008
2009 // Receive the (4 Byte) "random" nonce
2010 if (!ReaderReceive(receivedAnswer)) {
2011 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2012 continue;
2013 }
2014
2015 previous_nt = nt;
2016 nt = bytes_to_num(receivedAnswer, 4);
2017
2018 // Transmit reader nonce with fake par
2019 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2020
2021 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2022 int nt_distance = dist_nt(previous_nt, nt);
2023 if (nt_distance == 0) {
2024 nt_attacked = nt;
2025 }
2026 else {
2027 if (nt_distance == -99999) { // invalid nonce received, try again
2028 continue;
2029 }
2030 sync_cycles = (sync_cycles - nt_distance);
2031 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2032 continue;
2033 }
2034 }
2035
2036 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2037 catch_up_cycles = -dist_nt(nt_attacked, nt);
2038 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2039 catch_up_cycles = 0;
2040 continue;
2041 }
2042 if (catch_up_cycles == last_catch_up) {
2043 consecutive_resyncs++;
2044 }
2045 else {
2046 last_catch_up = catch_up_cycles;
2047 consecutive_resyncs = 0;
2048 }
2049 if (consecutive_resyncs < 3) {
2050 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2051 }
2052 else {
2053 sync_cycles = sync_cycles + catch_up_cycles;
2054 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2055 }
2056 continue;
2057 }
2058
2059 consecutive_resyncs = 0;
2060
2061 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2062 if (ReaderReceive(receivedAnswer))
2063 {
2064 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2065
2066 if (nt_diff == 0)
2067 {
2068 par_low = par & 0x07; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2069 }
2070
2071 led_on = !led_on;
2072 if(led_on) LED_B_ON(); else LED_B_OFF();
2073
2074 par_list[nt_diff] = par;
2075 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2076
2077 // Test if the information is complete
2078 if (nt_diff == 0x07) {
2079 isOK = 1;
2080 break;
2081 }
2082
2083 nt_diff = (nt_diff + 1) & 0x07;
2084 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2085 par = par_low;
2086 } else {
2087 if (nt_diff == 0 && first_try)
2088 {
2089 par++;
2090 } else {
2091 par = (((par >> 3) + 1) << 3) | par_low;
2092 }
2093 }
2094 }
2095
2096
2097 mf_nr_ar[3] &= 0x1F;
2098
2099 byte_t buf[28];
2100 memcpy(buf + 0, uid, 4);
2101 num_to_bytes(nt, 4, buf + 4);
2102 memcpy(buf + 8, par_list, 8);
2103 memcpy(buf + 16, ks_list, 8);
2104 memcpy(buf + 24, mf_nr_ar, 4);
2105
2106 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2107
2108 // Thats it...
2109 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2110 LEDsoff();
2111
2112 iso14a_set_tracing(FALSE);
2113 }
2114
2115 /**
2116 *MIFARE 1K simulate.
2117 *
2118 *@param flags :
2119 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2120 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2121 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2122 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2123 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2124 */
2125 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2126 {
2127 int cardSTATE = MFEMUL_NOFIELD;
2128 int _7BUID = 0;
2129 int vHf = 0; // in mV
2130 int res;
2131 uint32_t selTimer = 0;
2132 uint32_t authTimer = 0;
2133 uint32_t par = 0;
2134 int len = 0;
2135 uint8_t cardWRBL = 0;
2136 uint8_t cardAUTHSC = 0;
2137 uint8_t cardAUTHKEY = 0xff; // no authentication
2138 uint32_t cardRr = 0;
2139 uint32_t cuid = 0;
2140 //uint32_t rn_enc = 0;
2141 uint32_t ans = 0;
2142 uint32_t cardINTREG = 0;
2143 uint8_t cardINTBLOCK = 0;
2144 struct Crypto1State mpcs = {0, 0};
2145 struct Crypto1State *pcs;
2146 pcs = &mpcs;
2147 uint32_t numReads = 0;//Counts numer of times reader read a block
2148 uint8_t* receivedCmd = eml_get_bigbufptr_recbuf();
2149 uint8_t *response = eml_get_bigbufptr_sendbuf();
2150
2151 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2152 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2153 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2154 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2155 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2156
2157 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2158 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2159
2160 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2161 // This can be used in a reader-only attack.
2162 // (it can also be retrieved via 'hf 14a list', but hey...
2163 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2164 uint8_t ar_nr_collected = 0;
2165
2166 // clear trace
2167 iso14a_clear_trace();
2168 iso14a_set_tracing(TRUE);
2169
2170 // Authenticate response - nonce
2171 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2172
2173 //-- Determine the UID
2174 // Can be set from emulator memory, incoming data
2175 // and can be 7 or 4 bytes long
2176 if (flags & FLAG_4B_UID_IN_DATA)
2177 {
2178 // 4B uid comes from data-portion of packet
2179 memcpy(rUIDBCC1,datain,4);
2180 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2181
2182 } else if (flags & FLAG_7B_UID_IN_DATA) {
2183 // 7B uid comes from data-portion of packet
2184 memcpy(&rUIDBCC1[1],datain,3);
2185 memcpy(rUIDBCC2, datain+3, 4);
2186 _7BUID = true;
2187 } else {
2188 // get UID from emul memory
2189 emlGetMemBt(receivedCmd, 7, 1);
2190 _7BUID = !(receivedCmd[0] == 0x00);
2191 if (!_7BUID) { // ---------- 4BUID
2192 emlGetMemBt(rUIDBCC1, 0, 4);
2193 } else { // ---------- 7BUID
2194 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2195 emlGetMemBt(rUIDBCC2, 3, 4);
2196 }
2197 }
2198
2199 /*
2200 * Regardless of what method was used to set the UID, set fifth byte and modify
2201 * the ATQA for 4 or 7-byte UID
2202 */
2203 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2204 if (_7BUID) {
2205 rATQA[0] = 0x44;
2206 rUIDBCC1[0] = 0x88;
2207 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2208 }
2209
2210 // We need to listen to the high-frequency, peak-detected path.
2211 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2212
2213
2214 if (MF_DBGLEVEL >= 1) {
2215 if (!_7BUID) {
2216 Dbprintf("4B UID: %02x%02x%02x%02x",
2217 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2218 } else {
2219 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2220 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2221 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2222 }
2223 }
2224
2225 bool finished = FALSE;
2226 while (!BUTTON_PRESS() && !finished) {
2227 WDT_HIT();
2228
2229 // find reader field
2230 // Vref = 3300mV, and an 10:1 voltage divider on the input
2231 // can measure voltages up to 33000 mV
2232 if (cardSTATE == MFEMUL_NOFIELD) {
2233 vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;
2234 if (vHf > MF_MINFIELDV) {
2235 cardSTATE_TO_IDLE();
2236 LED_A_ON();
2237 }
2238 }
2239 if(cardSTATE == MFEMUL_NOFIELD) continue;
2240
2241 //Now, get data
2242
2243 res = EmGetCmd(receivedCmd, &len);
2244 if (res == 2) { //Field is off!
2245 cardSTATE = MFEMUL_NOFIELD;
2246 LEDsoff();
2247 continue;
2248 } else if (res == 1) {
2249 break; //return value 1 means button press
2250 }
2251
2252 // REQ or WUP request in ANY state and WUP in HALTED state
2253 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2254 selTimer = GetTickCount();
2255 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2256 cardSTATE = MFEMUL_SELECT1;
2257
2258 // init crypto block
2259 LED_B_OFF();
2260 LED_C_OFF();
2261 crypto1_destroy(pcs);
2262 cardAUTHKEY = 0xff;
2263 continue;
2264 }
2265
2266 switch (cardSTATE) {
2267 case MFEMUL_NOFIELD:
2268 case MFEMUL_HALTED:
2269 case MFEMUL_IDLE:{
2270 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2271 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2272 break;
2273 }
2274 case MFEMUL_SELECT1:{
2275 // select all
2276 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2277 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2278 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2279 break;
2280 }
2281
2282 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2283 {
2284 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2285 }
2286 // select card
2287 if (len == 9 &&
2288 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2289 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2290 cuid = bytes_to_num(rUIDBCC1, 4);
2291 if (!_7BUID) {
2292 cardSTATE = MFEMUL_WORK;
2293 LED_B_ON();
2294 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2295 break;
2296 } else {
2297 cardSTATE = MFEMUL_SELECT2;
2298 }
2299 }
2300 break;
2301 }
2302 case MFEMUL_AUTH1:{
2303 if( len != 8)
2304 {
2305 cardSTATE_TO_IDLE();
2306 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2307 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2308 break;
2309 }
2310 uint32_t ar = bytes_to_num(receivedCmd, 4);
2311 uint32_t nr= bytes_to_num(&receivedCmd[4], 4);
2312
2313 //Collect AR/NR
2314 if(ar_nr_collected < 2){
2315 if(ar_nr_responses[2] != ar)
2316 {// Avoid duplicates... probably not necessary, ar should vary.
2317 ar_nr_responses[ar_nr_collected*4] = cuid;
2318 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2319 ar_nr_responses[ar_nr_collected*4+2] = ar;
2320 ar_nr_responses[ar_nr_collected*4+3] = nr;
2321 ar_nr_collected++;
2322 }
2323 }
2324
2325 // --- crypto
2326 crypto1_word(pcs, ar , 1);
2327 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2328
2329 // test if auth OK
2330 if (cardRr != prng_successor(nonce, 64)){
2331 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2332 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2333 cardRr, prng_successor(nonce, 64));
2334 // Shouldn't we respond anything here?
2335 // Right now, we don't nack or anything, which causes the
2336 // reader to do a WUPA after a while. /Martin
2337 // -- which is the correct response. /piwi
2338 cardSTATE_TO_IDLE();
2339 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2340 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2341 break;
2342 }
2343
2344 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2345
2346 num_to_bytes(ans, 4, rAUTH_AT);
2347 // --- crypto
2348 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2349 LED_C_ON();
2350 cardSTATE = MFEMUL_WORK;
2351 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2352 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2353 GetTickCount() - authTimer);
2354 break;
2355 }
2356 case MFEMUL_SELECT2:{
2357 if (!len) {
2358 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2359 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2360 break;
2361 }
2362 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2363 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2364 break;
2365 }
2366
2367 // select 2 card
2368 if (len == 9 &&
2369 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2370 EmSendCmd(rSAK, sizeof(rSAK));
2371 cuid = bytes_to_num(rUIDBCC2, 4);
2372 cardSTATE = MFEMUL_WORK;
2373 LED_B_ON();
2374 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2375 break;
2376 }
2377
2378 // i guess there is a command). go into the work state.
2379 if (len != 4) {
2380 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2381 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2382 break;
2383 }
2384 cardSTATE = MFEMUL_WORK;
2385 //goto lbWORK;
2386 //intentional fall-through to the next case-stmt
2387 }
2388
2389 case MFEMUL_WORK:{
2390 if (len == 0) {
2391 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2392 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2393 break;
2394 }
2395
2396 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2397
2398 if(encrypted_data) {
2399 // decrypt seqence
2400 mf_crypto1_decrypt(pcs, receivedCmd, len);
2401 }
2402
2403 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2404 authTimer = GetTickCount();
2405 cardAUTHSC = receivedCmd[1] / 4; // received block num
2406 cardAUTHKEY = receivedCmd[0] - 0x60;
2407 crypto1_destroy(pcs);//Added by martin
2408 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2409
2410 if (!encrypted_data) { // first authentication
2411 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2412
2413 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2414 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2415 } else { // nested authentication
2416 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2417 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2418 num_to_bytes(ans, 4, rAUTH_AT);
2419 }
2420 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2421 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2422 cardSTATE = MFEMUL_AUTH1;
2423 break;
2424 }
2425
2426 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2427 // BUT... ACK --> NACK
2428 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2429 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2430 break;
2431 }
2432
2433 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2434 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2435 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2436 break;
2437 }
2438
2439 if(len != 4) {
2440 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2441 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2442 break;
2443 }
2444
2445 if(receivedCmd[0] == 0x30 // read block
2446 || receivedCmd[0] == 0xA0 // write block
2447 || receivedCmd[0] == 0xC0 // inc
2448 || receivedCmd[0] == 0xC1 // dec
2449 || receivedCmd[0] == 0xC2 // restore
2450 || receivedCmd[0] == 0xB0) { // transfer
2451 if (receivedCmd[1] >= 16 * 4) {
2452 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2453 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2454 break;
2455 }
2456
2457 if (receivedCmd[1] / 4 != cardAUTHSC) {
2458 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2459 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2460 break;
2461 }
2462 }
2463 // read block
2464 if (receivedCmd[0] == 0x30) {
2465 if (MF_DBGLEVEL >= 4) {
2466 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2467 }
2468 emlGetMem(response, receivedCmd[1], 1);
2469 AppendCrc14443a(response, 16);
2470 mf_crypto1_encrypt(pcs, response, 18, &par);
2471 EmSendCmdPar(response, 18, par);
2472 numReads++;
2473 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2474 Dbprintf("%d reads done, exiting", numReads);
2475 finished = true;
2476 }
2477 break;
2478 }
2479 // write block
2480 if (receivedCmd[0] == 0xA0) {
2481 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2482 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2483 cardSTATE = MFEMUL_WRITEBL2;
2484 cardWRBL = receivedCmd[1];
2485 break;
2486 }
2487 // increment, decrement, restore
2488 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2489 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2490 if (emlCheckValBl(receivedCmd[1])) {
2491 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2492 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2493 break;
2494 }
2495 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2496 if (receivedCmd[0] == 0xC1)
2497 cardSTATE = MFEMUL_INTREG_INC;
2498 if (receivedCmd[0] == 0xC0)
2499 cardSTATE = MFEMUL_INTREG_DEC;
2500 if (receivedCmd[0] == 0xC2)
2501 cardSTATE = MFEMUL_INTREG_REST;
2502 cardWRBL = receivedCmd[1];
2503 break;
2504 }
2505 // transfer
2506 if (receivedCmd[0] == 0xB0) {
2507 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2508 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2509 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2510 else
2511 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2512 break;
2513 }
2514 // halt
2515 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2516 LED_B_OFF();
2517 LED_C_OFF();
2518 cardSTATE = MFEMUL_HALTED;
2519 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2520 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2521 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2522 break;
2523 }
2524 // RATS
2525 if (receivedCmd[0] == 0xe0) {//RATS
2526 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2527 break;
2528 }
2529 // command not allowed
2530 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2531 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2532 break;
2533 }
2534 case MFEMUL_WRITEBL2:{
2535 if (len == 18){
2536 mf_crypto1_decrypt(pcs, receivedCmd, len);
2537 emlSetMem(receivedCmd, cardWRBL, 1);
2538 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2539 cardSTATE = MFEMUL_WORK;
2540 } else {
2541 cardSTATE_TO_IDLE();
2542 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2543 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2544 }
2545 break;
2546 }
2547
2548 case MFEMUL_INTREG_INC:{
2549 mf_crypto1_decrypt(pcs, receivedCmd, len);
2550 memcpy(&ans, receivedCmd, 4);
2551 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2552 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2553 cardSTATE_TO_IDLE();
2554 break;
2555 }
2556 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2557 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2558 cardINTREG = cardINTREG + ans;
2559 cardSTATE = MFEMUL_WORK;
2560 break;
2561 }
2562 case MFEMUL_INTREG_DEC:{
2563 mf_crypto1_decrypt(pcs, receivedCmd, len);
2564 memcpy(&ans, receivedCmd, 4);
2565 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2566 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2567 cardSTATE_TO_IDLE();
2568 break;
2569 }
2570 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2571 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2572 cardINTREG = cardINTREG - ans;
2573 cardSTATE = MFEMUL_WORK;
2574 break;
2575 }
2576 case MFEMUL_INTREG_REST:{
2577 mf_crypto1_decrypt(pcs, receivedCmd, len);
2578 memcpy(&ans, receivedCmd, 4);
2579 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2580 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2581 cardSTATE_TO_IDLE();
2582 break;
2583 }
2584 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2585 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2586 cardSTATE = MFEMUL_WORK;
2587 break;
2588 }
2589 }
2590 }
2591
2592 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2593 LEDsoff();
2594
2595 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2596 {
2597 //May just aswell send the collected ar_nr in the response aswell
2598 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2599 }
2600
2601 if(flags & FLAG_NR_AR_ATTACK)
2602 {
2603 if(ar_nr_collected > 1) {
2604 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2605 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2606 ar_nr_responses[0], // UID
2607 ar_nr_responses[1], //NT
2608 ar_nr_responses[2], //AR1
2609 ar_nr_responses[3], //NR1
2610 ar_nr_responses[6], //AR2
2611 ar_nr_responses[7] //NR2
2612 );
2613 } else {
2614 Dbprintf("Failed to obtain two AR/NR pairs!");
2615 if(ar_nr_collected >0) {
2616 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2617 ar_nr_responses[0], // UID
2618 ar_nr_responses[1], //NT
2619 ar_nr_responses[2], //AR1
2620 ar_nr_responses[3] //NR1
2621 );
2622 }
2623 }
2624 }
2625 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen);
2626 }
2627
2628
2629
2630 //-----------------------------------------------------------------------------
2631 // MIFARE sniffer.
2632 //
2633 //-----------------------------------------------------------------------------
2634 void RAMFUNC SniffMifare(uint8_t param) {
2635 // param:
2636 // bit 0 - trigger from first card answer
2637 // bit 1 - trigger from first reader 7-bit request
2638
2639 // C(red) A(yellow) B(green)
2640 LEDsoff();
2641 // init trace buffer
2642 iso14a_clear_trace();
2643 iso14a_set_tracing(TRUE);
2644
2645 // The command (reader -> tag) that we're receiving.
2646 // The length of a received command will in most cases be no more than 18 bytes.
2647 // So 32 should be enough!
2648 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
2649 // The response (tag -> reader) that we're receiving.
2650 uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET);
2651
2652 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2653 // into trace, along with its length and other annotations.
2654 //uint8_t *trace = (uint8_t *)BigBuf;
2655
2656 // The DMA buffer, used to stream samples from the FPGA
2657 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
2658 uint8_t *data = dmaBuf;
2659 uint8_t previous_data = 0;
2660 int maxDataLen = 0;
2661 int dataLen = 0;
2662 bool ReaderIsActive = FALSE;
2663 bool TagIsActive = FALSE;
2664
2665 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2666
2667 // Set up the demodulator for tag -> reader responses.
2668 Demod.output = receivedResponse;
2669
2670 // Set up the demodulator for the reader -> tag commands
2671 Uart.output = receivedCmd;
2672
2673 // Setup for the DMA.
2674 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2675
2676 LED_D_OFF();
2677
2678 // init sniffer
2679 MfSniffInit();
2680
2681 // And now we loop, receiving samples.
2682 for(uint32_t sniffCounter = 0; TRUE; ) {
2683
2684 if(BUTTON_PRESS()) {
2685 DbpString("cancelled by button");
2686 break;
2687 }
2688
2689 LED_A_ON();
2690 WDT_HIT();
2691
2692 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2693 // check if a transaction is completed (timeout after 2000ms).
2694 // if yes, stop the DMA transfer and send what we have so far to the client
2695 if (MfSniffSend(2000)) {
2696 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2697 sniffCounter = 0;
2698 data = dmaBuf;
2699 maxDataLen = 0;
2700 ReaderIsActive = FALSE;
2701 TagIsActive = FALSE;
2702 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2703 }
2704 }
2705
2706 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2707 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2708 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2709 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2710 } else {
2711 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2712 }
2713 // test for length of buffer
2714 if(dataLen > maxDataLen) { // we are more behind than ever...
2715 maxDataLen = dataLen;
2716 if(dataLen > 400) {
2717 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2718 break;
2719 }
2720 }
2721 if(dataLen < 1) continue;
2722
2723 // primary buffer was stopped ( <-- we lost data!
2724 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2725 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2726 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2727 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2728 }
2729 // secondary buffer sets as primary, secondary buffer was stopped
2730 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2731 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2732 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2733 }
2734
2735 LED_A_OFF();
2736
2737 if (sniffCounter & 0x01) {
2738
2739 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2740 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2741 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2742 LED_C_INV();
2743 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parityBits, Uart.bitCount, TRUE)) break;
2744
2745 /* And ready to receive another command. */
2746 UartReset();
2747
2748 /* And also reset the demod code */
2749 DemodReset();
2750 }
2751 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2752 }
2753
2754 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2755 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2756 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2757 LED_C_INV();
2758
2759 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parityBits, Demod.bitCount, FALSE)) break;
2760
2761 // And ready to receive another response.
2762 DemodReset();
2763 }
2764 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2765 }
2766 }
2767
2768 previous_data = *data;
2769 sniffCounter++;
2770 data++;
2771 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2772 data = dmaBuf;
2773 }
2774
2775 } // main cycle
2776
2777 DbpString("COMMAND FINISHED");
2778
2779 FpgaDisableSscDma();
2780 MfSniffEnd();
2781
2782 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2783 LEDsoff();
2784 }
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