1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
11 #include "proxmark3.h"
21 * Does the sample acquisition. If threshold is specified, the actual sampling
22 * is not commenced until the threshold has been reached.
23 * @param trigger_threshold - the threshold
24 * @param silent - is true, now outputs are made. If false, dbprints the status
26 void DoAcquisition125k_internal(int trigger_threshold
,bool silent
)
28 uint8_t *dest
= BigBuf_get_addr();
29 int n
= BigBuf_max_trace_len();
35 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
36 AT91C_BASE_SSC
->SSC_THR
= 0x43;
39 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
40 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
42 if (trigger_threshold
!= -1 && dest
[i
] < trigger_threshold
)
45 trigger_threshold
= -1;
51 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
52 dest
[0], dest
[1], dest
[2], dest
[3], dest
[4], dest
[5], dest
[6], dest
[7]);
57 * Perform sample aquisition.
59 void DoAcquisition125k(int trigger_threshold
)
61 DoAcquisition125k_internal(trigger_threshold
, false);
65 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
66 * if not already loaded, sets divisor and starts up the antenna.
67 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
71 void LFSetupFPGAForADC(int divisor
, bool lf_field
)
73 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
74 if ( (divisor
== 1) || (divisor
< 0) || (divisor
> 255) )
75 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
76 else if (divisor
== 0)
77 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor
);
81 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| (lf_field
? FPGA_LF_ADC_READER_FIELD
: 0));
83 // Connect the A/D to the peak-detected low-frequency path.
84 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
85 // Give it a bit of time for the resonant antenna to settle.
87 // Now set up the SSC to get the ADC samples that are now streaming at us.
91 * Initializes the FPGA, and acquires the samples.
93 void AcquireRawAdcSamples125k(int divisor
)
95 LFSetupFPGAForADC(divisor
, true);
96 // Now call the acquisition routine
97 DoAcquisition125k_internal(-1,false);
100 * Initializes the FPGA for snoop-mode, and acquires the samples.
103 void SnoopLFRawAdcSamples(int divisor
, int trigger_threshold
)
105 LFSetupFPGAForADC(divisor
, false);
106 DoAcquisition125k(trigger_threshold
);
109 void ModThenAcquireRawAdcSamples125k(int delay_off
, int period_0
, int period_1
, uint8_t *command
)
112 /* Make sure the tag is reset */
113 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
118 int divisor_used
= 95; // 125 KHz
119 // see if 'h' was specified
121 if (command
[strlen((char *) command
) - 1] == 'h')
122 divisor_used
= 88; // 134.8 KHz
125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor_used
);
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
127 // Give it a bit of time for the resonant antenna to settle.
130 // And a little more time for the tag to fully power up
133 // Now set up the SSC to get the ADC samples that are now streaming at us.
136 // now modulate the reader field
137 while(*command
!= '\0' && *command
!= ' ') {
138 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
140 SpinDelayUs(delay_off
);
141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor_used
);
143 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
145 if(*(command
++) == '0')
146 SpinDelayUs(period_0
);
148 SpinDelayUs(period_1
);
150 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
152 SpinDelayUs(delay_off
);
153 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor_used
);
155 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
158 DoAcquisition125k(-1);
161 /* blank r/w tag data stream
162 ...0000000000000000 01111111
163 1010101010101010101010101010101010101010101010101010101010101010
166 101010101010101[0]000...
168 [5555fe852c5555555555555555fe0000]
172 // some hardcoded initial params
173 // when we read a TI tag we sample the zerocross line at 2Mhz
174 // TI tags modulate a 1 as 16 cycles of 123.2Khz
175 // TI tags modulate a 0 as 16 cycles of 134.2Khz
176 #define FSAMPLE 2000000
177 #define FREQLO 123200
178 #define FREQHI 134200
180 signed char *dest
= (signed char *)BigBuf_get_addr();
181 uint16_t n
= BigBuf_max_trace_len();
182 // 128 bit shift register [shift3:shift2:shift1:shift0]
183 uint32_t shift3
= 0, shift2
= 0, shift1
= 0, shift0
= 0;
185 int i
, cycles
=0, samples
=0;
186 // how many sample points fit in 16 cycles of each frequency
187 uint32_t sampleslo
= (FSAMPLE
<<4)/FREQLO
, sampleshi
= (FSAMPLE
<<4)/FREQHI
;
188 // when to tell if we're close enough to one freq or another
189 uint32_t threshold
= (sampleslo
- sampleshi
+ 1)>>1;
191 // TI tags charge at 134.2Khz
192 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
193 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
195 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
196 // connects to SSP_DIN and the SSP_DOUT logic level controls
197 // whether we're modulating the antenna (high)
198 // or listening to the antenna (low)
199 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
201 // get TI tag data into the buffer
204 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
206 for (i
=0; i
<n
-1; i
++) {
207 // count cycles by looking for lo to hi zero crossings
208 if ( (dest
[i
]<0) && (dest
[i
+1]>0) ) {
210 // after 16 cycles, measure the frequency
213 samples
=i
-samples
; // number of samples in these 16 cycles
215 // TI bits are coming to us lsb first so shift them
216 // right through our 128 bit right shift register
217 shift0
= (shift0
>>1) | (shift1
<< 31);
218 shift1
= (shift1
>>1) | (shift2
<< 31);
219 shift2
= (shift2
>>1) | (shift3
<< 31);
222 // check if the cycles fall close to the number
223 // expected for either the low or high frequency
224 if ( (samples
>(sampleslo
-threshold
)) && (samples
<(sampleslo
+threshold
)) ) {
225 // low frequency represents a 1
227 } else if ( (samples
>(sampleshi
-threshold
)) && (samples
<(sampleshi
+threshold
)) ) {
228 // high frequency represents a 0
230 // probably detected a gay waveform or noise
231 // use this as gaydar or discard shift register and start again
232 shift3
= shift2
= shift1
= shift0
= 0;
236 // for each bit we receive, test if we've detected a valid tag
238 // if we see 17 zeroes followed by 6 ones, we might have a tag
239 // remember the bits are backwards
240 if ( ((shift0
& 0x7fffff) == 0x7e0000) ) {
241 // if start and end bytes match, we have a tag so break out of the loop
242 if ( ((shift0
>>16)&0xff) == ((shift3
>>8)&0xff) ) {
243 cycles
= 0xF0B; //use this as a flag (ugly but whatever)
251 // if flag is set we have a tag
253 DbpString("Info: No valid tag detected.");
255 // put 64 bit data into shift1 and shift0
256 shift0
= (shift0
>>24) | (shift1
<< 8);
257 shift1
= (shift1
>>24) | (shift2
<< 8);
259 // align 16 bit crc into lower half of shift2
260 shift2
= ((shift2
>>24) | (shift3
<< 8)) & 0x0ffff;
262 // if r/w tag, check ident match
263 if (shift3
& (1<<15) ) {
264 DbpString("Info: TI tag is rewriteable");
265 // only 15 bits compare, last bit of ident is not valid
266 if (((shift3
>> 16) ^ shift0
) & 0x7fff ) {
267 DbpString("Error: Ident mismatch!");
269 DbpString("Info: TI tag ident is valid");
272 DbpString("Info: TI tag is readonly");
275 // WARNING the order of the bytes in which we calc crc below needs checking
276 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
277 // bytes in reverse or something
281 crc
= update_crc16(crc
, (shift0
)&0xff);
282 crc
= update_crc16(crc
, (shift0
>>8)&0xff);
283 crc
= update_crc16(crc
, (shift0
>>16)&0xff);
284 crc
= update_crc16(crc
, (shift0
>>24)&0xff);
285 crc
= update_crc16(crc
, (shift1
)&0xff);
286 crc
= update_crc16(crc
, (shift1
>>8)&0xff);
287 crc
= update_crc16(crc
, (shift1
>>16)&0xff);
288 crc
= update_crc16(crc
, (shift1
>>24)&0xff);
290 Dbprintf("Info: Tag data: %x%08x, crc=%x",
291 (unsigned int)shift1
, (unsigned int)shift0
, (unsigned int)shift2
& 0xFFFF);
292 if (crc
!= (shift2
&0xffff)) {
293 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc
);
295 DbpString("Info: CRC is good");
300 void WriteTIbyte(uint8_t b
)
304 // modulate 8 bits out to the antenna
308 // stop modulating antenna
315 // stop modulating antenna
325 void AcquireTiType(void)
328 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
329 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
330 #define TIBUFLEN 1250
333 uint32_t *BigBuf
= (uint32_t *)BigBuf_get_addr();
334 memset(BigBuf
,0,BigBuf_max_trace_len()/sizeof(uint32_t));
336 // Set up the synchronous serial port
337 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DIN
;
338 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
;
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
342 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
344 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_SWRST
;
345 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_RXEN
| AT91C_SSC_TXEN
;
347 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
348 // 48/2 = 24 MHz clock must be divided by 12
349 AT91C_BASE_SSC
->SSC_CMR
= 12;
351 AT91C_BASE_SSC
->SSC_RCMR
= SSC_CLOCK_MODE_SELECT(0);
352 AT91C_BASE_SSC
->SSC_RFMR
= SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF
;
353 AT91C_BASE_SSC
->SSC_TCMR
= 0;
354 AT91C_BASE_SSC
->SSC_TFMR
= 0;
361 // Charge TI tag for 50ms.
364 // stop modulating antenna and listen
371 if(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
372 BigBuf
[i
] = AT91C_BASE_SSC
->SSC_RHR
; // store 32 bit values in buffer
373 i
++; if(i
>= TIBUFLEN
) break;
378 // return stolen pin to SSP
379 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DOUT
;
380 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
| GPIO_SSC_DOUT
;
382 char *dest
= (char *)BigBuf_get_addr();
385 for (i
=TIBUFLEN
-1; i
>=0; i
--) {
386 for (j
=0; j
<32; j
++) {
387 if(BigBuf
[i
] & (1 << j
)) {
396 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
397 // if crc provided, it will be written with the data verbatim (even if bogus)
398 // if not provided a valid crc will be computed from the data and written.
399 void WriteTItag(uint32_t idhi
, uint32_t idlo
, uint16_t crc
)
401 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
403 crc
= update_crc16(crc
, (idlo
)&0xff);
404 crc
= update_crc16(crc
, (idlo
>>8)&0xff);
405 crc
= update_crc16(crc
, (idlo
>>16)&0xff);
406 crc
= update_crc16(crc
, (idlo
>>24)&0xff);
407 crc
= update_crc16(crc
, (idhi
)&0xff);
408 crc
= update_crc16(crc
, (idhi
>>8)&0xff);
409 crc
= update_crc16(crc
, (idhi
>>16)&0xff);
410 crc
= update_crc16(crc
, (idhi
>>24)&0xff);
412 Dbprintf("Writing to tag: %x%08x, crc=%x",
413 (unsigned int) idhi
, (unsigned int) idlo
, crc
);
415 // TI tags charge at 134.2Khz
416 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
417 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
418 // connects to SSP_DIN and the SSP_DOUT logic level controls
419 // whether we're modulating the antenna (high)
420 // or listening to the antenna (low)
421 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
424 // steal this pin from the SSP and use it to control the modulation
425 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
426 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
428 // writing algorithm:
429 // a high bit consists of a field off for 1ms and field on for 1ms
430 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
431 // initiate a charge time of 50ms (field on) then immediately start writing bits
432 // start by writing 0xBB (keyword) and 0xEB (password)
433 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
434 // finally end with 0x0300 (write frame)
435 // all data is sent lsb firts
436 // finish with 15ms programming time
440 SpinDelay(50); // charge time
442 WriteTIbyte(0xbb); // keyword
443 WriteTIbyte(0xeb); // password
444 WriteTIbyte( (idlo
)&0xff );
445 WriteTIbyte( (idlo
>>8 )&0xff );
446 WriteTIbyte( (idlo
>>16)&0xff );
447 WriteTIbyte( (idlo
>>24)&0xff );
448 WriteTIbyte( (idhi
)&0xff );
449 WriteTIbyte( (idhi
>>8 )&0xff );
450 WriteTIbyte( (idhi
>>16)&0xff );
451 WriteTIbyte( (idhi
>>24)&0xff ); // data hi to lo
452 WriteTIbyte( (crc
)&0xff ); // crc lo
453 WriteTIbyte( (crc
>>8 )&0xff ); // crc hi
454 WriteTIbyte(0x00); // write frame lo
455 WriteTIbyte(0x03); // write frame hi
457 SpinDelay(50); // programming time
461 // get TI tag data into the buffer
464 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
465 DbpString("Now use tiread to check");
468 void SimulateTagLowFrequency(int period
, int gap
, int ledcontrol
)
471 uint8_t *tab
= BigBuf_get_addr();
473 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
474 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
);
476 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
| GPIO_SSC_CLK
;
478 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
479 AT91C_BASE_PIOA
->PIO_ODR
= GPIO_SSC_CLK
;
481 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
482 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
486 while(!(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
)) {
488 DbpString("Stopped");
505 while(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
) {
507 DbpString("Stopped");
524 #define DEBUG_FRAME_CONTENTS 1
525 void SimulateTagLowFrequencyBidir(int divisor
, int t0
)
529 // compose fc/8 fc/10 waveform
530 static void fc(int c
, int *n
) {
531 uint8_t *dest
= BigBuf_get_addr();
534 // for when we want an fc8 pattern every 4 logical bits
545 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
547 for (idx
=0; idx
<6; idx
++) {
559 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
561 for (idx
=0; idx
<5; idx
++) {
576 // prepare a waveform pattern in the buffer based on the ID given then
577 // simulate a HID tag until the button is pressed
578 void CmdHIDsimTAG(int hi
, int lo
, int ledcontrol
)
582 HID tag bitstream format
583 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
584 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
585 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
586 A fc8 is inserted before every 4 bits
587 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
588 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
592 DbpString("Tags can only have 44 bits.");
596 // special start of frame marker containing invalid bit sequences
597 fc(8, &n
); fc(8, &n
); // invalid
598 fc(8, &n
); fc(10, &n
); // logical 0
599 fc(10, &n
); fc(10, &n
); // invalid
600 fc(8, &n
); fc(10, &n
); // logical 0
603 // manchester encode bits 43 to 32
604 for (i
=11; i
>=0; i
--) {
605 if ((i
%4)==3) fc(0,&n
);
607 fc(10, &n
); fc(8, &n
); // low-high transition
609 fc(8, &n
); fc(10, &n
); // high-low transition
614 // manchester encode bits 31 to 0
615 for (i
=31; i
>=0; i
--) {
616 if ((i
%4)==3) fc(0,&n
);
618 fc(10, &n
); fc(8, &n
); // low-high transition
620 fc(8, &n
); fc(10, &n
); // high-low transition
626 SimulateTagLowFrequency(n
, 0, ledcontrol
);
632 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
633 void CmdHIDdemodFSK(int findone
, int *high
, int *low
, int ledcontrol
)
635 uint8_t *dest
= BigBuf_get_addr();
637 size_t size
=sizeof(BigBuf
);
638 uint32_t hi2
=0, hi
=0, lo
=0;
640 // Configure to go in 125Khz listen mode
641 LFSetupFPGAForADC(95, true);
643 while(!BUTTON_PRESS()) {
646 if (ledcontrol
) LED_A_ON();
648 DoAcquisition125k_internal(-1,true);
650 idx
= HIDdemodFSK(dest
, BigBuf_max_trace_len(), &hi2
, &hi
, &lo
);
652 size
= sizeof(BigBuf
);
654 idx
= HIDdemodFSK(dest
, &size
, &hi2
, &hi
, &lo
);
657 // final loop, go over previously decoded manchester data and decode into usable tag ID
658 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
659 if (hi2
!= 0){ //extra large HID tags
660 Dbprintf("TAG ID: %x%08x%08x (%d)",
661 (unsigned int) hi2
, (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF);
662 }else { //standard HID tags <38 bits
663 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
666 uint32_t cardnum
= 0;
667 if (((hi
>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
669 lo2
=(((hi
& 31) << 12) | (lo
>>20)); //get bits 21-37 to check for format len bit
671 while(lo2
> 1){ //find last bit set to 1 (format len bit)
679 cardnum
= (lo
>>1)&0xFFFF;
683 cardnum
= (lo
>>1)&0x7FFFF;
684 fc
= ((hi
&0xF)<<12)|(lo
>>20);
687 cardnum
= (lo
>>1)&0xFFFF;
688 fc
= ((hi
&1)<<15)|(lo
>>17);
691 cardnum
= (lo
>>1)&0xFFFFF;
692 fc
= ((hi
&1)<<11)|(lo
>>21);
695 else { //if bit 38 is not set then 37 bit format is used
700 cardnum
= (lo
>>1)&0x7FFFF;
701 fc
= ((hi
&0xF)<<12)|(lo
>>20);
704 //Dbprintf("TAG ID: %x%08x (%d)",
705 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
706 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
707 (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF,
708 (unsigned int) bitlen
, (unsigned int) fc
, (unsigned int) cardnum
);
711 if (ledcontrol
) LED_A_OFF();
719 DbpString("Stopped");
720 if (ledcontrol
) LED_A_OFF();
723 void CmdEM410xdemod(int findone
, int *high
, int *low
, int ledcontrol
)
725 uint8_t *dest
= BigBuf_get_addr();
727 size_t size
=0, idx
=0;
728 int clk
=0, invert
=0, errCnt
=0;
730 // Configure to go in 125Khz listen mode
731 LFSetupFPGAForADC(95, true);
733 while(!BUTTON_PRESS()) {
736 if (ledcontrol
) LED_A_ON();
738 DoAcquisition125k_internal(-1,true);
739 size
= BigBuf_max_trace_len();
740 //Dbprintf("DEBUG: Buffer got");
741 //askdemod and manchester decode
742 errCnt
= askmandemod(dest
, &size
, &clk
, &invert
);
743 //Dbprintf("DEBUG: ASK Got");
747 lo
= Em410xDecode(dest
, &size
, &idx
);
748 //Dbprintf("DEBUG: EM GOT");
750 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
753 (uint32_t)(lo
&0xFFFF),
754 (uint32_t)((lo
>>16LL) & 0xFF),
755 (uint32_t)(lo
& 0xFFFFFF));
758 if (ledcontrol
) LED_A_OFF();
762 //Dbprintf("DEBUG: No Tag");
771 DbpString("Stopped");
772 if (ledcontrol
) LED_A_OFF();
775 void CmdIOdemodFSK(int findone
, int *high
, int *low
, int ledcontrol
)
777 uint8_t *dest
= BigBuf_get_addr();
779 uint32_t code
=0, code2
=0;
781 uint8_t facilitycode
=0;
783 // Configure to go in 125Khz listen mode
784 LFSetupFPGAForADC(95, true);
786 while(!BUTTON_PRESS()) {
788 if (ledcontrol
) LED_A_ON();
789 DoAcquisition125k_internal(-1,true);
790 //fskdemod and get start index
792 idx
= IOdemodFSK(dest
, BigBuf_max_trace_len());
797 //0 10 20 30 40 50 60
799 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
800 //-----------------------------------------------------------------------------
801 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
803 //XSF(version)facility:codeone+codetwo
805 if(findone
){ //only print binary if we are doing one
806 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
], dest
[idx
+1], dest
[idx
+2],dest
[idx
+3],dest
[idx
+4],dest
[idx
+5],dest
[idx
+6],dest
[idx
+7],dest
[idx
+8]);
807 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+9], dest
[idx
+10],dest
[idx
+11],dest
[idx
+12],dest
[idx
+13],dest
[idx
+14],dest
[idx
+15],dest
[idx
+16],dest
[idx
+17]);
808 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+18],dest
[idx
+19],dest
[idx
+20],dest
[idx
+21],dest
[idx
+22],dest
[idx
+23],dest
[idx
+24],dest
[idx
+25],dest
[idx
+26]);
809 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+27],dest
[idx
+28],dest
[idx
+29],dest
[idx
+30],dest
[idx
+31],dest
[idx
+32],dest
[idx
+33],dest
[idx
+34],dest
[idx
+35]);
810 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+36],dest
[idx
+37],dest
[idx
+38],dest
[idx
+39],dest
[idx
+40],dest
[idx
+41],dest
[idx
+42],dest
[idx
+43],dest
[idx
+44]);
811 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+45],dest
[idx
+46],dest
[idx
+47],dest
[idx
+48],dest
[idx
+49],dest
[idx
+50],dest
[idx
+51],dest
[idx
+52],dest
[idx
+53]);
812 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest
[idx
+54],dest
[idx
+55],dest
[idx
+56],dest
[idx
+57],dest
[idx
+58],dest
[idx
+59],dest
[idx
+60],dest
[idx
+61],dest
[idx
+62],dest
[idx
+63]);
814 code
= bytebits_to_byte(dest
+idx
,32);
815 code2
= bytebits_to_byte(dest
+idx
+32,32);
816 version
= bytebits_to_byte(dest
+idx
+27,8); //14,4
817 facilitycode
= bytebits_to_byte(dest
+idx
+18,8) ;
818 number
= (bytebits_to_byte(dest
+idx
+36,8)<<8)|(bytebits_to_byte(dest
+idx
+45,8)); //36,9
820 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version
,facilitycode
,number
,code
,code2
);
821 // if we're only looking for one tag
823 if (ledcontrol
) LED_A_OFF();
828 version
=facilitycode
=0;
834 DbpString("Stopped");
835 if (ledcontrol
) LED_A_OFF();
838 /*------------------------------
839 * T5555/T5557/T5567 routines
840 *------------------------------
843 /* T55x7 configuration register definitions */
844 #define T55x7_POR_DELAY 0x00000001
845 #define T55x7_ST_TERMINATOR 0x00000008
846 #define T55x7_PWD 0x00000010
847 #define T55x7_MAXBLOCK_SHIFT 5
848 #define T55x7_AOR 0x00000200
849 #define T55x7_PSKCF_RF_2 0
850 #define T55x7_PSKCF_RF_4 0x00000400
851 #define T55x7_PSKCF_RF_8 0x00000800
852 #define T55x7_MODULATION_DIRECT 0
853 #define T55x7_MODULATION_PSK1 0x00001000
854 #define T55x7_MODULATION_PSK2 0x00002000
855 #define T55x7_MODULATION_PSK3 0x00003000
856 #define T55x7_MODULATION_FSK1 0x00004000
857 #define T55x7_MODULATION_FSK2 0x00005000
858 #define T55x7_MODULATION_FSK1a 0x00006000
859 #define T55x7_MODULATION_FSK2a 0x00007000
860 #define T55x7_MODULATION_MANCHESTER 0x00008000
861 #define T55x7_MODULATION_BIPHASE 0x00010000
862 #define T55x7_BITRATE_RF_8 0
863 #define T55x7_BITRATE_RF_16 0x00040000
864 #define T55x7_BITRATE_RF_32 0x00080000
865 #define T55x7_BITRATE_RF_40 0x000C0000
866 #define T55x7_BITRATE_RF_50 0x00100000
867 #define T55x7_BITRATE_RF_64 0x00140000
868 #define T55x7_BITRATE_RF_100 0x00180000
869 #define T55x7_BITRATE_RF_128 0x001C0000
871 /* T5555 (Q5) configuration register definitions */
872 #define T5555_ST_TERMINATOR 0x00000001
873 #define T5555_MAXBLOCK_SHIFT 0x00000001
874 #define T5555_MODULATION_MANCHESTER 0
875 #define T5555_MODULATION_PSK1 0x00000010
876 #define T5555_MODULATION_PSK2 0x00000020
877 #define T5555_MODULATION_PSK3 0x00000030
878 #define T5555_MODULATION_FSK1 0x00000040
879 #define T5555_MODULATION_FSK2 0x00000050
880 #define T5555_MODULATION_BIPHASE 0x00000060
881 #define T5555_MODULATION_DIRECT 0x00000070
882 #define T5555_INVERT_OUTPUT 0x00000080
883 #define T5555_PSK_RF_2 0
884 #define T5555_PSK_RF_4 0x00000100
885 #define T5555_PSK_RF_8 0x00000200
886 #define T5555_USE_PWD 0x00000400
887 #define T5555_USE_AOR 0x00000800
888 #define T5555_BITRATE_SHIFT 12
889 #define T5555_FAST_WRITE 0x00004000
890 #define T5555_PAGE_SELECT 0x00008000
893 * Relevant times in microsecond
894 * To compensate antenna falling times shorten the write times
895 * and enlarge the gap ones.
897 #define START_GAP 250
898 #define WRITE_GAP 160
899 #define WRITE_0 144 // 192
900 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
902 // Write one bit to card
903 void T55xxWriteBit(int bit
)
905 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
906 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
907 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
909 SpinDelayUs(WRITE_0
);
911 SpinDelayUs(WRITE_1
);
912 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
913 SpinDelayUs(WRITE_GAP
);
916 // Write one card block in page 0, no lock
917 void T55xxWriteBlock(uint32_t Data
, uint32_t Block
, uint32_t Pwd
, uint8_t PwdMode
)
919 //unsigned int i; //enio adjustment 12/10/14
922 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
923 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
924 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
926 // Give it a bit of time for the resonant antenna to settle.
927 // And for the tag to fully power up
930 // Now start writting
931 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
932 SpinDelayUs(START_GAP
);
936 T55xxWriteBit(0); //Page 0
939 for (i
= 0x80000000; i
!= 0; i
>>= 1)
940 T55xxWriteBit(Pwd
& i
);
946 for (i
= 0x80000000; i
!= 0; i
>>= 1)
947 T55xxWriteBit(Data
& i
);
950 for (i
= 0x04; i
!= 0; i
>>= 1)
951 T55xxWriteBit(Block
& i
);
953 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
954 // so wait a little more)
955 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
956 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
958 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
961 // Read one card block in page 0
962 void T55xxReadBlock(uint32_t Block
, uint32_t Pwd
, uint8_t PwdMode
)
964 uint8_t *dest
= BigBuf_get_addr();
965 //int m=0, i=0; //enio adjustment 12/10/14
967 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
968 m
= BigBuf_max_trace_len();
969 // Clear destination buffer before sending the command
970 memset(dest
, 128, m
);
971 // Connect the A/D to the peak-detected low-frequency path.
972 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
973 // Now set up the SSC to get the ADC samples that are now streaming at us.
977 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
978 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
980 // Give it a bit of time for the resonant antenna to settle.
981 // And for the tag to fully power up
984 // Now start writting
985 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
986 SpinDelayUs(START_GAP
);
990 T55xxWriteBit(0); //Page 0
993 for (i
= 0x80000000; i
!= 0; i
>>= 1)
994 T55xxWriteBit(Pwd
& i
);
999 for (i
= 0x04; i
!= 0; i
>>= 1)
1000 T55xxWriteBit(Block
& i
);
1002 // Turn field on to read the response
1003 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1004 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1006 // Now do the acquisition
1009 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1010 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1012 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1013 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1014 // we don't care about actual value, only if it's more or less than a
1015 // threshold essentially we capture zero crossings for later analysis
1016 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1022 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1027 // Read card traceability data (page 1)
1028 void T55xxReadTrace(void){
1029 uint8_t *dest
= BigBuf_get_addr();
1032 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1033 m
= BigBuf_max_trace_len();
1034 // Clear destination buffer before sending the command
1035 memset(dest
, 128, m
);
1036 // Connect the A/D to the peak-detected low-frequency path.
1037 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1038 // Now set up the SSC to get the ADC samples that are now streaming at us.
1042 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1043 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1045 // Give it a bit of time for the resonant antenna to settle.
1046 // And for the tag to fully power up
1049 // Now start writting
1050 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1051 SpinDelayUs(START_GAP
);
1055 T55xxWriteBit(1); //Page 1
1057 // Turn field on to read the response
1058 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1059 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1061 // Now do the acquisition
1064 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1065 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1067 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1068 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1074 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1079 /*-------------- Cloning routines -----------*/
1080 // Copy HID id to card and setup block 0 config
1081 void CopyHIDtoT55x7(uint32_t hi2
, uint32_t hi
, uint32_t lo
, uint8_t longFMT
)
1083 int data1
=0, data2
=0, data3
=0, data4
=0, data5
=0, data6
=0; //up to six blocks for long format
1087 // Ensure no more than 84 bits supplied
1089 DbpString("Tags can only have 84 bits.");
1092 // Build the 6 data blocks for supplied 84bit ID
1094 data1
= 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1095 for (int i
=0;i
<4;i
++) {
1096 if (hi2
& (1<<(19-i
)))
1097 data1
|= (1<<(((3-i
)*2)+1)); // 1 -> 10
1099 data1
|= (1<<((3-i
)*2)); // 0 -> 01
1103 for (int i
=0;i
<16;i
++) {
1104 if (hi2
& (1<<(15-i
)))
1105 data2
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1107 data2
|= (1<<((15-i
)*2)); // 0 -> 01
1111 for (int i
=0;i
<16;i
++) {
1112 if (hi
& (1<<(31-i
)))
1113 data3
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1115 data3
|= (1<<((15-i
)*2)); // 0 -> 01
1119 for (int i
=0;i
<16;i
++) {
1120 if (hi
& (1<<(15-i
)))
1121 data4
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1123 data4
|= (1<<((15-i
)*2)); // 0 -> 01
1127 for (int i
=0;i
<16;i
++) {
1128 if (lo
& (1<<(31-i
)))
1129 data5
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1131 data5
|= (1<<((15-i
)*2)); // 0 -> 01
1135 for (int i
=0;i
<16;i
++) {
1136 if (lo
& (1<<(15-i
)))
1137 data6
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1139 data6
|= (1<<((15-i
)*2)); // 0 -> 01
1143 // Ensure no more than 44 bits supplied
1145 DbpString("Tags can only have 44 bits.");
1149 // Build the 3 data blocks for supplied 44bit ID
1152 data1
= 0x1D000000; // load preamble
1154 for (int i
=0;i
<12;i
++) {
1155 if (hi
& (1<<(11-i
)))
1156 data1
|= (1<<(((11-i
)*2)+1)); // 1 -> 10
1158 data1
|= (1<<((11-i
)*2)); // 0 -> 01
1162 for (int i
=0;i
<16;i
++) {
1163 if (lo
& (1<<(31-i
)))
1164 data2
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1166 data2
|= (1<<((15-i
)*2)); // 0 -> 01
1170 for (int i
=0;i
<16;i
++) {
1171 if (lo
& (1<<(15-i
)))
1172 data3
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1174 data3
|= (1<<((15-i
)*2)); // 0 -> 01
1179 // Program the data blocks for supplied ID
1180 // and the block 0 for HID format
1181 T55xxWriteBlock(data1
,1,0,0);
1182 T55xxWriteBlock(data2
,2,0,0);
1183 T55xxWriteBlock(data3
,3,0,0);
1185 if (longFMT
) { // if long format there are 6 blocks
1186 T55xxWriteBlock(data4
,4,0,0);
1187 T55xxWriteBlock(data5
,5,0,0);
1188 T55xxWriteBlock(data6
,6,0,0);
1191 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1192 T55xxWriteBlock(T55x7_BITRATE_RF_50
|
1193 T55x7_MODULATION_FSK2a
|
1194 last_block
<< T55x7_MAXBLOCK_SHIFT
,
1202 void CopyIOtoT55x7(uint32_t hi
, uint32_t lo
, uint8_t longFMT
)
1204 int data1
=0, data2
=0; //up to six blocks for long format
1206 data1
= hi
; // load preamble
1210 // Program the data blocks for supplied ID
1211 // and the block 0 for HID format
1212 T55xxWriteBlock(data1
,1,0,0);
1213 T55xxWriteBlock(data2
,2,0,0);
1216 T55xxWriteBlock(0x00147040,0,0,0);
1222 // Define 9bit header for EM410x tags
1223 #define EM410X_HEADER 0x1FF
1224 #define EM410X_ID_LENGTH 40
1226 void WriteEM410x(uint32_t card
, uint32_t id_hi
, uint32_t id_lo
)
1229 uint64_t id
= EM410X_HEADER
;
1230 uint64_t rev_id
= 0; // reversed ID
1231 int c_parity
[4]; // column parity
1232 int r_parity
= 0; // row parity
1235 // Reverse ID bits given as parameter (for simpler operations)
1236 for (i
= 0; i
< EM410X_ID_LENGTH
; ++i
) {
1238 rev_id
= (rev_id
<< 1) | (id_lo
& 1);
1241 rev_id
= (rev_id
<< 1) | (id_hi
& 1);
1246 for (i
= 0; i
< EM410X_ID_LENGTH
; ++i
) {
1247 id_bit
= rev_id
& 1;
1250 // Don't write row parity bit at start of parsing
1252 id
= (id
<< 1) | r_parity
;
1253 // Start counting parity for new row
1260 // First elements in column?
1262 // Fill out first elements
1263 c_parity
[i
] = id_bit
;
1265 // Count column parity
1266 c_parity
[i
% 4] ^= id_bit
;
1269 id
= (id
<< 1) | id_bit
;
1273 // Insert parity bit of last row
1274 id
= (id
<< 1) | r_parity
;
1276 // Fill out column parity at the end of tag
1277 for (i
= 0; i
< 4; ++i
)
1278 id
= (id
<< 1) | c_parity
[i
];
1283 Dbprintf("Started writing %s tag ...", card
? "T55x7":"T5555");
1287 T55xxWriteBlock((uint32_t)(id
>> 32), 1, 0, 0);
1288 T55xxWriteBlock((uint32_t)id
, 2, 0, 0);
1290 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1292 // Clock rate is stored in bits 8-15 of the card value
1293 clock
= (card
& 0xFF00) >> 8;
1294 Dbprintf("Clock rate: %d", clock
);
1298 clock
= T55x7_BITRATE_RF_32
;
1301 clock
= T55x7_BITRATE_RF_16
;
1304 // A value of 0 is assumed to be 64 for backwards-compatibility
1307 clock
= T55x7_BITRATE_RF_64
;
1310 Dbprintf("Invalid clock rate: %d", clock
);
1314 // Writing configuration for T55x7 tag
1315 T55xxWriteBlock(clock
|
1316 T55x7_MODULATION_MANCHESTER
|
1317 2 << T55x7_MAXBLOCK_SHIFT
,
1321 // Writing configuration for T5555(Q5) tag
1322 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT
|
1323 T5555_MODULATION_MANCHESTER
|
1324 2 << T5555_MAXBLOCK_SHIFT
,
1328 Dbprintf("Tag %s written with 0x%08x%08x\n", card
? "T55x7":"T5555",
1329 (uint32_t)(id
>> 32), (uint32_t)id
);
1332 // Clone Indala 64-bit tag by UID to T55x7
1333 void CopyIndala64toT55x7(int hi
, int lo
)
1336 //Program the 2 data blocks for supplied 64bit UID
1337 // and the block 0 for Indala64 format
1338 T55xxWriteBlock(hi
,1,0,0);
1339 T55xxWriteBlock(lo
,2,0,0);
1340 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1341 T55xxWriteBlock(T55x7_BITRATE_RF_32
|
1342 T55x7_MODULATION_PSK1
|
1343 2 << T55x7_MAXBLOCK_SHIFT
,
1345 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1346 // T5567WriteBlock(0x603E1042,0);
1352 void CopyIndala224toT55x7(int uid1
, int uid2
, int uid3
, int uid4
, int uid5
, int uid6
, int uid7
)
1355 //Program the 7 data blocks for supplied 224bit UID
1356 // and the block 0 for Indala224 format
1357 T55xxWriteBlock(uid1
,1,0,0);
1358 T55xxWriteBlock(uid2
,2,0,0);
1359 T55xxWriteBlock(uid3
,3,0,0);
1360 T55xxWriteBlock(uid4
,4,0,0);
1361 T55xxWriteBlock(uid5
,5,0,0);
1362 T55xxWriteBlock(uid6
,6,0,0);
1363 T55xxWriteBlock(uid7
,7,0,0);
1364 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1365 T55xxWriteBlock(T55x7_BITRATE_RF_32
|
1366 T55x7_MODULATION_PSK1
|
1367 7 << T55x7_MAXBLOCK_SHIFT
,
1369 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1370 // T5567WriteBlock(0x603E10E2,0);
1377 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1378 #define max(x,y) ( x<y ? y:x)
1380 int DemodPCF7931(uint8_t **outBlocks
) {
1381 uint8_t BitStream
[256];
1382 uint8_t Blocks
[8][16];
1383 uint8_t *GraphBuffer
= BigBuf_get_addr();
1384 int GraphTraceLen
= BigBuf_max_trace_len();
1385 int i
, j
, lastval
, bitidx
, half_switch
;
1387 int tolerance
= clock
/ 8;
1388 int pmc
, block_done
;
1389 int lc
, warnings
= 0;
1391 int lmin
=128, lmax
=128;
1394 AcquireRawAdcSamples125k(0);
1401 /* Find first local max/min */
1402 if(GraphBuffer
[1] > GraphBuffer
[0]) {
1403 while(i
< GraphTraceLen
) {
1404 if( !(GraphBuffer
[i
] > GraphBuffer
[i
-1]) && GraphBuffer
[i
] > lmax
)
1411 while(i
< GraphTraceLen
) {
1412 if( !(GraphBuffer
[i
] < GraphBuffer
[i
-1]) && GraphBuffer
[i
] < lmin
)
1424 for (bitidx
= 0; i
< GraphTraceLen
; i
++)
1426 if ( (GraphBuffer
[i
-1] > GraphBuffer
[i
] && dir
== 1 && GraphBuffer
[i
] > lmax
) || (GraphBuffer
[i
-1] < GraphBuffer
[i
] && dir
== 0 && GraphBuffer
[i
] < lmin
))
1431 // Switch depending on lc length:
1432 // Tolerance is 1/8 of clock rate (arbitrary)
1433 if (abs(lc
-clock
/4) < tolerance
) {
1435 if((i
- pmc
) == lc
) { /* 16T0 was previous one */
1437 i
+= (128+127+16+32+33+16)-1;
1445 } else if (abs(lc
-clock
/2) < tolerance
) {
1447 if((i
- pmc
) == lc
) { /* 16T0 was previous one */
1449 i
+= (128+127+16+32+33)-1;
1454 else if(half_switch
== 1) {
1455 BitStream
[bitidx
++] = 0;
1460 } else if (abs(lc
-clock
) < tolerance
) {
1462 BitStream
[bitidx
++] = 1;
1468 Dbprintf("Error: too many detection errors, aborting.");
1473 if(block_done
== 1) {
1475 for(j
=0; j
<16; j
++) {
1476 Blocks
[num_blocks
][j
] = 128*BitStream
[j
*8+7]+
1477 64*BitStream
[j
*8+6]+
1478 32*BitStream
[j
*8+5]+
1479 16*BitStream
[j
*8+4]+
1491 if(i
< GraphTraceLen
)
1493 if (GraphBuffer
[i
-1] > GraphBuffer
[i
]) dir
=0;
1500 if(num_blocks
== 4) break;
1502 memcpy(outBlocks
, Blocks
, 16*num_blocks
);
1506 int IsBlock0PCF7931(uint8_t *Block
) {
1507 // Assume RFU means 0 :)
1508 if((memcmp(Block
, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block
+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1510 if((memcmp(Block
+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block
[7] == 0) // PAC disabled, can it *really* happen ?
1515 int IsBlock1PCF7931(uint8_t *Block
) {
1516 // Assume RFU means 0 :)
1517 if(Block
[10] == 0 && Block
[11] == 0 && Block
[12] == 0 && Block
[13] == 0)
1518 if((Block
[14] & 0x7f) <= 9 && Block
[15] <= 9)
1526 void ReadPCF7931() {
1527 uint8_t Blocks
[8][17];
1528 uint8_t tmpBlocks
[4][16];
1529 int i
, j
, ind
, ind2
, n
;
1536 memset(Blocks
, 0, 8*17*sizeof(uint8_t));
1539 memset(tmpBlocks
, 0, 4*16*sizeof(uint8_t));
1540 n
= DemodPCF7931((uint8_t**)tmpBlocks
);
1543 if(error
==10 && num_blocks
== 0) {
1544 Dbprintf("Error, no tag or bad tag");
1547 else if (tries
==20 || error
==10) {
1548 Dbprintf("Error reading the tag");
1549 Dbprintf("Here is the partial content");
1554 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1555 tmpBlocks
[i
][0], tmpBlocks
[i
][1], tmpBlocks
[i
][2], tmpBlocks
[i
][3], tmpBlocks
[i
][4], tmpBlocks
[i
][5], tmpBlocks
[i
][6], tmpBlocks
[i
][7],
1556 tmpBlocks
[i
][8], tmpBlocks
[i
][9], tmpBlocks
[i
][10], tmpBlocks
[i
][11], tmpBlocks
[i
][12], tmpBlocks
[i
][13], tmpBlocks
[i
][14], tmpBlocks
[i
][15]);
1558 for(i
=0; i
<n
; i
++) {
1559 if(IsBlock0PCF7931(tmpBlocks
[i
])) {
1561 if(i
< n
-1 && IsBlock1PCF7931(tmpBlocks
[i
+1])) {
1565 memcpy(Blocks
[0], tmpBlocks
[i
], 16);
1566 Blocks
[0][ALLOC
] = 1;
1567 memcpy(Blocks
[1], tmpBlocks
[i
+1], 16);
1568 Blocks
[1][ALLOC
] = 1;
1569 max_blocks
= max((Blocks
[1][14] & 0x7f), Blocks
[1][15]) + 1;
1571 Dbprintf("(dbg) Max blocks: %d", max_blocks
);
1573 // Handle following blocks
1574 for(j
=i
+2, ind2
=2; j
!=i
; j
++, ind2
++, num_blocks
++) {
1577 memcpy(Blocks
[ind2
], tmpBlocks
[j
], 16);
1578 Blocks
[ind2
][ALLOC
] = 1;
1586 for(i
=0; i
<n
; i
++) { // Look for identical block in known blocks
1587 if(memcmp(tmpBlocks
[i
], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1588 for(j
=0; j
<max_blocks
; j
++) {
1589 if(Blocks
[j
][ALLOC
] == 1 && !memcmp(tmpBlocks
[i
], Blocks
[j
], 16)) {
1590 // Found an identical block
1591 for(ind
=i
-1,ind2
=j
-1; ind
>= 0; ind
--,ind2
--) {
1594 if(!Blocks
[ind2
][ALLOC
]) { // Block ind2 not already found
1595 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1596 memcpy(Blocks
[ind2
], tmpBlocks
[ind
], 16);
1597 Blocks
[ind2
][ALLOC
] = 1;
1599 if(num_blocks
== max_blocks
) goto end
;
1602 for(ind
=i
+1,ind2
=j
+1; ind
< n
; ind
++,ind2
++) {
1603 if(ind2
> max_blocks
)
1605 if(!Blocks
[ind2
][ALLOC
]) { // Block ind2 not already found
1606 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1607 memcpy(Blocks
[ind2
], tmpBlocks
[ind
], 16);
1608 Blocks
[ind2
][ALLOC
] = 1;
1610 if(num_blocks
== max_blocks
) goto end
;
1619 if (BUTTON_PRESS()) return;
1620 } while (num_blocks
!= max_blocks
);
1622 Dbprintf("-----------------------------------------");
1623 Dbprintf("Memory content:");
1624 Dbprintf("-----------------------------------------");
1625 for(i
=0; i
<max_blocks
; i
++) {
1626 if(Blocks
[i
][ALLOC
]==1)
1627 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1628 Blocks
[i
][0], Blocks
[i
][1], Blocks
[i
][2], Blocks
[i
][3], Blocks
[i
][4], Blocks
[i
][5], Blocks
[i
][6], Blocks
[i
][7],
1629 Blocks
[i
][8], Blocks
[i
][9], Blocks
[i
][10], Blocks
[i
][11], Blocks
[i
][12], Blocks
[i
][13], Blocks
[i
][14], Blocks
[i
][15]);
1631 Dbprintf("<missing block %d>", i
);
1633 Dbprintf("-----------------------------------------");
1639 //-----------------------------------
1640 // EM4469 / EM4305 routines
1641 //-----------------------------------
1642 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1643 #define FWD_CMD_WRITE 0xA
1644 #define FWD_CMD_READ 0x9
1645 #define FWD_CMD_DISABLE 0x5
1648 uint8_t forwardLink_data
[64]; //array of forwarded bits
1649 uint8_t * forward_ptr
; //ptr for forward message preparation
1650 uint8_t fwd_bit_sz
; //forwardlink bit counter
1651 uint8_t * fwd_write_ptr
; //forwardlink bit pointer
1653 //====================================================================
1654 // prepares command bits
1656 //====================================================================
1657 //--------------------------------------------------------------------
1658 uint8_t Prepare_Cmd( uint8_t cmd
) {
1659 //--------------------------------------------------------------------
1661 *forward_ptr
++ = 0; //start bit
1662 *forward_ptr
++ = 0; //second pause for 4050 code
1664 *forward_ptr
++ = cmd
;
1666 *forward_ptr
++ = cmd
;
1668 *forward_ptr
++ = cmd
;
1670 *forward_ptr
++ = cmd
;
1672 return 6; //return number of emited bits
1675 //====================================================================
1676 // prepares address bits
1678 //====================================================================
1680 //--------------------------------------------------------------------
1681 uint8_t Prepare_Addr( uint8_t addr
) {
1682 //--------------------------------------------------------------------
1684 register uint8_t line_parity
;
1689 *forward_ptr
++ = addr
;
1690 line_parity
^= addr
;
1694 *forward_ptr
++ = (line_parity
& 1);
1696 return 7; //return number of emited bits
1699 //====================================================================
1700 // prepares data bits intreleaved with parity bits
1702 //====================================================================
1704 //--------------------------------------------------------------------
1705 uint8_t Prepare_Data( uint16_t data_low
, uint16_t data_hi
) {
1706 //--------------------------------------------------------------------
1708 register uint8_t line_parity
;
1709 register uint8_t column_parity
;
1710 register uint8_t i
, j
;
1711 register uint16_t data
;
1716 for(i
=0; i
<4; i
++) {
1718 for(j
=0; j
<8; j
++) {
1719 line_parity
^= data
;
1720 column_parity
^= (data
& 1) << j
;
1721 *forward_ptr
++ = data
;
1724 *forward_ptr
++ = line_parity
;
1729 for(j
=0; j
<8; j
++) {
1730 *forward_ptr
++ = column_parity
;
1731 column_parity
>>= 1;
1735 return 45; //return number of emited bits
1738 //====================================================================
1739 // Forward Link send function
1740 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1741 // fwd_bit_count set with number of bits to be sent
1742 //====================================================================
1743 void SendForward(uint8_t fwd_bit_count
) {
1745 fwd_write_ptr
= forwardLink_data
;
1746 fwd_bit_sz
= fwd_bit_count
;
1751 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1752 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1753 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1755 // Give it a bit of time for the resonant antenna to settle.
1756 // And for the tag to fully power up
1759 // force 1st mod pulse (start gap must be longer for 4305)
1760 fwd_bit_sz
--; //prepare next bit modulation
1762 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1763 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1764 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1765 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);//field on
1766 SpinDelayUs(16*8); //16 cycles on (8us each)
1768 // now start writting
1769 while(fwd_bit_sz
-- > 0) { //prepare next bit modulation
1770 if(((*fwd_write_ptr
++) & 1) == 1)
1771 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1773 //These timings work for 4469/4269/4305 (with the 55*8 above)
1774 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1775 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1776 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1777 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);//field on
1778 SpinDelayUs(9*8); //16 cycles on (8us each)
1783 void EM4xLogin(uint32_t Password
) {
1785 uint8_t fwd_bit_count
;
1787 forward_ptr
= forwardLink_data
;
1788 fwd_bit_count
= Prepare_Cmd( FWD_CMD_LOGIN
);
1789 fwd_bit_count
+= Prepare_Data( Password
&0xFFFF, Password
>>16 );
1791 SendForward(fwd_bit_count
);
1793 //Wait for command to complete
1798 void EM4xReadWord(uint8_t Address
, uint32_t Pwd
, uint8_t PwdMode
) {
1800 uint8_t fwd_bit_count
;
1801 uint8_t *dest
= BigBuf_get_addr();
1804 //If password mode do login
1805 if (PwdMode
== 1) EM4xLogin(Pwd
);
1807 forward_ptr
= forwardLink_data
;
1808 fwd_bit_count
= Prepare_Cmd( FWD_CMD_READ
);
1809 fwd_bit_count
+= Prepare_Addr( Address
);
1811 m
= BigBuf_max_trace_len();
1812 // Clear destination buffer before sending the command
1813 memset(dest
, 128, m
);
1814 // Connect the A/D to the peak-detected low-frequency path.
1815 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1816 // Now set up the SSC to get the ADC samples that are now streaming at us.
1819 SendForward(fwd_bit_count
);
1821 // Now do the acquisition
1824 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1825 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1827 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1828 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1833 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1837 void EM4xWriteWord(uint32_t Data
, uint8_t Address
, uint32_t Pwd
, uint8_t PwdMode
) {
1839 uint8_t fwd_bit_count
;
1841 //If password mode do login
1842 if (PwdMode
== 1) EM4xLogin(Pwd
);
1844 forward_ptr
= forwardLink_data
;
1845 fwd_bit_count
= Prepare_Cmd( FWD_CMD_WRITE
);
1846 fwd_bit_count
+= Prepare_Addr( Address
);
1847 fwd_bit_count
+= Prepare_Data( Data
&0xFFFF, Data
>>16 );
1849 SendForward(fwd_bit_count
);
1851 //Wait for write to complete
1853 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off