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ADD: added support for some NTAG/EV1 commands to "hf 14a sim" on device side.
[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18 #include "iso14443crc.h"
19 #include "iso14443a.h"
20 #include "crapto1.h"
21 #include "mifareutil.h"
22 #include "BigBuf.h"
23 static uint32_t iso14a_timeout;
24 int rsamples = 0;
25 uint8_t trigger = 0;
26 // the block number for the ISO14443-4 PCB
27 static uint8_t iso14_pcb_blocknum = 0;
28
29 //
30 // ISO14443 timing:
31 //
32 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
33 #define REQUEST_GUARD_TIME (7000/16 + 1)
34 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
35 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
36 // bool LastCommandWasRequest = FALSE;
37
38 //
39 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
40 //
41 // When the PM acts as reader and is receiving tag data, it takes
42 // 3 ticks delay in the AD converter
43 // 16 ticks until the modulation detector completes and sets curbit
44 // 8 ticks until bit_to_arm is assigned from curbit
45 // 8*16 ticks for the transfer from FPGA to ARM
46 // 4*16 ticks until we measure the time
47 // - 8*16 ticks because we measure the time of the previous transfer
48 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
49
50 // When the PM acts as a reader and is sending, it takes
51 // 4*16 ticks until we can write data to the sending hold register
52 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
53 // 8 ticks until the first transfer starts
54 // 8 ticks later the FPGA samples the data
55 // 1 tick to assign mod_sig_coil
56 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
57
58 // When the PM acts as tag and is receiving it takes
59 // 2 ticks delay in the RF part (for the first falling edge),
60 // 3 ticks for the A/D conversion,
61 // 8 ticks on average until the start of the SSC transfer,
62 // 8 ticks until the SSC samples the first data
63 // 7*16 ticks to complete the transfer from FPGA to ARM
64 // 8 ticks until the next ssp_clk rising edge
65 // 4*16 ticks until we measure the time
66 // - 8*16 ticks because we measure the time of the previous transfer
67 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
68
69 // The FPGA will report its internal sending delay in
70 uint16_t FpgaSendQueueDelay;
71 // the 5 first bits are the number of bits buffered in mod_sig_buf
72 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
73 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
74
75 // When the PM acts as tag and is sending, it takes
76 // 4*16 ticks until we can write data to the sending hold register
77 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
78 // 8 ticks until the first transfer starts
79 // 8 ticks later the FPGA samples the data
80 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
81 // + 1 tick to assign mod_sig_coil
82 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
83
84 // When the PM acts as sniffer and is receiving tag data, it takes
85 // 3 ticks A/D conversion
86 // 14 ticks to complete the modulation detection
87 // 8 ticks (on average) until the result is stored in to_arm
88 // + the delays in transferring data - which is the same for
89 // sniffing reader and tag data and therefore not relevant
90 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
91
92 // When the PM acts as sniffer and is receiving reader data, it takes
93 // 2 ticks delay in analogue RF receiver (for the falling edge of the
94 // start bit, which marks the start of the communication)
95 // 3 ticks A/D conversion
96 // 8 ticks on average until the data is stored in to_arm.
97 // + the delays in transferring data - which is the same for
98 // sniffing reader and tag data and therefore not relevant
99 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
100
101 //variables used for timing purposes:
102 //these are in ssp_clk cycles:
103 static uint32_t NextTransferTime;
104 static uint32_t LastTimeProxToAirStart;
105 static uint32_t LastProxToAirDuration;
106
107
108
109 // CARD TO READER - manchester
110 // Sequence D: 11110000 modulation with subcarrier during first half
111 // Sequence E: 00001111 modulation with subcarrier during second half
112 // Sequence F: 00000000 no modulation with subcarrier
113 // READER TO CARD - miller
114 // Sequence X: 00001100 drop after half a period
115 // Sequence Y: 00000000 no drop
116 // Sequence Z: 11000000 drop at start
117 #define SEC_D 0xf0
118 #define SEC_E 0x0f
119 #define SEC_F 0x00
120 #define SEC_X 0x0c
121 #define SEC_Y 0x00
122 #define SEC_Z 0xc0
123
124 const uint8_t OddByteParity[256] = {
125 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
126 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
141 };
142
143
144 void iso14a_set_trigger(bool enable) {
145 trigger = enable;
146 }
147
148
149 void iso14a_set_timeout(uint32_t timeout) {
150 iso14a_timeout = timeout;
151 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
152 }
153
154
155 void iso14a_set_ATS_timeout(uint8_t *ats) {
156
157 uint8_t tb1;
158 uint8_t fwi;
159 uint32_t fwt;
160
161 if (ats[0] > 1) { // there is a format byte T0
162 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
163 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
164 tb1 = ats[3];
165 } else {
166 tb1 = ats[2];
167 }
168 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
169 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
170
171 iso14a_set_timeout(fwt/(8*16));
172 }
173 }
174 }
175
176
177 //-----------------------------------------------------------------------------
178 // Generate the parity value for a byte sequence
179 //
180 //-----------------------------------------------------------------------------
181 byte_t oddparity (const byte_t bt)
182 {
183 return OddByteParity[bt];
184 }
185
186 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
187 {
188 uint16_t paritybit_cnt = 0;
189 uint16_t paritybyte_cnt = 0;
190 uint8_t parityBits = 0;
191
192 for (uint16_t i = 0; i < iLen; i++) {
193 // Generate the parity bits
194 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
195 if (paritybit_cnt == 7) {
196 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
197 parityBits = 0; // and advance to next Parity Byte
198 paritybyte_cnt++;
199 paritybit_cnt = 0;
200 } else {
201 paritybit_cnt++;
202 }
203 }
204
205 // save remaining parity bits
206 par[paritybyte_cnt] = parityBits;
207
208 }
209
210 void AppendCrc14443a(uint8_t* data, int len)
211 {
212 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
213 }
214
215 void AppendCrc14443b(uint8_t* data, int len)
216 {
217 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
218 }
219
220
221 //=============================================================================
222 // ISO 14443 Type A - Miller decoder
223 //=============================================================================
224 // Basics:
225 // This decoder is used when the PM3 acts as a tag.
226 // The reader will generate "pauses" by temporarily switching of the field.
227 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
228 // The FPGA does a comparison with a threshold and would deliver e.g.:
229 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
230 // The Miller decoder needs to identify the following sequences:
231 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
232 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
233 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
234 // Note 1: the bitstream may start at any time. We therefore need to sync.
235 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
236 //-----------------------------------------------------------------------------
237 static tUart Uart;
238
239 // Lookup-Table to decide if 4 raw bits are a modulation.
240 // We accept the following:
241 // 0001 - a 3 tick wide pause
242 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
243 // 0111 - a 2 tick wide pause shifted left
244 // 1001 - a 2 tick wide pause shifted right
245 const bool Mod_Miller_LUT[] = {
246 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
247 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
248 };
249 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
250 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
251
252 void UartReset()
253 {
254 Uart.state = STATE_UNSYNCD;
255 Uart.bitCount = 0;
256 Uart.len = 0; // number of decoded data bytes
257 Uart.parityLen = 0; // number of decoded parity bytes
258 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
259 Uart.parityBits = 0; // holds 8 parity bits
260 Uart.startTime = 0;
261 Uart.endTime = 0;
262
263 Uart.byteCntMax = 0;
264 Uart.posCnt = 0;
265 Uart.syncBit = 9999;
266 }
267
268 void UartInit(uint8_t *data, uint8_t *parity)
269 {
270 Uart.output = data;
271 Uart.parity = parity;
272 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
273 UartReset();
274 }
275
276 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
277 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
278 {
279
280 Uart.fourBits = (Uart.fourBits << 8) | bit;
281
282 if (Uart.state == STATE_UNSYNCD) { // not yet synced
283
284 Uart.syncBit = 9999; // not set
285
286 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
287 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
288 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
289
290 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
291 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
292 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
293 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
294 //
295 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
296 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
297
298 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
299 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
300 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
301 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
302 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
303 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
304 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
305 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
306
307 if (Uart.syncBit != 9999) { // found a sync bit
308 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
309 Uart.startTime -= Uart.syncBit;
310 Uart.endTime = Uart.startTime;
311 Uart.state = STATE_START_OF_COMMUNICATION;
312 }
313
314 } else {
315
316 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
317 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
318 UartReset();
319 } else { // Modulation in first half = Sequence Z = logic "0"
320 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
321 UartReset();
322 } else {
323 Uart.bitCount++;
324 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
325 Uart.state = STATE_MILLER_Z;
326 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
327 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
328 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
329 Uart.parityBits <<= 1; // make room for the parity bit
330 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
331 Uart.bitCount = 0;
332 Uart.shiftReg = 0;
333 if((Uart.len&0x0007) == 0) { // every 8 data bytes
334 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
335 Uart.parityBits = 0;
336 }
337 }
338 }
339 }
340 } else {
341 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
342 Uart.bitCount++;
343 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
344 Uart.state = STATE_MILLER_X;
345 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
346 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
347 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
348 Uart.parityBits <<= 1; // make room for the new parity bit
349 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
350 Uart.bitCount = 0;
351 Uart.shiftReg = 0;
352 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
353 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
354 Uart.parityBits = 0;
355 }
356 }
357 } else { // no modulation in both halves - Sequence Y
358 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
359 Uart.state = STATE_UNSYNCD;
360 Uart.bitCount--; // last "0" was part of EOC sequence
361 Uart.shiftReg <<= 1; // drop it
362 if(Uart.bitCount > 0) { // if we decoded some bits
363 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
364 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
365 Uart.parityBits <<= 1; // add a (void) parity bit
366 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
367 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
368 return TRUE;
369 } else if (Uart.len & 0x0007) { // there are some parity bits to store
370 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
371 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
372 }
373 if (Uart.len) {
374 return TRUE; // we are finished with decoding the raw data sequence
375 } else {
376 UartReset(); // Nothing received - start over
377 }
378 }
379 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
380 UartReset();
381 } else { // a logic "0"
382 Uart.bitCount++;
383 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
384 Uart.state = STATE_MILLER_Y;
385 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
386 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
387 Uart.parityBits <<= 1; // make room for the parity bit
388 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
389 Uart.bitCount = 0;
390 Uart.shiftReg = 0;
391 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
392 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
393 Uart.parityBits = 0;
394 }
395 }
396 }
397 }
398 }
399
400 }
401
402 return FALSE; // not finished yet, need more data
403 }
404
405
406
407 //=============================================================================
408 // ISO 14443 Type A - Manchester decoder
409 //=============================================================================
410 // Basics:
411 // This decoder is used when the PM3 acts as a reader.
412 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
413 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
414 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
415 // The Manchester decoder needs to identify the following sequences:
416 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
417 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
418 // 8 ticks unmodulated: Sequence F = end of communication
419 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
420 // Note 1: the bitstream may start at any time. We therefore need to sync.
421 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
422 static tDemod Demod;
423
424 // Lookup-Table to decide if 4 raw bits are a modulation.
425 // We accept three or four "1" in any position
426 const bool Mod_Manchester_LUT[] = {
427 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
428 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
429 };
430
431 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
432 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
433
434
435 void DemodReset()
436 {
437 Demod.state = DEMOD_UNSYNCD;
438 Demod.len = 0; // number of decoded data bytes
439 Demod.parityLen = 0;
440 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
441 Demod.parityBits = 0; //
442 Demod.collisionPos = 0; // Position of collision bit
443 Demod.twoBits = 0xffff; // buffer for 2 Bits
444 Demod.highCnt = 0;
445 Demod.startTime = 0;
446 Demod.endTime = 0;
447
448 //
449 Demod.bitCount = 0;
450 Demod.syncBit = 0xFFFF;
451 Demod.samples = 0;
452 }
453
454 void DemodInit(uint8_t *data, uint8_t *parity)
455 {
456 Demod.output = data;
457 Demod.parity = parity;
458 DemodReset();
459 }
460
461 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
462 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
463 {
464
465 Demod.twoBits = (Demod.twoBits << 8) | bit;
466
467 if (Demod.state == DEMOD_UNSYNCD) {
468
469 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
470 if (Demod.twoBits == 0x0000) {
471 Demod.highCnt++;
472 } else {
473 Demod.highCnt = 0;
474 }
475 } else {
476 Demod.syncBit = 0xFFFF; // not set
477 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
478 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
479 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
480 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
481 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
482 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
483 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
484 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
485 if (Demod.syncBit != 0xFFFF) {
486 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
487 Demod.startTime -= Demod.syncBit;
488 Demod.bitCount = offset; // number of decoded data bits
489 Demod.state = DEMOD_MANCHESTER_DATA;
490 }
491 }
492
493 } else {
494
495 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
496 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
497 if (!Demod.collisionPos) {
498 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
499 }
500 } // modulation in first half only - Sequence D = 1
501 Demod.bitCount++;
502 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
503 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
504 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
505 Demod.parityBits <<= 1; // make room for the parity bit
506 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
507 Demod.bitCount = 0;
508 Demod.shiftReg = 0;
509 if((Demod.len&0x0007) == 0) { // every 8 data bytes
510 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
511 Demod.parityBits = 0;
512 }
513 }
514 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
515 } else { // no modulation in first half
516 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
517 Demod.bitCount++;
518 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
519 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
520 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
521 Demod.parityBits <<= 1; // make room for the new parity bit
522 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
523 Demod.bitCount = 0;
524 Demod.shiftReg = 0;
525 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
526 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
527 Demod.parityBits = 0;
528 }
529 }
530 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
531 } else { // no modulation in both halves - End of communication
532 if(Demod.bitCount > 0) { // there are some remaining data bits
533 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
534 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
535 Demod.parityBits <<= 1; // add a (void) parity bit
536 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
537 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
538 return TRUE;
539 } else if (Demod.len & 0x0007) { // there are some parity bits to store
540 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
541 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
542 }
543 if (Demod.len) {
544 return TRUE; // we are finished with decoding the raw data sequence
545 } else { // nothing received. Start over
546 DemodReset();
547 }
548 }
549 }
550 }
551 return FALSE; // not finished yet, need more data
552 }
553
554 //=============================================================================
555 // Finally, a `sniffer' for ISO 14443 Type A
556 // Both sides of communication!
557 //=============================================================================
558
559 //-----------------------------------------------------------------------------
560 // Record the sequence of commands sent by the reader to the tag, with
561 // triggering so that we start recording at the point that the tag is moved
562 // near the reader.
563 //-----------------------------------------------------------------------------
564 void RAMFUNC SniffIso14443a(uint8_t param) {
565 // param:
566 // bit 0 - trigger from first card answer
567 // bit 1 - trigger from first reader 7-bit request
568
569 LEDsoff();
570
571 // We won't start recording the frames that we acquire until we trigger;
572 // a good trigger condition to get started is probably when we see a
573 // response from the tag.
574 // triggered == FALSE -- to wait first for card
575 bool triggered = !(param & 0x03);
576
577 // Allocate memory from BigBuf for some buffers
578 // free all previous allocations first
579 BigBuf_free();
580
581 // The command (reader -> tag) that we're receiving.
582 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
583 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
584
585 // The response (tag -> reader) that we're receiving.
586 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
587 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
588
589 // The DMA buffer, used to stream samples from the FPGA
590 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
591
592 // init trace buffer
593 clear_trace();
594 set_tracing(TRUE);
595
596 uint8_t *data = dmaBuf;
597 uint8_t previous_data = 0;
598 int maxDataLen = 0;
599 int dataLen = 0;
600 bool TagIsActive = FALSE;
601 bool ReaderIsActive = FALSE;
602
603 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
604
605 // Set up the demodulator for tag -> reader responses.
606 DemodInit(receivedResponse, receivedResponsePar);
607
608 // Set up the demodulator for the reader -> tag commands
609 UartInit(receivedCmd, receivedCmdPar);
610
611 // Setup and start DMA.
612 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
613
614 // And now we loop, receiving samples.
615 for(uint32_t rsamples = 0; TRUE; ) {
616
617 if(BUTTON_PRESS()) {
618 DbpString("cancelled by button");
619 break;
620 }
621
622 LED_A_ON();
623 WDT_HIT();
624
625 int register readBufDataP = data - dmaBuf;
626 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
627 if (readBufDataP <= dmaBufDataP){
628 dataLen = dmaBufDataP - readBufDataP;
629 } else {
630 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
631 }
632 // test for length of buffer
633 if(dataLen > maxDataLen) {
634 maxDataLen = dataLen;
635 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
636 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
637 break;
638 }
639 }
640 if(dataLen < 1) continue;
641
642 // primary buffer was stopped( <-- we lost data!
643 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
644 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
645 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
646 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
647 }
648 // secondary buffer sets as primary, secondary buffer was stopped
649 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
650 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
651 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
652 }
653
654 LED_A_OFF();
655
656 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
657
658 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
659 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
660 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
661 LED_C_ON();
662
663 // check - if there is a short 7bit request from reader
664 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
665
666 if(triggered) {
667 if (!LogTrace(receivedCmd,
668 Uart.len,
669 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
670 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
671 Uart.parity,
672 TRUE)) break;
673 }
674 /* And ready to receive another command. */
675 UartReset();
676 //UartInit(receivedCmd, receivedCmdPar);
677 /* And also reset the demod code, which might have been */
678 /* false-triggered by the commands from the reader. */
679 DemodReset();
680 LED_B_OFF();
681 }
682 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
683 }
684
685 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
686 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
687 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
688 LED_B_ON();
689
690 if (!LogTrace(receivedResponse,
691 Demod.len,
692 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
693 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
694 Demod.parity,
695 FALSE)) break;
696
697 if ((!triggered) && (param & 0x01)) triggered = TRUE;
698
699 // And ready to receive another response.
700 DemodReset();
701 // And reset the Miller decoder including itS (now outdated) input buffer
702 UartInit(receivedCmd, receivedCmdPar);
703
704 LED_C_OFF();
705 }
706 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
707 }
708 }
709
710 previous_data = *data;
711 rsamples++;
712 data++;
713 if(data == dmaBuf + DMA_BUFFER_SIZE) {
714 data = dmaBuf;
715 }
716 } // main cycle
717
718 DbpString("COMMAND FINISHED");
719
720 FpgaDisableSscDma();
721 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
722 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
723 LEDsoff();
724 }
725
726 //-----------------------------------------------------------------------------
727 // Prepare tag messages
728 //-----------------------------------------------------------------------------
729 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
730 {
731 ToSendReset();
732
733 // Correction bit, might be removed when not needed
734 ToSendStuffBit(0);
735 ToSendStuffBit(0);
736 ToSendStuffBit(0);
737 ToSendStuffBit(0);
738 ToSendStuffBit(1); // 1
739 ToSendStuffBit(0);
740 ToSendStuffBit(0);
741 ToSendStuffBit(0);
742
743 // Send startbit
744 ToSend[++ToSendMax] = SEC_D;
745 LastProxToAirDuration = 8 * ToSendMax - 4;
746
747 for(uint16_t i = 0; i < len; i++) {
748 uint8_t b = cmd[i];
749
750 // Data bits
751 for(uint16_t j = 0; j < 8; j++) {
752 if(b & 1) {
753 ToSend[++ToSendMax] = SEC_D;
754 } else {
755 ToSend[++ToSendMax] = SEC_E;
756 }
757 b >>= 1;
758 }
759
760 // Get the parity bit
761 if (parity[i>>3] & (0x80>>(i&0x0007))) {
762 ToSend[++ToSendMax] = SEC_D;
763 LastProxToAirDuration = 8 * ToSendMax - 4;
764 } else {
765 ToSend[++ToSendMax] = SEC_E;
766 LastProxToAirDuration = 8 * ToSendMax;
767 }
768 }
769
770 // Send stopbit
771 ToSend[++ToSendMax] = SEC_F;
772
773 // Convert from last byte pos to length
774 ToSendMax++;
775 }
776
777 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
778 {
779 uint8_t par[MAX_PARITY_SIZE];
780
781 GetParity(cmd, len, par);
782 CodeIso14443aAsTagPar(cmd, len, par);
783 }
784
785
786 static void Code4bitAnswerAsTag(uint8_t cmd)
787 {
788 int i;
789
790 ToSendReset();
791
792 // Correction bit, might be removed when not needed
793 ToSendStuffBit(0);
794 ToSendStuffBit(0);
795 ToSendStuffBit(0);
796 ToSendStuffBit(0);
797 ToSendStuffBit(1); // 1
798 ToSendStuffBit(0);
799 ToSendStuffBit(0);
800 ToSendStuffBit(0);
801
802 // Send startbit
803 ToSend[++ToSendMax] = SEC_D;
804
805 uint8_t b = cmd;
806 for(i = 0; i < 4; i++) {
807 if(b & 1) {
808 ToSend[++ToSendMax] = SEC_D;
809 LastProxToAirDuration = 8 * ToSendMax - 4;
810 } else {
811 ToSend[++ToSendMax] = SEC_E;
812 LastProxToAirDuration = 8 * ToSendMax;
813 }
814 b >>= 1;
815 }
816
817 // Send stopbit
818 ToSend[++ToSendMax] = SEC_F;
819
820 // Convert from last byte pos to length
821 ToSendMax++;
822 }
823
824 //-----------------------------------------------------------------------------
825 // Wait for commands from reader
826 // Stop when button is pressed
827 // Or return TRUE when command is captured
828 //-----------------------------------------------------------------------------
829 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
830 {
831 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
832 // only, since we are receiving, not transmitting).
833 // Signal field is off with the appropriate LED
834 LED_D_OFF();
835 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
836
837 // Now run a `software UART' on the stream of incoming samples.
838 UartInit(received, parity);
839
840 // clear RXRDY:
841 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
842
843 for(;;) {
844 WDT_HIT();
845
846 if(BUTTON_PRESS()) return FALSE;
847
848 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
849 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
850 if(MillerDecoding(b, 0)) {
851 *len = Uart.len;
852 return TRUE;
853 }
854 }
855 }
856 }
857
858 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
859 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
860 int EmSend4bit(uint8_t resp);
861 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
862 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
863 int EmSendCmd(uint8_t *resp, uint16_t respLen);
864 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
865 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
866 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
867
868 static uint8_t* free_buffer_pointer;
869
870 typedef struct {
871 uint8_t* response;
872 size_t response_n;
873 uint8_t* modulation;
874 size_t modulation_n;
875 uint32_t ProxToAirDuration;
876 } tag_response_info_t;
877
878 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
879 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
880 // This will need the following byte array for a modulation sequence
881 // 144 data bits (18 * 8)
882 // 18 parity bits
883 // 2 Start and stop
884 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
885 // 1 just for the case
886 // ----------- +
887 // 166 bytes, since every bit that needs to be send costs us a byte
888 //
889
890
891 // Prepare the tag modulation bits from the message
892 CodeIso14443aAsTag(response_info->response,response_info->response_n);
893
894 // Make sure we do not exceed the free buffer space
895 if (ToSendMax > max_buffer_size) {
896 Dbprintf("Out of memory, when modulating bits for tag answer:");
897 Dbhexdump(response_info->response_n,response_info->response,false);
898 return false;
899 }
900
901 // Copy the byte array, used for this modulation to the buffer position
902 memcpy(response_info->modulation,ToSend,ToSendMax);
903
904 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
905 response_info->modulation_n = ToSendMax;
906 response_info->ProxToAirDuration = LastProxToAirDuration;
907
908 return true;
909 }
910
911
912 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
913 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
914 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
915 // -> need 273 bytes buffer
916 // 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits
917 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 370 //273
918
919 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
920 // Retrieve and store the current buffer index
921 response_info->modulation = free_buffer_pointer;
922
923 // Determine the maximum size we can use from our buffer
924 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
925
926 // Forward the prepare tag modulation function to the inner function
927 if (prepare_tag_modulation(response_info, max_buffer_size)) {
928 // Update the free buffer offset
929 free_buffer_pointer += ToSendMax;
930 return true;
931 } else {
932 return false;
933 }
934 }
935
936 //-----------------------------------------------------------------------------
937 // Main loop of simulated tag: receive commands from reader, decide what
938 // response to send, and send it.
939 //-----------------------------------------------------------------------------
940 void SimulateIso14443aTag(int tagType, int flags, int uid_2nd, byte_t* data)
941 {
942
943 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
944 // This can be used in a reader-only attack.
945 // (it can also be retrieved via 'hf 14a list', but hey...
946 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
947 uint8_t ar_nr_collected = 0;
948
949 uint8_t sak;
950
951 uint8_t blockzeros[512];
952 memset(blockzeros, 0x00, sizeof(blockzeros));
953
954 // PACK response to PWD AUTH for EV1/NTAG
955 uint8_t response8[4];
956
957 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
958 uint8_t response1[2];
959
960 switch (tagType) {
961 case 1: { // MIFARE Classic
962 // Says: I am Mifare 1k - original line
963 response1[0] = 0x04;
964 response1[1] = 0x00;
965 sak = 0x08;
966 } break;
967 case 2: { // MIFARE Ultralight
968 // Says: I am a stupid memory tag, no crypto
969 response1[0] = 0x44;
970 response1[1] = 0x00;
971 sak = 0x00;
972 } break;
973 case 3: { // MIFARE DESFire
974 // Says: I am a DESFire tag, ph33r me
975 response1[0] = 0x04;
976 response1[1] = 0x03;
977 sak = 0x20;
978 } break;
979 case 4: { // ISO/IEC 14443-4
980 // Says: I am a javacard (JCOP)
981 response1[0] = 0x04;
982 response1[1] = 0x00;
983 sak = 0x28;
984 } break;
985 case 5: { // MIFARE TNP3XXX
986 // Says: I am a toy
987 response1[0] = 0x01;
988 response1[1] = 0x0f;
989 sak = 0x01;
990 } break;
991 case 6: { // MIFARE Mini
992 // Says: I am a Mifare Mini, 320b
993 response1[0] = 0x44;
994 response1[1] = 0x00;
995 sak = 0x09;
996 } break;
997 case 7: { // NTAG?
998 // Says: I am a NTAG,
999 response1[0] = 0x44;
1000 response1[1] = 0x00;
1001 sak = 0x00;
1002 // PACK
1003 response8[0] = 0x80;
1004 response8[1] = 0x80;
1005 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
1006 } break;
1007 default: {
1008 Dbprintf("Error: unkown tagtype (%d)",tagType);
1009 return;
1010 } break;
1011 }
1012
1013 // The second response contains the (mandatory) first 24 bits of the UID
1014 uint8_t response2[5] = {0x00};
1015
1016 // Check if the uid uses the (optional) part
1017 uint8_t response2a[5] = {0x00};
1018
1019 if (flags & FLAG_7B_UID_IN_DATA) {
1020 response2[0] = 0x88;
1021 response2[1] = data[0];
1022 response2[2] = data[1];
1023 response2[3] = data[2];
1024
1025 response2a[0] = data[3];
1026 response2a[1] = data[4];
1027 response2a[2] = data[5];
1028 response2a[3] = data[6]; //??
1029 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1030
1031 // Configure the ATQA and SAK accordingly
1032 response1[0] |= 0x40;
1033 sak |= 0x04;
1034 } else {
1035 memcpy(response2, data, 4);
1036 //num_to_bytes(uid_1st,4,response2);
1037 // Configure the ATQA and SAK accordingly
1038 response1[0] &= 0xBF;
1039 sak &= 0xFB;
1040 }
1041
1042 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1043 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1044
1045 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1046 uint8_t response3[3] = {0x00};
1047 response3[0] = sak;
1048 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1049
1050 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1051 uint8_t response3a[3] = {0x00};
1052 response3a[0] = sak & 0xFB;
1053 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1054
1055 uint8_t response5[] = { 0x01, 0x01, 0x01, 0x01 }; // Very random tag nonce
1056 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1057 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1058 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1059 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1060 // TC(1) = 0x02: CID supported, NAD not supported
1061 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1062
1063 // Prepare GET_VERSION (different for EV-1 / NTAG)
1064 //uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
1065 uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
1066
1067 #define TAG_RESPONSE_COUNT 9
1068 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1069 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1070 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1071 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1072 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1073 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1074 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1075 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1076 { .response = response7_NTAG, .response_n = sizeof(response7_NTAG) }, // EV1/NTAG GET_VERSION response
1077 { .response = response8, .response_n = sizeof(response8) }, // EV1/NTAG PACK response
1078 };
1079
1080 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1081 // Such a response is less time critical, so we can prepare them on the fly
1082 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1083 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1084 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1085 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1086 tag_response_info_t dynamic_response_info = {
1087 .response = dynamic_response_buffer,
1088 .response_n = 0,
1089 .modulation = dynamic_modulation_buffer,
1090 .modulation_n = 0
1091 };
1092
1093 BigBuf_free_keep_EM();
1094
1095 // allocate buffers:
1096 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1097 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1098 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1099
1100 // clear trace
1101 clear_trace();
1102 set_tracing(TRUE);
1103
1104 // Prepare the responses of the anticollision phase
1105 // there will be not enough time to do this at the moment the reader sends it REQA
1106 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1107 prepare_allocated_tag_modulation(&responses[i]);
1108 }
1109
1110 int len = 0;
1111
1112 // To control where we are in the protocol
1113 int order = 0;
1114 int lastorder;
1115
1116 // Just to allow some checks
1117 int happened = 0;
1118 int happened2 = 0;
1119 int cmdsRecvd = 0;
1120
1121 // We need to listen to the high-frequency, peak-detected path.
1122 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1123
1124 cmdsRecvd = 0;
1125 tag_response_info_t* p_response;
1126
1127 LED_A_ON();
1128 for(;;) {
1129 // Clean receive command buffer
1130
1131 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1132 DbpString("Button press");
1133 break;
1134 }
1135
1136 p_response = NULL;
1137
1138 // Okay, look at the command now.
1139 lastorder = order;
1140 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1141 p_response = &responses[0]; order = 1;
1142 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1143 p_response = &responses[0]; order = 6;
1144 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1145 p_response = &responses[1]; order = 2;
1146 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1147 p_response = &responses[2]; order = 20;
1148 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1149 p_response = &responses[3]; order = 3;
1150 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1151 p_response = &responses[4]; order = 30;
1152 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1153 uint8_t block = receivedCmd[1];
1154 if ( tagType == 7 ) {
1155
1156 if ( block < 4 ) {
1157 //NTAG 215
1158 uint8_t start = 4 * block;
1159
1160 uint8_t blockdata[50] = {
1161 data[0],data[1],data[2], 0x88 ^ data[0] ^ data[1] ^ data[2],
1162 data[3],data[4],data[5],data[6],
1163 data[3] ^ data[4] ^ data[5] ^ data[6],0x48,0x0f,0xe0,
1164 0xe1,0x10,0x12,0x00,
1165 0x03,0x00,0xfe,0x00,
1166 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
1167 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
1168 0x00,0x00,0x00,0x00,
1169 0x00,0x00};
1170 ComputeCrc14443(CRC_14443_A, blockdata+start, 16, blockdata+start+17, blockdata+start+18);
1171 EmSendCmdEx( blockdata+start, 18, false);
1172 } else {
1173 ComputeCrc14443(CRC_14443_A, blockzeros,16, blockzeros+17,blockzeros+18);
1174 EmSendCmdEx(blockzeros,18,false);
1175 }
1176 p_response = NULL;
1177
1178 } else {
1179 EmSendCmdEx(data+(4*block),16,false);
1180 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1181 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1182 p_response = NULL;
1183 }
1184 } else if(receivedCmd[0] == 0x3A) { // Received a FAST READ -- just returns all zeros.
1185 uint8_t len = (receivedCmd[2]- receivedCmd[1] ) * 4;
1186 ComputeCrc14443(CRC_14443_A, blockzeros,len, blockzeros+len+1, blockzeros+len+2);
1187 EmSendCmdEx(blockzeros,len+2,false);
1188 p_response = NULL;
1189 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1190
1191 if (tracing) {
1192 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1193 }
1194 p_response = NULL;
1195 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1196
1197 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
1198 p_response = &responses[7];
1199 } else {
1200 p_response = &responses[5]; order = 7;
1201 }
1202 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1203 if (tagType == 1 || tagType == 2) { // RATS not supported
1204 EmSend4bit(CARD_NACK_NA);
1205 p_response = NULL;
1206 } else {
1207 p_response = &responses[6]; order = 70;
1208 }
1209 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1210 if (tracing) {
1211 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1212 }
1213 uint32_t nonce = bytes_to_num(response5,4);
1214 uint32_t nr = bytes_to_num(receivedCmd,4);
1215 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1216 //Dbprintf("Auth attempt {nonce}{nr}{ar}: %08x %08x %08x", nonce, nr, ar);
1217
1218 if(flags & FLAG_NR_AR_ATTACK )
1219 {
1220 if(ar_nr_collected < 2){
1221 // Avoid duplicates... probably not necessary, nr should vary.
1222 //if(ar_nr_responses[3] != nr){
1223 ar_nr_responses[ar_nr_collected*5] = 0;
1224 ar_nr_responses[ar_nr_collected*5+1] = 0;
1225 ar_nr_responses[ar_nr_collected*5+2] = nonce;
1226 ar_nr_responses[ar_nr_collected*5+3] = nr;
1227 ar_nr_responses[ar_nr_collected*5+4] = ar;
1228 ar_nr_collected++;
1229 //}
1230 }
1231
1232 if(ar_nr_collected > 1 ) {
1233
1234 if (MF_DBGLEVEL >= 2) {
1235 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
1236 Dbprintf("../tools/mfkey/mfkey32 %07x%08x %08x %08x %08x %08x %08x",
1237 ar_nr_responses[0], // UID1
1238 ar_nr_responses[1], // UID2
1239 ar_nr_responses[2], // NT
1240 ar_nr_responses[3], // AR1
1241 ar_nr_responses[4], // NR1
1242 ar_nr_responses[8], // AR2
1243 ar_nr_responses[9] // NR2
1244 );
1245 }
1246 uint8_t len = ar_nr_collected*5*4;
1247 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,len,0,&ar_nr_responses,len);
1248 ar_nr_collected = 0;
1249 memset(ar_nr_responses, 0x00, len);
1250 }
1251 }
1252 } else if (receivedCmd[0] == 0x1a ) // ULC authentication
1253 {
1254
1255 }
1256 else if (receivedCmd[0] == 0x1b) // NTAG / EV-1 authentication
1257 {
1258 if ( tagType == 7 ) {
1259 p_response = &responses[8]; // PACK response
1260 }
1261 }
1262 else {
1263 // Check for ISO 14443A-4 compliant commands, look at left nibble
1264 switch (receivedCmd[0]) {
1265
1266 case 0x0B:
1267 case 0x0A: { // IBlock (command)
1268 dynamic_response_info.response[0] = receivedCmd[0];
1269 dynamic_response_info.response[1] = 0x00;
1270 dynamic_response_info.response[2] = 0x90;
1271 dynamic_response_info.response[3] = 0x00;
1272 dynamic_response_info.response_n = 4;
1273 } break;
1274
1275 case 0x1A:
1276 case 0x1B: { // Chaining command
1277 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1278 dynamic_response_info.response_n = 2;
1279 } break;
1280
1281 case 0xaa:
1282 case 0xbb: {
1283 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1284 dynamic_response_info.response_n = 2;
1285 } break;
1286
1287 case 0xBA: { //
1288 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1289 dynamic_response_info.response_n = 2;
1290 } break;
1291
1292 case 0xCA:
1293 case 0xC2: { // Readers sends deselect command
1294 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1295 dynamic_response_info.response_n = 2;
1296 } break;
1297
1298 default: {
1299 // Never seen this command before
1300 if (tracing) {
1301 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1302 }
1303 Dbprintf("Received unknown command (len=%d):",len);
1304 Dbhexdump(len,receivedCmd,false);
1305 // Do not respond
1306 dynamic_response_info.response_n = 0;
1307 } break;
1308 }
1309
1310 if (dynamic_response_info.response_n > 0) {
1311 // Copy the CID from the reader query
1312 dynamic_response_info.response[1] = receivedCmd[1];
1313
1314 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1315 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1316 dynamic_response_info.response_n += 2;
1317
1318 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1319 Dbprintf("Error preparing tag response");
1320 if (tracing) {
1321 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1322 }
1323 break;
1324 }
1325 p_response = &dynamic_response_info;
1326 }
1327 }
1328
1329 // Count number of wakeups received after a halt
1330 if(order == 6 && lastorder == 5) { happened++; }
1331
1332 // Count number of other messages after a halt
1333 if(order != 6 && lastorder == 5) { happened2++; }
1334
1335 if(cmdsRecvd > 999) {
1336 DbpString("1000 commands later...");
1337 break;
1338 }
1339 cmdsRecvd++;
1340
1341 if (p_response != NULL) {
1342 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1343 // do the tracing for the previous reader request and this tag answer:
1344 uint8_t par[MAX_PARITY_SIZE];
1345 GetParity(p_response->response, p_response->response_n, par);
1346
1347 EmLogTrace(Uart.output,
1348 Uart.len,
1349 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1350 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1351 Uart.parity,
1352 p_response->response,
1353 p_response->response_n,
1354 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1355 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1356 par);
1357 }
1358
1359 if (!tracing) {
1360 Dbprintf("Trace Full. Simulation stopped.");
1361 break;
1362 }
1363 }
1364
1365 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1366
1367 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1368 LED_A_OFF();
1369 BigBuf_free_keep_EM();
1370 }
1371
1372
1373 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1374 // of bits specified in the delay parameter.
1375 void PrepareDelayedTransfer(uint16_t delay)
1376 {
1377 uint8_t bitmask = 0;
1378 uint8_t bits_to_shift = 0;
1379 uint8_t bits_shifted = 0;
1380
1381 delay &= 0x07;
1382 if (delay) {
1383 for (uint16_t i = 0; i < delay; i++) {
1384 bitmask |= (0x01 << i);
1385 }
1386 ToSend[ToSendMax++] = 0x00;
1387 for (uint16_t i = 0; i < ToSendMax; i++) {
1388 bits_to_shift = ToSend[i] & bitmask;
1389 ToSend[i] = ToSend[i] >> delay;
1390 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1391 bits_shifted = bits_to_shift;
1392 }
1393 }
1394 }
1395
1396
1397 //-------------------------------------------------------------------------------------
1398 // Transmit the command (to the tag) that was placed in ToSend[].
1399 // Parameter timing:
1400 // if NULL: transfer at next possible time, taking into account
1401 // request guard time and frame delay time
1402 // if == 0: transfer immediately and return time of transfer
1403 // if != 0: delay transfer until time specified
1404 //-------------------------------------------------------------------------------------
1405 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1406 {
1407
1408 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1409
1410 uint32_t ThisTransferTime = 0;
1411
1412 if (timing) {
1413 if(*timing == 0) { // Measure time
1414 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1415 } else {
1416 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1417 }
1418 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1419 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1420 LastTimeProxToAirStart = *timing;
1421 } else {
1422 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1423 while(GetCountSspClk() < ThisTransferTime);
1424 LastTimeProxToAirStart = ThisTransferTime;
1425 }
1426
1427 // clear TXRDY
1428 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1429
1430 uint16_t c = 0;
1431 for(;;) {
1432 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1433 AT91C_BASE_SSC->SSC_THR = cmd[c];
1434 c++;
1435 if(c >= len) {
1436 break;
1437 }
1438 }
1439 }
1440
1441 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1442 }
1443
1444
1445 //-----------------------------------------------------------------------------
1446 // Prepare reader command (in bits, support short frames) to send to FPGA
1447 //-----------------------------------------------------------------------------
1448 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1449 {
1450 int i, j;
1451 int last;
1452 uint8_t b;
1453
1454 ToSendReset();
1455
1456 // Start of Communication (Seq. Z)
1457 ToSend[++ToSendMax] = SEC_Z;
1458 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1459 last = 0;
1460
1461 size_t bytecount = nbytes(bits);
1462 // Generate send structure for the data bits
1463 for (i = 0; i < bytecount; i++) {
1464 // Get the current byte to send
1465 b = cmd[i];
1466 size_t bitsleft = MIN((bits-(i*8)),8);
1467
1468 for (j = 0; j < bitsleft; j++) {
1469 if (b & 1) {
1470 // Sequence X
1471 ToSend[++ToSendMax] = SEC_X;
1472 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1473 last = 1;
1474 } else {
1475 if (last == 0) {
1476 // Sequence Z
1477 ToSend[++ToSendMax] = SEC_Z;
1478 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1479 } else {
1480 // Sequence Y
1481 ToSend[++ToSendMax] = SEC_Y;
1482 last = 0;
1483 }
1484 }
1485 b >>= 1;
1486 }
1487
1488 // Only transmit parity bit if we transmitted a complete byte
1489 if (j == 8 && parity != NULL) {
1490 // Get the parity bit
1491 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1492 // Sequence X
1493 ToSend[++ToSendMax] = SEC_X;
1494 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1495 last = 1;
1496 } else {
1497 if (last == 0) {
1498 // Sequence Z
1499 ToSend[++ToSendMax] = SEC_Z;
1500 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1501 } else {
1502 // Sequence Y
1503 ToSend[++ToSendMax] = SEC_Y;
1504 last = 0;
1505 }
1506 }
1507 }
1508 }
1509
1510 // End of Communication: Logic 0 followed by Sequence Y
1511 if (last == 0) {
1512 // Sequence Z
1513 ToSend[++ToSendMax] = SEC_Z;
1514 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1515 } else {
1516 // Sequence Y
1517 ToSend[++ToSendMax] = SEC_Y;
1518 last = 0;
1519 }
1520 ToSend[++ToSendMax] = SEC_Y;
1521
1522 // Convert to length of command:
1523 ToSendMax++;
1524 }
1525
1526 //-----------------------------------------------------------------------------
1527 // Prepare reader command to send to FPGA
1528 //-----------------------------------------------------------------------------
1529 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1530 {
1531 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1532 }
1533
1534
1535 //-----------------------------------------------------------------------------
1536 // Wait for commands from reader
1537 // Stop when button is pressed (return 1) or field was gone (return 2)
1538 // Or return 0 when command is captured
1539 //-----------------------------------------------------------------------------
1540 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1541 {
1542 *len = 0;
1543
1544 uint32_t timer = 0, vtime = 0;
1545 int analogCnt = 0;
1546 int analogAVG = 0;
1547
1548 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1549 // only, since we are receiving, not transmitting).
1550 // Signal field is off with the appropriate LED
1551 LED_D_OFF();
1552 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1553
1554 // Set ADC to read field strength
1555 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1556 AT91C_BASE_ADC->ADC_MR =
1557 ADC_MODE_PRESCALE(63) |
1558 ADC_MODE_STARTUP_TIME(1) |
1559 ADC_MODE_SAMPLE_HOLD_TIME(15);
1560 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1561 // start ADC
1562 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1563
1564 // Now run a 'software UART' on the stream of incoming samples.
1565 UartInit(received, parity);
1566
1567 // Clear RXRDY:
1568 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1569
1570 for(;;) {
1571 WDT_HIT();
1572
1573 if (BUTTON_PRESS()) return 1;
1574
1575 // test if the field exists
1576 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1577 analogCnt++;
1578 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1579 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1580 if (analogCnt >= 32) {
1581 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1582 vtime = GetTickCount();
1583 if (!timer) timer = vtime;
1584 // 50ms no field --> card to idle state
1585 if (vtime - timer > 50) return 2;
1586 } else
1587 if (timer) timer = 0;
1588 analogCnt = 0;
1589 analogAVG = 0;
1590 }
1591 }
1592
1593 // receive and test the miller decoding
1594 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1595 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1596 if(MillerDecoding(b, 0)) {
1597 *len = Uart.len;
1598 return 0;
1599 }
1600 }
1601
1602 }
1603 }
1604
1605
1606 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1607 {
1608 uint8_t b;
1609 uint16_t i = 0;
1610 uint32_t ThisTransferTime;
1611
1612 // Modulate Manchester
1613 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1614
1615 // include correction bit if necessary
1616 if (Uart.parityBits & 0x01) {
1617 correctionNeeded = TRUE;
1618 }
1619 if(correctionNeeded) {
1620 // 1236, so correction bit needed
1621 i = 0;
1622 } else {
1623 i = 1;
1624 }
1625
1626 // clear receiving shift register and holding register
1627 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1628 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1629 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1630 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1631
1632 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1633 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1634 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1635 if (AT91C_BASE_SSC->SSC_RHR) break;
1636 }
1637
1638 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1639
1640 // Clear TXRDY:
1641 AT91C_BASE_SSC->SSC_THR = SEC_F;
1642
1643 // send cycle
1644 for(; i < respLen; ) {
1645 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1646 AT91C_BASE_SSC->SSC_THR = resp[i++];
1647 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1648 }
1649
1650 if(BUTTON_PRESS()) {
1651 break;
1652 }
1653 }
1654
1655 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1656 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1657 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1658 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1659 AT91C_BASE_SSC->SSC_THR = SEC_F;
1660 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1661 i++;
1662 }
1663 }
1664
1665 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1666
1667 return 0;
1668 }
1669
1670 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1671 Code4bitAnswerAsTag(resp);
1672 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1673 // do the tracing for the previous reader request and this tag answer:
1674 uint8_t par[1];
1675 GetParity(&resp, 1, par);
1676 EmLogTrace(Uart.output,
1677 Uart.len,
1678 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1679 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1680 Uart.parity,
1681 &resp,
1682 1,
1683 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1684 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1685 par);
1686 return res;
1687 }
1688
1689 int EmSend4bit(uint8_t resp){
1690 return EmSend4bitEx(resp, false);
1691 }
1692
1693 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1694 CodeIso14443aAsTagPar(resp, respLen, par);
1695 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1696 // do the tracing for the previous reader request and this tag answer:
1697 EmLogTrace(Uart.output,
1698 Uart.len,
1699 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1700 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1701 Uart.parity,
1702 resp,
1703 respLen,
1704 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1705 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1706 par);
1707 return res;
1708 }
1709
1710 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1711 uint8_t par[MAX_PARITY_SIZE];
1712 GetParity(resp, respLen, par);
1713 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1714 }
1715
1716 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1717 uint8_t par[MAX_PARITY_SIZE];
1718 GetParity(resp, respLen, par);
1719 return EmSendCmdExPar(resp, respLen, false, par);
1720 }
1721
1722 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1723 return EmSendCmdExPar(resp, respLen, false, par);
1724 }
1725
1726 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1727 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1728 {
1729 if (tracing) {
1730 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1731 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1732 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1733 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1734 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1735 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1736 reader_EndTime = tag_StartTime - exact_fdt;
1737 reader_StartTime = reader_EndTime - reader_modlen;
1738 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1739 return FALSE;
1740 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1741 } else {
1742 return TRUE;
1743 }
1744 }
1745
1746 //-----------------------------------------------------------------------------
1747 // Wait a certain time for tag response
1748 // If a response is captured return TRUE
1749 // If it takes too long return FALSE
1750 //-----------------------------------------------------------------------------
1751 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1752 {
1753 uint32_t c = 0x00;
1754
1755 // Set FPGA mode to "reader listen mode", no modulation (listen
1756 // only, since we are receiving, not transmitting).
1757 // Signal field is on with the appropriate LED
1758 LED_D_ON();
1759 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1760
1761 // Now get the answer from the card
1762 DemodInit(receivedResponse, receivedResponsePar);
1763
1764 // clear RXRDY:
1765 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1766
1767 for(;;) {
1768 WDT_HIT();
1769
1770 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1771 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1772 if(ManchesterDecoding(b, offset, 0)) {
1773 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1774 return TRUE;
1775 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1776 return FALSE;
1777 }
1778 }
1779 }
1780 }
1781
1782
1783 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1784 {
1785 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1786
1787 // Send command to tag
1788 TransmitFor14443a(ToSend, ToSendMax, timing);
1789 if(trigger)
1790 LED_A_ON();
1791
1792 // Log reader command in trace buffer
1793 if (tracing) {
1794 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1795 }
1796 }
1797
1798
1799 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1800 {
1801 ReaderTransmitBitsPar(frame, len*8, par, timing);
1802 }
1803
1804
1805 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1806 {
1807 // Generate parity and redirect
1808 uint8_t par[MAX_PARITY_SIZE];
1809 GetParity(frame, len/8, par);
1810 ReaderTransmitBitsPar(frame, len, par, timing);
1811 }
1812
1813
1814 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1815 {
1816 // Generate parity and redirect
1817 uint8_t par[MAX_PARITY_SIZE];
1818 GetParity(frame, len, par);
1819 ReaderTransmitBitsPar(frame, len*8, par, timing);
1820 }
1821
1822 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1823 {
1824 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1825 if (tracing) {
1826 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1827 }
1828 return Demod.len;
1829 }
1830
1831 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1832 {
1833 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1834 if (tracing) {
1835 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1836 }
1837 return Demod.len;
1838 }
1839
1840 /* performs iso14443a anticollision procedure
1841 * fills the uid pointer unless NULL
1842 * fills resp_data unless NULL */
1843 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1844 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1845 uint8_t sel_all[] = { 0x93,0x20 };
1846 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1847 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1848 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1849 uint8_t resp_par[MAX_PARITY_SIZE];
1850 byte_t uid_resp[4];
1851 size_t uid_resp_len;
1852
1853 uint8_t sak = 0x04; // cascade uid
1854 int cascade_level = 0;
1855 int len;
1856
1857 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1858 ReaderTransmitBitsPar(wupa,7,0, NULL);
1859
1860 // Receive the ATQA
1861 if(!ReaderReceive(resp, resp_par)) return 0;
1862
1863 if(p_hi14a_card) {
1864 memcpy(p_hi14a_card->atqa, resp, 2);
1865 p_hi14a_card->uidlen = 0;
1866 memset(p_hi14a_card->uid,0,10);
1867 }
1868
1869 // clear uid
1870 if (uid_ptr) {
1871 memset(uid_ptr,0,10);
1872 }
1873
1874 // check for proprietary anticollision:
1875 if ((resp[0] & 0x1F) == 0) {
1876 return 3;
1877 }
1878
1879 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1880 // which case we need to make a cascade 2 request and select - this is a long UID
1881 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1882 for(; sak & 0x04; cascade_level++) {
1883 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1884 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1885
1886 // SELECT_ALL
1887 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1888 if (!ReaderReceive(resp, resp_par)) return 0;
1889
1890 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1891 memset(uid_resp, 0, 4);
1892 uint16_t uid_resp_bits = 0;
1893 uint16_t collision_answer_offset = 0;
1894 // anti-collision-loop:
1895 while (Demod.collisionPos) {
1896 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1897 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1898 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1899 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1900 }
1901 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1902 uid_resp_bits++;
1903 // construct anticollosion command:
1904 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1905 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1906 sel_uid[2+i] = uid_resp[i];
1907 }
1908 collision_answer_offset = uid_resp_bits%8;
1909 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1910 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1911 }
1912 // finally, add the last bits and BCC of the UID
1913 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1914 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1915 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1916 }
1917
1918 } else { // no collision, use the response to SELECT_ALL as current uid
1919 memcpy(uid_resp, resp, 4);
1920 }
1921 uid_resp_len = 4;
1922
1923 // calculate crypto UID. Always use last 4 Bytes.
1924 if(cuid_ptr) {
1925 *cuid_ptr = bytes_to_num(uid_resp, 4);
1926 }
1927
1928 // Construct SELECT UID command
1929 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1930 memcpy(sel_uid+2, uid_resp, 4); // the UID
1931 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1932 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1933 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1934
1935 // Receive the SAK
1936 if (!ReaderReceive(resp, resp_par)) return 0;
1937 sak = resp[0];
1938
1939 // Test if more parts of the uid are coming
1940 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1941 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1942 // http://www.nxp.com/documents/application_note/AN10927.pdf
1943 uid_resp[0] = uid_resp[1];
1944 uid_resp[1] = uid_resp[2];
1945 uid_resp[2] = uid_resp[3];
1946
1947 uid_resp_len = 3;
1948 }
1949
1950 if(uid_ptr) {
1951 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1952 }
1953
1954 if(p_hi14a_card) {
1955 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1956 p_hi14a_card->uidlen += uid_resp_len;
1957 }
1958 }
1959
1960 if(p_hi14a_card) {
1961 p_hi14a_card->sak = sak;
1962 p_hi14a_card->ats_len = 0;
1963 }
1964
1965 // non iso14443a compliant tag
1966 if( (sak & 0x20) == 0) return 2;
1967
1968 // Request for answer to select
1969 AppendCrc14443a(rats, 2);
1970 ReaderTransmit(rats, sizeof(rats), NULL);
1971
1972 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1973
1974
1975 if(p_hi14a_card) {
1976 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1977 p_hi14a_card->ats_len = len;
1978 }
1979
1980 // reset the PCB block number
1981 iso14_pcb_blocknum = 0;
1982
1983 // set default timeout based on ATS
1984 iso14a_set_ATS_timeout(resp);
1985
1986 return 1;
1987 }
1988
1989 void iso14443a_setup(uint8_t fpga_minor_mode) {
1990 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1991 // Set up the synchronous serial port
1992 FpgaSetupSsc();
1993 // connect Demodulated Signal to ADC:
1994 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1995
1996 // Signal field is on with the appropriate LED
1997 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1998 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1999 LED_D_ON();
2000 } else {
2001 LED_D_OFF();
2002 }
2003 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
2004
2005 // Start the timer
2006 StartCountSspClk();
2007
2008 DemodReset();
2009 UartReset();
2010 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
2011 iso14a_set_timeout(10*106); // 10ms default
2012 }
2013
2014 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
2015 uint8_t parity[MAX_PARITY_SIZE];
2016 uint8_t real_cmd[cmd_len+4];
2017 real_cmd[0] = 0x0a; //I-Block
2018 // put block number into the PCB
2019 real_cmd[0] |= iso14_pcb_blocknum;
2020 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
2021 memcpy(real_cmd+2, cmd, cmd_len);
2022 AppendCrc14443a(real_cmd,cmd_len+2);
2023
2024 ReaderTransmit(real_cmd, cmd_len+4, NULL);
2025 size_t len = ReaderReceive(data, parity);
2026 uint8_t *data_bytes = (uint8_t *) data;
2027 if (!len)
2028 return 0; //DATA LINK ERROR
2029 // if we received an I- or R(ACK)-Block with a block number equal to the
2030 // current block number, toggle the current block number
2031 else if (len >= 4 // PCB+CID+CRC = 4 bytes
2032 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2033 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2034 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2035 {
2036 iso14_pcb_blocknum ^= 1;
2037 }
2038
2039 return len;
2040 }
2041
2042 //-----------------------------------------------------------------------------
2043 // Read an ISO 14443a tag. Send out commands and store answers.
2044 //
2045 //-----------------------------------------------------------------------------
2046 void ReaderIso14443a(UsbCommand *c)
2047 {
2048 iso14a_command_t param = c->arg[0];
2049 uint8_t *cmd = c->d.asBytes;
2050 size_t len = c->arg[1] & 0xffff;
2051 size_t lenbits = c->arg[1] >> 16;
2052 uint32_t timeout = c->arg[2];
2053 uint32_t arg0 = 0;
2054 byte_t buf[USB_CMD_DATA_SIZE];
2055 uint8_t par[MAX_PARITY_SIZE];
2056
2057 if(param & ISO14A_CONNECT) {
2058 clear_trace();
2059 }
2060
2061 set_tracing(TRUE);
2062
2063 if(param & ISO14A_REQUEST_TRIGGER) {
2064 iso14a_set_trigger(TRUE);
2065 }
2066
2067 if(param & ISO14A_CONNECT) {
2068 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
2069 if(!(param & ISO14A_NO_SELECT)) {
2070 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
2071 arg0 = iso14443a_select_card(NULL,card,NULL);
2072 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
2073 }
2074 }
2075
2076 if(param & ISO14A_SET_TIMEOUT) {
2077 iso14a_set_timeout(timeout);
2078 }
2079
2080 if(param & ISO14A_APDU) {
2081 arg0 = iso14_apdu(cmd, len, buf);
2082 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2083 }
2084
2085 if(param & ISO14A_RAW) {
2086 if(param & ISO14A_APPEND_CRC) {
2087 if(param & ISO14A_TOPAZMODE) {
2088 AppendCrc14443b(cmd,len);
2089 } else {
2090 AppendCrc14443a(cmd,len);
2091 }
2092 len += 2;
2093 if (lenbits) lenbits += 16;
2094 }
2095 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2096 if(param & ISO14A_TOPAZMODE) {
2097 int bits_to_send = lenbits;
2098 uint16_t i = 0;
2099 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2100 bits_to_send -= 7;
2101 while (bits_to_send > 0) {
2102 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2103 bits_to_send -= 8;
2104 }
2105 } else {
2106 GetParity(cmd, lenbits/8, par);
2107 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2108 }
2109 } else { // want to send complete bytes only
2110 if(param & ISO14A_TOPAZMODE) {
2111 uint16_t i = 0;
2112 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2113 while (i < len) {
2114 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2115 }
2116 } else {
2117 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2118 }
2119 }
2120 arg0 = ReaderReceive(buf, par);
2121 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2122 }
2123
2124 if(param & ISO14A_REQUEST_TRIGGER) {
2125 iso14a_set_trigger(FALSE);
2126 }
2127
2128 if(param & ISO14A_NO_DISCONNECT) {
2129 return;
2130 }
2131
2132 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2133 LEDsoff();
2134 }
2135
2136
2137 // Determine the distance between two nonces.
2138 // Assume that the difference is small, but we don't know which is first.
2139 // Therefore try in alternating directions.
2140 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2141
2142 if (nt1 == nt2) return 0;
2143
2144 uint16_t i;
2145 uint32_t nttmp1 = nt1;
2146 uint32_t nttmp2 = nt2;
2147
2148 for (i = 1; i < 32768; i++) {
2149 nttmp1 = prng_successor(nttmp1, 1);
2150 if (nttmp1 == nt2) return i;
2151 nttmp2 = prng_successor(nttmp2, 1);
2152 if (nttmp2 == nt1) return -i;
2153 }
2154
2155 return(-99999); // either nt1 or nt2 are invalid nonces
2156 }
2157
2158
2159 //-----------------------------------------------------------------------------
2160 // Recover several bits of the cypher stream. This implements (first stages of)
2161 // the algorithm described in "The Dark Side of Security by Obscurity and
2162 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2163 // (article by Nicolas T. Courtois, 2009)
2164 //-----------------------------------------------------------------------------
2165 void ReaderMifare(bool first_try) {
2166 // free eventually allocated BigBuf memory. We want all for tracing.
2167 BigBuf_free();
2168
2169 clear_trace();
2170 set_tracing(TRUE);
2171
2172 // Mifare AUTH
2173 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2174 uint8_t mf_nr_ar[8] = { 0x00 }; //{ 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01 };
2175 static uint8_t mf_nr_ar3 = 0;
2176
2177 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = { 0x00 };
2178 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = { 0x00 };
2179
2180 byte_t nt_diff = 0;
2181 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2182 static byte_t par_low = 0;
2183 bool led_on = TRUE;
2184 uint8_t uid[10] = {0x00};
2185 //uint32_t cuid = 0x00;
2186
2187 uint32_t nt = 0;
2188 uint32_t previous_nt = 0;
2189 static uint32_t nt_attacked = 0;
2190 byte_t par_list[8] = {0x00};
2191 byte_t ks_list[8] = {0x00};
2192
2193 static uint32_t sync_time = 0;
2194 static uint32_t sync_cycles = 0;
2195 int catch_up_cycles = 0;
2196 int last_catch_up = 0;
2197 uint16_t consecutive_resyncs = 0;
2198 int isOK = 0;
2199
2200 int numWrongDistance = 0;
2201
2202 if (first_try) {
2203 mf_nr_ar3 = 0;
2204 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2205 sync_time = GetCountSspClk() & 0xfffffff8;
2206 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2207 nt_attacked = 0;
2208 nt = 0;
2209 par[0] = 0;
2210 }
2211 else {
2212 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2213 mf_nr_ar3++;
2214 mf_nr_ar[3] = mf_nr_ar3;
2215 par[0] = par_low;
2216 }
2217
2218 LED_A_ON();
2219 LED_B_OFF();
2220 LED_C_OFF();
2221 LED_C_ON();
2222
2223 for(uint16_t i = 0; TRUE; i++) {
2224
2225 WDT_HIT();
2226
2227 // Test if the action was cancelled
2228 if(BUTTON_PRESS()) break;
2229
2230 if (numWrongDistance > 1000) {
2231 isOK = 0;
2232 break;
2233 }
2234
2235 //if(!iso14443a_select_card(uid, NULL, &cuid)) {
2236 if(!iso14443a_select_card(uid, NULL, NULL)) {
2237 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2238 continue;
2239 }
2240
2241 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2242 catch_up_cycles = 0;
2243
2244 // if we missed the sync time already, advance to the next nonce repeat
2245 while(GetCountSspClk() > sync_time) {
2246 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2247 }
2248
2249 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2250 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2251
2252 // Receive the (4 Byte) "random" nonce
2253 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2254 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2255 continue;
2256 }
2257
2258 previous_nt = nt;
2259 nt = bytes_to_num(receivedAnswer, 4);
2260
2261 // Transmit reader nonce with fake par
2262 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2263
2264 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2265 int nt_distance = dist_nt(previous_nt, nt);
2266 if (nt_distance == 0) {
2267 nt_attacked = nt;
2268 }
2269 else {
2270
2271 // invalid nonce received, try again
2272 if (nt_distance == -99999) {
2273 numWrongDistance++;
2274 if (MF_DBGLEVEL >= 3) Dbprintf("The two nonces has invalid distance, tag could have good PRNG\n");
2275 continue;
2276 }
2277
2278 sync_cycles = (sync_cycles - nt_distance);
2279 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2280 continue;
2281 }
2282 }
2283
2284 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2285 catch_up_cycles = -dist_nt(nt_attacked, nt);
2286 if (catch_up_cycles >= 99999) { // invalid nonce received. Don't resync on that one.
2287 catch_up_cycles = 0;
2288 continue;
2289 }
2290 if (catch_up_cycles == last_catch_up) {
2291 consecutive_resyncs++;
2292 }
2293 else {
2294 last_catch_up = catch_up_cycles;
2295 consecutive_resyncs = 0;
2296 }
2297 if (consecutive_resyncs < 3) {
2298 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2299 }
2300 else {
2301 sync_cycles = sync_cycles + catch_up_cycles;
2302 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2303 }
2304 continue;
2305 }
2306
2307 consecutive_resyncs = 0;
2308
2309 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2310 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
2311 {
2312 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2313
2314 if (nt_diff == 0)
2315 {
2316 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2317 }
2318
2319 led_on = !led_on;
2320 if(led_on) LED_B_ON(); else LED_B_OFF();
2321
2322 par_list[nt_diff] = SwapBits(par[0], 8);
2323 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2324
2325 // Test if the information is complete
2326 if (nt_diff == 0x07) {
2327 isOK = 1;
2328 break;
2329 }
2330
2331 nt_diff = (nt_diff + 1) & 0x07;
2332 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2333 par[0] = par_low;
2334 } else {
2335 if (nt_diff == 0 && first_try)
2336 {
2337 par[0]++;
2338 } else {
2339 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2340 }
2341 }
2342 }
2343
2344 mf_nr_ar[3] &= 0x1F;
2345
2346 byte_t buf[28] = {0x00};
2347
2348 memcpy(buf + 0, uid, 4);
2349 num_to_bytes(nt, 4, buf + 4);
2350 memcpy(buf + 8, par_list, 8);
2351 memcpy(buf + 16, ks_list, 8);
2352 memcpy(buf + 24, mf_nr_ar, 4);
2353
2354 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2355
2356 set_tracing(FALSE);
2357 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2358 LEDsoff();
2359 }
2360
2361
2362 /*
2363 *MIFARE 1K simulate.
2364 *
2365 *@param flags :
2366 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2367 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2368 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2369 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2370 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2371 */
2372 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2373 {
2374 int cardSTATE = MFEMUL_NOFIELD;
2375 int _7BUID = 0;
2376 int vHf = 0; // in mV
2377 int res;
2378 uint32_t selTimer = 0;
2379 uint32_t authTimer = 0;
2380 uint16_t len = 0;
2381 uint8_t cardWRBL = 0;
2382 uint8_t cardAUTHSC = 0;
2383 uint8_t cardAUTHKEY = 0xff; // no authentication
2384 // uint32_t cardRr = 0;
2385 uint32_t cuid = 0;
2386 //uint32_t rn_enc = 0;
2387 uint32_t ans = 0;
2388 uint32_t cardINTREG = 0;
2389 uint8_t cardINTBLOCK = 0;
2390 struct Crypto1State mpcs = {0, 0};
2391 struct Crypto1State *pcs;
2392 pcs = &mpcs;
2393 uint32_t numReads = 0;//Counts numer of times reader read a block
2394 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2395 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2396 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2397 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2398
2399 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2400 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2401 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2402 //uint8_t rSAK[] = {0x08, 0xb6, 0xdd}; // Mifare Classic
2403 uint8_t rSAK[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
2404 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2405
2406 uint8_t rAUTH_NT[] = {0x01, 0x01, 0x01, 0x01};
2407 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2408
2409 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2410 // This can be used in a reader-only attack.
2411 // (it can also be retrieved via 'hf 14a list', but hey...
2412 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
2413 uint8_t ar_nr_collected = 0;
2414
2415 // free eventually allocated BigBuf memory but keep Emulator Memory
2416 BigBuf_free_keep_EM();
2417
2418 // clear trace
2419 clear_trace();
2420 set_tracing(TRUE);
2421
2422 // Authenticate response - nonce
2423 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2424
2425 //-- Determine the UID
2426 // Can be set from emulator memory, incoming data
2427 // and can be 7 or 4 bytes long
2428 if (flags & FLAG_4B_UID_IN_DATA)
2429 {
2430 // 4B uid comes from data-portion of packet
2431 memcpy(rUIDBCC1,datain,4);
2432 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2433
2434 } else if (flags & FLAG_7B_UID_IN_DATA) {
2435 // 7B uid comes from data-portion of packet
2436 memcpy(&rUIDBCC1[1],datain,3);
2437 memcpy(rUIDBCC2, datain+3, 4);
2438 _7BUID = true;
2439 } else {
2440 // get UID from emul memory
2441 emlGetMemBt(receivedCmd, 7, 1);
2442 _7BUID = !(receivedCmd[0] == 0x00);
2443 if (!_7BUID) { // ---------- 4BUID
2444 emlGetMemBt(rUIDBCC1, 0, 4);
2445 } else { // ---------- 7BUID
2446 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2447 emlGetMemBt(rUIDBCC2, 3, 4);
2448 }
2449 }
2450
2451 // save uid.
2452 ar_nr_responses[0*5] = bytes_to_num(rUIDBCC1+1, 3);
2453 if ( _7BUID )
2454 ar_nr_responses[0*5+1] = bytes_to_num(rUIDBCC2, 4);
2455
2456 /*
2457 * Regardless of what method was used to set the UID, set fifth byte and modify
2458 * the ATQA for 4 or 7-byte UID
2459 */
2460 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2461 if (_7BUID) {
2462 rATQA[0] = 0x44;
2463 rUIDBCC1[0] = 0x88;
2464 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2465 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2466 }
2467
2468 // We need to listen to the high-frequency, peak-detected path.
2469 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2470
2471
2472 if (MF_DBGLEVEL >= 1) {
2473 if (!_7BUID) {
2474 Dbprintf("4B UID: %02x%02x%02x%02x",
2475 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2476 } else {
2477 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2478 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2479 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2480 }
2481 }
2482
2483 bool finished = FALSE;
2484 while (!BUTTON_PRESS() && !finished) {
2485 WDT_HIT();
2486
2487 // find reader field
2488 if (cardSTATE == MFEMUL_NOFIELD) {
2489 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2490 if (vHf > MF_MINFIELDV) {
2491 cardSTATE_TO_IDLE();
2492 LED_A_ON();
2493 }
2494 }
2495 if(cardSTATE == MFEMUL_NOFIELD) continue;
2496
2497 //Now, get data
2498 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2499 if (res == 2) { //Field is off!
2500 cardSTATE = MFEMUL_NOFIELD;
2501 LEDsoff();
2502 continue;
2503 } else if (res == 1) {
2504 break; //return value 1 means button press
2505 }
2506
2507 // REQ or WUP request in ANY state and WUP in HALTED state
2508 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2509 selTimer = GetTickCount();
2510 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2511 cardSTATE = MFEMUL_SELECT1;
2512
2513 // init crypto block
2514 LED_B_OFF();
2515 LED_C_OFF();
2516 crypto1_destroy(pcs);
2517 cardAUTHKEY = 0xff;
2518 continue;
2519 }
2520
2521 switch (cardSTATE) {
2522 case MFEMUL_NOFIELD:
2523 case MFEMUL_HALTED:
2524 case MFEMUL_IDLE:{
2525 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2526 break;
2527 }
2528 case MFEMUL_SELECT1:{
2529 // select all
2530 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2531 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2532 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2533 break;
2534 }
2535
2536 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2537 {
2538 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2539 }
2540 // select card
2541 if (len == 9 &&
2542 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2543 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2544 cuid = bytes_to_num(rUIDBCC1, 4);
2545 if (!_7BUID) {
2546 cardSTATE = MFEMUL_WORK;
2547 LED_B_ON();
2548 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2549 break;
2550 } else {
2551 cardSTATE = MFEMUL_SELECT2;
2552 }
2553 }
2554 break;
2555 }
2556 case MFEMUL_AUTH1:{
2557 if( len != 8)
2558 {
2559 cardSTATE_TO_IDLE();
2560 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2561 break;
2562 }
2563
2564 uint32_t ar = bytes_to_num(receivedCmd, 4);
2565 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2566
2567 //Collect AR/NR
2568 //if(ar_nr_collected < 2 && cardAUTHSC == 2){
2569 if(ar_nr_collected < 2){
2570 if(ar_nr_responses[2] != ar)
2571 {// Avoid duplicates... probably not necessary, ar should vary.
2572 //ar_nr_responses[ar_nr_collected*5] = 0;
2573 //ar_nr_responses[ar_nr_collected*5+1] = 0;
2574 ar_nr_responses[ar_nr_collected*5+2] = nonce;
2575 ar_nr_responses[ar_nr_collected*5+3] = nr;
2576 ar_nr_responses[ar_nr_collected*5+4] = ar;
2577 ar_nr_collected++;
2578 }
2579 // Interactive mode flag, means we need to send ACK
2580 if(flags & FLAG_INTERACTIVE && ar_nr_collected == 2)
2581 {
2582 finished = true;
2583 }
2584 }
2585
2586 // --- crypto
2587 //crypto1_word(pcs, ar , 1);
2588 //cardRr = nr ^ crypto1_word(pcs, 0, 0);
2589
2590 //test if auth OK
2591 //if (cardRr != prng_successor(nonce, 64)){
2592
2593 //if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2594 // cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2595 // cardRr, prng_successor(nonce, 64));
2596 // Shouldn't we respond anything here?
2597 // Right now, we don't nack or anything, which causes the
2598 // reader to do a WUPA after a while. /Martin
2599 // -- which is the correct response. /piwi
2600 //cardSTATE_TO_IDLE();
2601 //LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2602 //break;
2603 //}
2604
2605 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2606
2607 num_to_bytes(ans, 4, rAUTH_AT);
2608 // --- crypto
2609 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2610 LED_C_ON();
2611 cardSTATE = MFEMUL_WORK;
2612 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2613 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2614 GetTickCount() - authTimer);
2615 break;
2616 }
2617 case MFEMUL_SELECT2:{
2618 if (!len) {
2619 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2620 break;
2621 }
2622 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2623 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2624 break;
2625 }
2626
2627 // select 2 card
2628 if (len == 9 &&
2629 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2630 EmSendCmd(rSAK, sizeof(rSAK));
2631 cuid = bytes_to_num(rUIDBCC2, 4);
2632 cardSTATE = MFEMUL_WORK;
2633 LED_B_ON();
2634 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2635 break;
2636 }
2637
2638 // i guess there is a command). go into the work state.
2639 if (len != 4) {
2640 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2641 break;
2642 }
2643 cardSTATE = MFEMUL_WORK;
2644 //goto lbWORK;
2645 //intentional fall-through to the next case-stmt
2646 }
2647
2648 case MFEMUL_WORK:{
2649 if (len == 0) {
2650 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2651 break;
2652 }
2653
2654 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2655
2656 if(encrypted_data) {
2657 // decrypt seqence
2658 mf_crypto1_decrypt(pcs, receivedCmd, len);
2659 }
2660
2661 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2662 authTimer = GetTickCount();
2663 cardAUTHSC = receivedCmd[1] / 4; // received block num
2664 cardAUTHKEY = receivedCmd[0] - 0x60;
2665 crypto1_destroy(pcs);//Added by martin
2666 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2667
2668 if (!encrypted_data) { // first authentication
2669 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2670
2671 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2672 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2673 } else { // nested authentication
2674 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2675 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2676 num_to_bytes(ans, 4, rAUTH_AT);
2677 }
2678
2679 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2680 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2681 cardSTATE = MFEMUL_AUTH1;
2682 break;
2683 }
2684
2685 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2686 // BUT... ACK --> NACK
2687 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2688 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2689 break;
2690 }
2691
2692 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2693 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2694 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2695 break;
2696 }
2697
2698 if(len != 4) {
2699 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2700 break;
2701 }
2702
2703 if(receivedCmd[0] == 0x30 // read block
2704 || receivedCmd[0] == 0xA0 // write block
2705 || receivedCmd[0] == 0xC0 // inc
2706 || receivedCmd[0] == 0xC1 // dec
2707 || receivedCmd[0] == 0xC2 // restore
2708 || receivedCmd[0] == 0xB0) { // transfer
2709 if (receivedCmd[1] >= 16 * 4) {
2710 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2711 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2712 break;
2713 }
2714
2715 if (receivedCmd[1] / 4 != cardAUTHSC) {
2716 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2717 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2718 break;
2719 }
2720 }
2721 // read block
2722 if (receivedCmd[0] == 0x30) {
2723 if (MF_DBGLEVEL >= 4) {
2724 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2725 }
2726 emlGetMem(response, receivedCmd[1], 1);
2727 AppendCrc14443a(response, 16);
2728 mf_crypto1_encrypt(pcs, response, 18, response_par);
2729 EmSendCmdPar(response, 18, response_par);
2730 numReads++;
2731 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
2732 Dbprintf("%d reads done, exiting", numReads);
2733 finished = true;
2734 }
2735 break;
2736 }
2737 // write block
2738 if (receivedCmd[0] == 0xA0) {
2739 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2740 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2741 cardSTATE = MFEMUL_WRITEBL2;
2742 cardWRBL = receivedCmd[1];
2743 break;
2744 }
2745 // increment, decrement, restore
2746 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2747 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2748 if (emlCheckValBl(receivedCmd[1])) {
2749 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2750 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2751 break;
2752 }
2753 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2754 if (receivedCmd[0] == 0xC1)
2755 cardSTATE = MFEMUL_INTREG_INC;
2756 if (receivedCmd[0] == 0xC0)
2757 cardSTATE = MFEMUL_INTREG_DEC;
2758 if (receivedCmd[0] == 0xC2)
2759 cardSTATE = MFEMUL_INTREG_REST;
2760 cardWRBL = receivedCmd[1];
2761 break;
2762 }
2763 // transfer
2764 if (receivedCmd[0] == 0xB0) {
2765 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2766 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2767 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2768 else
2769 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2770 break;
2771 }
2772 // halt
2773 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2774 LED_B_OFF();
2775 LED_C_OFF();
2776 cardSTATE = MFEMUL_HALTED;
2777 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2778 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2779 break;
2780 }
2781 // RATS
2782 if (receivedCmd[0] == 0xe0) {//RATS
2783 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2784 break;
2785 }
2786 // command not allowed
2787 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2788 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2789 break;
2790 }
2791 case MFEMUL_WRITEBL2:{
2792 if (len == 18){
2793 mf_crypto1_decrypt(pcs, receivedCmd, len);
2794 emlSetMem(receivedCmd, cardWRBL, 1);
2795 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2796 cardSTATE = MFEMUL_WORK;
2797 } else {
2798 cardSTATE_TO_IDLE();
2799 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2800 }
2801 break;
2802 }
2803
2804 case MFEMUL_INTREG_INC:{
2805 mf_crypto1_decrypt(pcs, receivedCmd, len);
2806 memcpy(&ans, receivedCmd, 4);
2807 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2808 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2809 cardSTATE_TO_IDLE();
2810 break;
2811 }
2812 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2813 cardINTREG = cardINTREG + ans;
2814 cardSTATE = MFEMUL_WORK;
2815 break;
2816 }
2817 case MFEMUL_INTREG_DEC:{
2818 mf_crypto1_decrypt(pcs, receivedCmd, len);
2819 memcpy(&ans, receivedCmd, 4);
2820 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2821 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2822 cardSTATE_TO_IDLE();
2823 break;
2824 }
2825 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2826 cardINTREG = cardINTREG - ans;
2827 cardSTATE = MFEMUL_WORK;
2828 break;
2829 }
2830 case MFEMUL_INTREG_REST:{
2831 mf_crypto1_decrypt(pcs, receivedCmd, len);
2832 memcpy(&ans, receivedCmd, 4);
2833 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2834 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2835 cardSTATE_TO_IDLE();
2836 break;
2837 }
2838 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2839 cardSTATE = MFEMUL_WORK;
2840 break;
2841 }
2842 }
2843 }
2844
2845 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2846 LEDsoff();
2847
2848 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2849 {
2850 //May just aswell send the collected ar_nr in the response aswell
2851 uint8_t len = ar_nr_collected*5*4;
2852 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
2853 }
2854
2855 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1 )
2856 {
2857 if(ar_nr_collected > 1 ) {
2858 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2859 Dbprintf("../tools/mfkey/mfkey32 %06x%08x %08x %08x %08x %08x %08x",
2860 ar_nr_responses[0], // UID1
2861 ar_nr_responses[1], // UID2
2862 ar_nr_responses[2], // NT
2863 ar_nr_responses[3], // AR1
2864 ar_nr_responses[4], // NR1
2865 ar_nr_responses[8], // AR2
2866 ar_nr_responses[9] // NR2
2867 );
2868 } else {
2869 Dbprintf("Failed to obtain two AR/NR pairs!");
2870 if(ar_nr_collected > 0 ) {
2871 Dbprintf("Only got these: UID=%07x%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2872 ar_nr_responses[0], // UID1
2873 ar_nr_responses[1], // UID2
2874 ar_nr_responses[2], // NT
2875 ar_nr_responses[3], // AR1
2876 ar_nr_responses[4] // NR1
2877 );
2878 }
2879 }
2880 }
2881 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2882 }
2883
2884
2885 //-----------------------------------------------------------------------------
2886 // MIFARE sniffer.
2887 //
2888 //-----------------------------------------------------------------------------
2889 void RAMFUNC SniffMifare(uint8_t param) {
2890 // param:
2891 // bit 0 - trigger from first card answer
2892 // bit 1 - trigger from first reader 7-bit request
2893
2894 // free eventually allocated BigBuf memory
2895 BigBuf_free();
2896
2897 // C(red) A(yellow) B(green)
2898 LEDsoff();
2899 // init trace buffer
2900 clear_trace();
2901 set_tracing(TRUE);
2902
2903 // The command (reader -> tag) that we're receiving.
2904 // The length of a received command will in most cases be no more than 18 bytes.
2905 // So 32 should be enough!
2906 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2907 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2908 // The response (tag -> reader) that we're receiving.
2909 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2910 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2911
2912 // allocate the DMA buffer, used to stream samples from the FPGA
2913 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2914 uint8_t *data = dmaBuf;
2915 uint8_t previous_data = 0;
2916 int maxDataLen = 0;
2917 int dataLen = 0;
2918 bool ReaderIsActive = FALSE;
2919 bool TagIsActive = FALSE;
2920
2921 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2922
2923 // Set up the demodulator for tag -> reader responses.
2924 DemodInit(receivedResponse, receivedResponsePar);
2925
2926 // Set up the demodulator for the reader -> tag commands
2927 UartInit(receivedCmd, receivedCmdPar);
2928
2929 // Setup for the DMA.
2930 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2931
2932 LED_D_OFF();
2933
2934 // init sniffer
2935 MfSniffInit();
2936
2937 // And now we loop, receiving samples.
2938 for(uint32_t sniffCounter = 0; TRUE; ) {
2939
2940 if(BUTTON_PRESS()) {
2941 DbpString("cancelled by button");
2942 break;
2943 }
2944
2945 LED_A_ON();
2946 WDT_HIT();
2947
2948 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2949 // check if a transaction is completed (timeout after 2000ms).
2950 // if yes, stop the DMA transfer and send what we have so far to the client
2951 if (MfSniffSend(2000)) {
2952 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2953 sniffCounter = 0;
2954 data = dmaBuf;
2955 maxDataLen = 0;
2956 ReaderIsActive = FALSE;
2957 TagIsActive = FALSE;
2958 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2959 }
2960 }
2961
2962 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2963 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2964 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2965 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2966 } else {
2967 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2968 }
2969 // test for length of buffer
2970 if(dataLen > maxDataLen) { // we are more behind than ever...
2971 maxDataLen = dataLen;
2972 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2973 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2974 break;
2975 }
2976 }
2977 if(dataLen < 1) continue;
2978
2979 // primary buffer was stopped ( <-- we lost data!
2980 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2981 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2982 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2983 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2984 }
2985 // secondary buffer sets as primary, secondary buffer was stopped
2986 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2987 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2988 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2989 }
2990
2991 LED_A_OFF();
2992
2993 if (sniffCounter & 0x01) {
2994
2995 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2996 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2997 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2998 LED_C_INV();
2999 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
3000
3001 /* And ready to receive another command. */
3002 //UartInit(receivedCmd, receivedCmdPar);
3003 UartReset();
3004
3005 /* And also reset the demod code */
3006 DemodReset();
3007 }
3008 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3009 }
3010
3011 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
3012 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3013 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3014 LED_C_INV();
3015
3016 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
3017
3018 // And ready to receive another response.
3019 DemodReset();
3020
3021 // And reset the Miller decoder including its (now outdated) input buffer
3022 UartInit(receivedCmd, receivedCmdPar);
3023 }
3024 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3025 }
3026 }
3027
3028 previous_data = *data;
3029 sniffCounter++;
3030 data++;
3031 if(data == dmaBuf + DMA_BUFFER_SIZE) {
3032 data = dmaBuf;
3033 }
3034
3035 } // main cycle
3036
3037 DbpString("COMMAND FINISHED");
3038
3039 FpgaDisableSscDma();
3040 MfSniffEnd();
3041
3042 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3043 LEDsoff();
3044 }
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